CN102569240A - Double-row pad layout structure - Google Patents
Double-row pad layout structure Download PDFInfo
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- CN102569240A CN102569240A CN2012100489983A CN201210048998A CN102569240A CN 102569240 A CN102569240 A CN 102569240A CN 2012100489983 A CN2012100489983 A CN 2012100489983A CN 201210048998 A CN201210048998 A CN 201210048998A CN 102569240 A CN102569240 A CN 102569240A
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- pad
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- output control
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to a double-row pad layout structure, which first relates to a chip. The chip comprises a core region and a pad loop region, wherein the core region is positioned at the center of the chip; the pad loop region is positioned around the core region; a core functional module is arranged in the core region; the pad loop region is divided into an internal pad loop region and an external pad loop region as well as an input and output control logical circuit; the internal pad loop region and the external pad loop region both comprise packaging leading wire pads and pad driving circuits; and the internal pad loop region and the external pad loop region are respectively arranged on the two sides of the input and output control logical circuit. The double-row pad layout structure provided by the invention has the advantages of simpler integral circuit and less control circuit buses; moreover, for high voltage application, even though an additional level transferring device is not needed in the circuit, the maximum layout in the pad layout structure can be also realized.
Description
Technical field
the present invention relates to a kind of layout structure of pad, especially a kind of layout structure of double pad.
Background technology
relate generally to the pad layout structure in the design that many chip periphery connect; These layout structures generally are made up of pad and driver circuit; Said chip comprises the nuclear district that is positioned at the center and is positioned at pad loop wire zone on every side, said nuclear district; The pad structure of design in this manner can bear static release device (owing to will comprise static release device, so require the pad structure can be bigger usually) under the big situation of pad structure.Owing to, therefore in chip design, generally need a less pad gap if a plurality of pad cell are set need take zones a large amount of on the chip.For chip with high number of pins; At least certain pad gap can cause under the certain situation of number of pins, pad being laid in certain at least chip area; In this case; Please refer to the layout structure of the said at present common single pad of Fig. 1, Fig. 1 has only shown the layout structure in the pad loop wire zone that is positioned at said nuclear district one side, and the final area of said chip can be subject to the size of pad.In order to improve the area utilization of chip nuclear, reduce the waste of inner wasted space, chip area is preferably determined by the nuclear in the chip.
if when bonding pads becomes single layout, and this will cause at the nuclear region memory at more redundant area, and will be as shown in Figure 1; If when thus welding disking area being double layout; As shown in Figure 2, will significantly reduce redundant area, improved the nuclear utilance.This layout structure is common for the drive electrode that shows, promptly said pad loop wire directly with chip on the kernel function module be connected, thereby be used to transmit signal.In existing two rows' the pad layout structure, each row's pad all is staggered on their position, when the one side at chip increases the number of pad, just can carry out integral layout with acceptable pad gap thus.
In
above-mentioned double layout, though the structure of said pad layout has produced advantage, still have a lot of problems, complicated such as whole circuit, the control signal bus is bigger; Moreover; For high voltage applications; Need level shifter be set at the pad line-internal; Because the transistor of high pressure layout requirement same-type with layout together, so the line number signal between N type and P transistor npn npn will become very big, this causes needing in the said pad circuit Butut minimum width.If employing minimum widith, correspondence have a plurality of number of pins, common settling mode is to make long and narrow pad line module, and discuss before the picture between the pad interlaced just no longer maybe.
are therefore satisfied at needs and to be had many pads number of pins, save simultaneously under the situation of chip area, and the novel double pad layout structure that proposes a kind of logic module layout of optimizing the pad layout structure and being correlated with more seems particularly important.
Summary of the invention
The actual technical problem to be solved of
the present invention is how to satisfy many pads number of pins, saves chip area simultaneously, more helps the signal line topology in the high-voltage applications, and a kind of novel double pad layout structure is provided in view of the above.
are in order to realize above-mentioned purpose of the present invention; The invention provides a kind of double pad layout structure; At first relate to a kind of chip; Said chip comprises the nuclear district that is positioned at the center and is positioned at pad loop wire zone on every side, said nuclear district that said nuclear is provided with the kernel function module in the district, pad loop wire zone and outer pad ring line zone and input and output control logic circuit in said pad loop wire zone is divided into; Said interior pad loop wire zone includes package lead pad and pad driver circuit with outer pad ring line zone, and said interior pad loop wire zone and outer pad ring line zone are laid in the both sides of said input and output control logic circuit respectively.
double pad layout structure of the present invention, whole circuit is comparatively simple, and the control circuit bus is less; Moreover; For high voltage applications; Even need the level transfer device be set in its inside circuit, also can realize the minimum Butut in the pad layout structure, also guaranteed to have simultaneously and saved pad occupation space described in the chip under a plurality of pad number of pins situation.
Description of drawings
Fig. 1 is the layout structure of existing single pad;
Fig. 2 is the layout structure of existing double pad;
Fig. 3 is the layout structure according to double pad according to the invention.
Embodiment
are further described the present invention below in conjunction with accompanying drawing and embodiment.
please refer to shown in Figure 3; Double pad layout structure of the present invention; At first relate to a kind of chip; Said chip comprises the nuclear district that is positioned at the center and is positioned at pad loop wire zone on every side, said nuclear district that said nuclear is provided with the kernel function module in the district, and comprises input and output control logic circuit in the said kernel function module; Said pad loop wire zone comprises pad and pad circuit and input and output control logic circuit.Among the present invention, said pad is being meant the package lead pad, and said pad circuit is meant the pad driver circuit, and said pad and pad link tester are crossed lead and be connected and be used to transmit signal; Pad loop wire zone and outer pad ring line zone in said pad loop wire zone is divided into, and pad loop wire zone and outer pad ring line zone are laid in the both sides of said input and output control logic circuit respectively in said.
In
double pad layout of the present invention; The said input and output control logic of said kernel function module controls circuit, and said input and output control logic circuit separates and is positioned at the periphery of said kernel function module from said kernel function module controls.Said input and output control logic circuit in said pad loop wire zone and outside between the pad ring line zone; And said input and output control logic circuit is positioned at the center of double pad layout structure, and the pad driver circuit in the said interior pad loop wire zone is symmetrical with the pad driver circuit in the outer pad ring line zone.In the wherein outer pad ring line zone, said pad is connected with the pad circuit earlier, and the pad circuit is connected with input and output control logic circuit more then; And in the interior pad loop wire zone; Said pad also is to be connected with the pad circuit earlier; The pad circuit is connected with input and output control logic circuit more then, and above-mentioned layout type causes inside and outside pad loop wire zone to be symmetrical structure with said input and output control logic circuit.Said input and output control logic circuit is directly connected on the said kernel function module.
in above-mentioned layout structure, it has only shown the layout structure in the pad loop wire zone that is positioned at said nuclear district one side, according to design demand, also can said double-deck pad layout be arranged on around four of said nuclear district.It is in the inside and outside pad loop wire zone of symmetrical structure with input and output control logic circuit that said pad is fixed on said; In order to reduce the quantity of control signal; The logic of direct and the communication of pad circuit of being useful on is placed in the input and output logic, with the communication cabling of minimized input and output control circuit and kernel function module; The position of said pad and distance can be adjusted, so that the holding wire cabling is more reasonable.In order to save the zone of whole pad structure, said pad be fixed on said pad circuit solid space directly over.
In
double pad layout structure of the present invention, related circuit is comparatively simple, and the control circuit bus is less; Moreover; For the more holding wire cabling that high voltage applications is brought,, also can realize the minimum Butut in the pad layout structure even need the level transfer device be set in its inside circuit; Simultaneously also guaranteed to have under a plurality of pad number of pins situation; It is redundant farthest to reduce the nuclear area that caused by pad layout, improves the utilance of nuclear effectively, minimizes final chip area.
Claims (10)
1. double pad layout structure; At first relate to a kind of chip; Said chip comprises the nuclear district that is positioned at the center and is positioned at pad loop wire zone on every side, said nuclear district; Said nuclear is provided with the kernel function module in the district; Pad loop wire zone and outer pad ring line zone and input and output control logic circuit in said pad loop wire zone is divided into, said interior pad loop wire zone includes package lead pad and pad driver circuit with outer pad ring line zone, and it is characterized in that: pad loop wire zone and outer pad ring line zone are laid in the both sides of said input and output control logic circuit respectively in said.
2. double pad layout structure as claimed in claim 1 is characterized in that: said input and output control logic circuit in said pad loop wire zone and outside between the pad ring line zone.
3. double pad layout structure as claimed in claim 1 is characterized in that: the pad driver circuit in said in the pad loop wire zone is symmetrical with the pad driver circuit in the outer pad ring line zone.
4. like claim 1 or 3 described double pad layout structures, it is characterized in that: said input and output control logic circuit connects said interior pad loop wire zone and outer pad ring line zone respectively.
5. like claim 1 or 3 described double pad layout structures; It is characterized in that: the said input and output control logic of said kernel function module controls circuit, and said input and output control logic circuit separates and is positioned at the periphery of said kernel function module from said kernel function module controls.
6. like claim 1 or 3 described double pad layout structures, it is characterized in that: in pad loop wire zone and the outer pad ring line zone, said pad driver circuit all connects said input and output control logic circuit in said.
7. like claim 1 or 3 described double pad layout structures, it is characterized in that: said input and output control logic circuit is positioned at the outside in pad loop wire zone.
8. double pad layout structure as claimed in claim 1 is characterized in that: said input and output control logic circuit is directly connected on the said kernel function module.
9. double pad layout structure as claimed in claim 1; It is characterized in that: in the said pad loop wire zone, said in pad loop wire zone and the outer pad ring line zone the package lead pad be connected on the said input and output control logic circuit after the pad driver circuit is connected.
10. double pad layout structure as claimed in claim 1 is characterized in that: the position of said package lead pad and distance can be adjusted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100489983A CN102569240A (en) | 2012-02-29 | 2012-02-29 | Double-row pad layout structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100489983A CN102569240A (en) | 2012-02-29 | 2012-02-29 | Double-row pad layout structure |
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| CN102569240A true CN102569240A (en) | 2012-07-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012100489983A Pending CN102569240A (en) | 2012-02-29 | 2012-02-29 | Double-row pad layout structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000232120A (en) * | 1999-02-10 | 2000-08-22 | Toshiba Corp | Semiconductor device |
| TW495940B (en) * | 2001-07-20 | 2002-07-21 | Via Tech Inc | Method for forming a grid array packaged integrated circuit |
| EP1391927A2 (en) * | 2002-08-21 | 2004-02-25 | Broadcom Corporation | Concentric bonding pad arrangement on an integrated circuit |
| CN101179071A (en) * | 2006-11-09 | 2008-05-14 | 松下电器产业株式会社 | Semiconductor integrated circuit and multi-chip module |
-
2012
- 2012-02-29 CN CN2012100489983A patent/CN102569240A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000232120A (en) * | 1999-02-10 | 2000-08-22 | Toshiba Corp | Semiconductor device |
| TW495940B (en) * | 2001-07-20 | 2002-07-21 | Via Tech Inc | Method for forming a grid array packaged integrated circuit |
| EP1391927A2 (en) * | 2002-08-21 | 2004-02-25 | Broadcom Corporation | Concentric bonding pad arrangement on an integrated circuit |
| CN101179071A (en) * | 2006-11-09 | 2008-05-14 | 松下电器产业株式会社 | Semiconductor integrated circuit and multi-chip module |
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Application publication date: 20120711 |