CN102569196A - Method for simplifying layer number of manufacturing process photomasks with multiple threshold voltages - Google Patents
Method for simplifying layer number of manufacturing process photomasks with multiple threshold voltages Download PDFInfo
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- CN102569196A CN102569196A CN201110384038XA CN201110384038A CN102569196A CN 102569196 A CN102569196 A CN 102569196A CN 201110384038X A CN201110384038X A CN 201110384038XA CN 201110384038 A CN201110384038 A CN 201110384038A CN 102569196 A CN102569196 A CN 102569196A
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Abstract
The invention discloses a method for simplifying layer number of manufacturing process photomasks with multiple threshold voltages, wherein the method comprises the following specific steps of: (step a) carrying out well ion implantation and conventional threshold voltage ion implantation on different threshold voltage regions of a PMOS (P-channel Metal Oxide Semiconductor) by using a photomask of a N well region; (step b) carrying out well ion implantation and conventional threshold voltage ion implantation on different threshold voltage regions of a NMOS (N-channel Mental-oxide-semiconductor) by using a photomask of a P well region; (step c) simultaneously doping in the high threshold voltage region of the NMOS and the low threshold voltage region of the PMOS by using one photomask; and (step d) simultaneously doping in the high threshold voltage region of the PMOS and the low threshold voltage region of the NMOS by using one photomask. The method for simplifying layer number of the manufacturing process photomasks with multiple threshold voltages, disclosed by the invention, has the following advantages that: the requirement that multiple threshold voltages coexist is satisfied on the process; meanwhile, the technological process is simplified so as to achieve the purpose of reducing the layer number of the photomasks so that the product cost is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially a kind of method of simplifying the processing procedure light shield number of plies of multi-Vt.
Background technology
For advanced nano semiconductor technology, multiple threshold voltage coexists as a processing procedure has become a requisite content of serving Chevron Research Company (CRC).But therefore also brought the too much worry of the light shield number of plies.Existing technology is that mix in high threshold voltage zone (HVT), conventional threshold voltage regions (RVT), the low threshold voltage zone (LVT) of corresponding N/PMOS respectively through different light shields; Increased the employed light shield number of plies of processing procedure so greatly, cost is higher.
Summary of the invention
Existing the problems referred to above when coexisting as a processing procedure to existing multi-Vt, the present invention provides a kind of method of simplifying the processing procedure light shield number of plies of multi-Vt.
The technological means that technical solution problem of the present invention is adopted is:
A kind of method of simplifying the processing procedure light shield number of plies of multi-Vt wherein, comprises following concrete steps:
Step a, the light shield through the N well region carry out for the different threshold voltages zone of PMOS that the trap ion injects and conventional threshold voltage ion injects;
Step b, the light shield through the P well region carry out for the different threshold voltages zone of NMOS that the trap ion injects and conventional threshold voltage ion injects;
Step c, light shield of use mix in the high threshold voltage zone of said NMOS and the low threshold voltage zone of said PMOS simultaneously simultaneously;
Steps d, light shield of use mix in the high threshold voltage zone of said PMOS and the low threshold voltage zone of said NMOS simultaneously.
The method of the processing procedure light shield number of plies of above-mentioned simplification multi-Vt, wherein, the said different threshold voltages zone among the said step a comprises high threshold voltage zone, conventional threshold voltage regions and low threshold voltage zone.
The method of the processing procedure light shield number of plies of above-mentioned simplification multi-Vt, wherein, the said different threshold voltages zone among the said step b comprises high threshold voltage zone, conventional threshold voltage regions and low threshold voltage zone.
The method of the processing procedure light shield number of plies of above-mentioned simplification multi-Vt, wherein, the high threshold voltage of the said NMOS among said step c zone is implemented homotype and is mixed, and the low threshold voltage zone of said PMOS is implemented transoid and is mixed.
The method of the processing procedure light shield number of plies of above-mentioned simplification multi-Vt, wherein, the high threshold voltage of the said PMOS in said steps d zone is implemented homotype and is mixed, and the low threshold voltage zone of said NMOS is implemented transoid and is mixed.
The invention has the beneficial effects as follows:
On technology, satisfied the demand of multi-Vt coexistence, again technological process has been simplified simultaneously, reached the purpose that reduces the light shield number of plies, product cost is reduced.
Description of drawings
Fig. 1 is the flow chart of the method for a kind of processing procedure light shield number of plies of simplifying multi-Vt of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is described further, but not as qualification of the present invention.
As shown in Figure 1, a kind of method of simplifying the processing procedure light shield number of plies of multi-Vt of the present invention wherein, comprises following concrete steps:
Step a, the light shield through the N well region carry out for high threshold voltage zone (HVT), conventional threshold voltage regions (RVT) and the low threshold voltage zone (LVT) of PMOS that the trap ion injects and the injection of conventional threshold voltage ion.
Step b, the light shield through the P well region carry out for high threshold voltage zone (HVT), conventional threshold voltage regions (RVT) and the low threshold voltage zone (LVT) of NMOS that the trap ion injects and the injection of conventional threshold voltage ion.
Step c, light shield of use mix in the high threshold voltage zone (HVT) of NMOS and the low threshold voltage zone (LVT) of PMOS simultaneously simultaneously; Wherein, Homotype is implemented in the high threshold voltage zone (HVT) of NMOS mixed, transoid is implemented in the low threshold voltage zone (LVT) of PMOS mixed to reduce threshold voltage to improve threshold voltage.
Steps d, light shield of use mix in the high threshold voltage zone (HVT) of PMOS and the low threshold voltage zone (LVT) of NMOS simultaneously; Wherein, Homotype is implemented in the high threshold voltage zone (HVT) of PMOS mixed, transoid is implemented in the low threshold voltage zone (LVT) of NMOS mixed to reduce threshold voltage to improve threshold voltage.
Above method makes script need the processing procedure of 6 light shields of use to be reduced to and only needs to use 4 light shields, and 6 original processing steps are reduced to 4, has played the purpose that reduces cost and simplify technology.
The above is merely preferred embodiment of the present invention; Be not so limit claim of the present invention; So the equivalent structure that all utilizations specification of the present invention and diagramatic content have been done changes, utilizes the material of mentioning same-actions such as tool among known and the present invention to replace; Utilize the means and methods of the same-actions of mentioning among known and the present invention such as means and methods tool to replace, resulting execution mode or result of implementation all are included in protection scope of the present invention.
Claims (5)
1. a method of simplifying the processing procedure light shield number of plies of multi-Vt is characterized in that, comprises following concrete steps:
Step a, the light shield through the N well region carry out for the different threshold voltages zone of PMOS that the trap ion injects and conventional threshold voltage ion injects;
Step b, the light shield through the P well region carry out for the different threshold voltages zone of NMOS that the trap ion injects and conventional threshold voltage ion injects;
Step c, light shield of use mix in the high threshold voltage zone of said NMOS and the low threshold voltage zone of said PMOS simultaneously simultaneously;
Steps d, light shield of use mix in the high threshold voltage zone of said PMOS and the low threshold voltage zone of said NMOS simultaneously.
2. simplify the method for the processing procedure light shield number of plies of multi-Vt according to claim 1, it is characterized in that, the said different threshold voltages zone among the said step a comprises high threshold voltage zone, conventional threshold voltage regions and low threshold voltage zone.
3. simplify the method for the processing procedure light shield number of plies of multi-Vt according to claim 1, it is characterized in that, the said different threshold voltages zone among the said step b comprises high threshold voltage zone, conventional threshold voltage regions and low threshold voltage zone.
4. simplify the method for the processing procedure light shield number of plies of multi-Vt according to claim 1, it is characterized in that, the high threshold voltage zone of the said NMOS among the said step c is implemented homotype and is mixed, and the low threshold voltage zone of said PMOS is implemented transoid and mixed.
5. simplify the method for the processing procedure light shield number of plies of multi-Vt according to claim 1, it is characterized in that, the high threshold voltage zone of the said PMOS in the said steps d is implemented homotype and is mixed, and the low threshold voltage zone of said NMOS is implemented transoid and mixed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110384038.XA CN102569196B (en) | 2011-11-28 | 2011-11-28 | Method for simplifying layer number of manufacturing process photomasks with multiple threshold voltages |
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| CN201110384038.XA CN102569196B (en) | 2011-11-28 | 2011-11-28 | Method for simplifying layer number of manufacturing process photomasks with multiple threshold voltages |
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| CN102569196A true CN102569196A (en) | 2012-07-11 |
| CN102569196B CN102569196B (en) | 2014-05-28 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6475846B1 (en) * | 1995-05-18 | 2002-11-05 | Texas Instruments Incorporated | Method of making floating-gate memory-cell array with digital logic transistors |
| US6670683B2 (en) * | 2001-01-04 | 2003-12-30 | International Business Machines Corporation | Composite transistor having a slew-rate control |
| CN1567595A (en) * | 2003-06-24 | 2005-01-19 | 北京大学 | A double-grid MOS transistor and method for making same |
| US20050242862A1 (en) * | 2004-04-29 | 2005-11-03 | Won Hyo-Sig | MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop |
| DE19816446B4 (en) * | 1998-04-14 | 2005-11-17 | Infineon Technologies Ag | Integrated circuit |
| US20090085122A1 (en) * | 2007-10-01 | 2009-04-02 | Vincent Ho | Poly profile engineering to modulate spacer induced stress for device enhancement |
-
2011
- 2011-11-28 CN CN201110384038.XA patent/CN102569196B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475846B1 (en) * | 1995-05-18 | 2002-11-05 | Texas Instruments Incorporated | Method of making floating-gate memory-cell array with digital logic transistors |
| DE19816446B4 (en) * | 1998-04-14 | 2005-11-17 | Infineon Technologies Ag | Integrated circuit |
| US6670683B2 (en) * | 2001-01-04 | 2003-12-30 | International Business Machines Corporation | Composite transistor having a slew-rate control |
| CN1567595A (en) * | 2003-06-24 | 2005-01-19 | 北京大学 | A double-grid MOS transistor and method for making same |
| US20050242862A1 (en) * | 2004-04-29 | 2005-11-03 | Won Hyo-Sig | MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop |
| US20090085122A1 (en) * | 2007-10-01 | 2009-04-02 | Vincent Ho | Poly profile engineering to modulate spacer induced stress for device enhancement |
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| CN102569196B (en) | 2014-05-28 |
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