CN102568604B - BCH (Broadcast Channel) encoder and decoder - Google Patents
BCH (Broadcast Channel) encoder and decoder Download PDFInfo
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- CN102568604B CN102568604B CN201110403284.5A CN201110403284A CN102568604B CN 102568604 B CN102568604 B CN 102568604B CN 201110403284 A CN201110403284 A CN 201110403284A CN 102568604 B CN102568604 B CN 102568604B
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Abstract
The invention is suitable for the technical field of communication and provides a BCH (Broadcast Channel) encoder. The BCH encoder is provided with a code word input end and an encoding calculation unit, wherein the encoding calculation unit comprises at least two complementation circuits used for encoding calculation of the code words, the input end of a first complementation circuit is connected with the code word input end through a first switch, and the input end of a second complementation circuit is also connected with the code word input end through a second switch. The invention provides a BCH decoder correspondingly, and the BCH decoder also comprises at least two complementation circuits used for decoding calculation. Therefore, the encoder and the decoder have double error correcting capabilities, by properly enlarging the verifying data space of BCH codes, the delaying is lowered, and the error correcting property is improved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of Bose-Chaudhuri-Hocquenghem Code device and demoder.
Background technology
Be applied to the error correcting technique mainly BCH of solid state hard disc at present, cataloged procedure is realized by division circuit complementation.Decode procedure is divided into three parts, is first complementation, hardware uses linear feedback shift register realize, and is then the calculating of syndrome successively, and key equation solving is finally money search procedure.When design BCH code carries out Error Correction of Coding; usually can consider that the area that error correction coding/decoding unit uses is economized as far as possible; sluggish (latency) is as far as possible short; simultaneously; the checking data space used also will be lacked as far as possible; error-correcting performance is also high as much as possible; but these require that some is competing in actual applications; current BCH encoding and decoding error correction is all improve error correcting capability by merely increasing checking data or increasing code length; and meanwhile, but sacrifice data space or sluggishness.
In summary, obviously there is inconvenience and defect in actual use, so be necessary to be improved in existing Bose-Chaudhuri-Hocquenghem Code device and demoder.
Summary of the invention
For above-mentioned defect, the object of the present invention is to provide a kind of Bose-Chaudhuri-Hocquenghem Code device and demoder, it not only can reduce sluggishness, can also improve the error correcting capability of BCH code.
To achieve these goals, the invention provides a kind of Bose-Chaudhuri-Hocquenghem Code device, there is a code word input end and coding computing unit, described coding computing unit comprises at least two-way complementation circuit, coding all for code word calculates, and the input end of the first complementation circuit connects described code word input end by the first switch; The input end of the second complementation circuit also connects described code word input end by second switch.
According to Bose-Chaudhuri-Hocquenghem Code device of the present invention, described code word input end connects a buffer, for code word described in buffer memory.
According to Bose-Chaudhuri-Hocquenghem Code device of the present invention, the output terminal of described first complementation circuit, the second complementation circuit and buffer is all connected to a multiplexer, and exports data by described multiplexer.
According to Bose-Chaudhuri-Hocquenghem Code device of the present invention, described first complementation circuit and each corresponding generator polynomial of the second complementation circuit.
According to Bose-Chaudhuri-Hocquenghem Code device of the present invention, described Bose-Chaudhuri-Hocquenghem Code device is scale-of-two Bose-Chaudhuri-Hocquenghem Code device.
The present invention provides a kind of BCH demoder accordingly, there is code word input end and a decoding-calculating unit, described decoding-calculating unit comprises at least two-way complementation circuit, and the decoding all for code word calculates, and the input end of the 3rd complementation circuit connects described code word input end by the 3rd switch; The input end of the 4th complementation circuit also connects described code word input end by the 4th switch.
According to BCH demoder of the present invention, described BCH demoder also comprises
Error message computing unit, for calculating the errors present information determining described decoded code word;
Error correction unit, for carrying out error correction to described mistake;
Described 3rd complementation circuit is connected to described error message computing unit, and described 4th complementation circuit is connected to described error message computing unit by a buffer, and described error message computing unit is connected to described error correction unit.
According to BCH demoder of the present invention, described error message computing unit comprises:
Syndrome computation subunit, for calculating acquisition syndrome;
Key equation solving subelement, for according to described syndrome determination key equation, and solves;
Money search subelement, for obtaining the root of key equation, and output error message.
Control subelement, for controlling the reference position of described money search.
According to BCH demoder of the present invention, described 3rd complementation circuit and each corresponding generator polynomial of the 4th complementation circuit.
According to BCH demoder of the present invention, described BCH demoder is two enter BCM demoder.
The present invention is by arranging the Code And Decode of two-way complementation circuit realiration BCH respectively, better, the corresponding generator polynomial of every road complementation circuit, error correcting capabilities corresponding different respectively, when not repairable mistake appears in the code word on a road, carry out the strong error correction of secondary by another road.Whereby, encoder of the present invention can increase the checking data space of part BCH code, improves error-correcting performance when not increasing sluggishness.
Accompanying drawing explanation
Fig. 1 is the structural representation of Bose-Chaudhuri-Hocquenghem Code device of the present invention;
Fig. 2 is the structural representation of BCH demoder of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
See Fig. 1, the invention provides a kind of Bose-Chaudhuri-Hocquenghem Code device 10, it has code word input end 11 and coding computing unit 12, and coding computing unit 12, for receiving code word from code word input end 11 and it being done to division complementation computing, obtains coding result whereby.
Coding computing unit 12 in the present embodiment comprises two-way complementation circuit, the input end of the first complementation circuit 121 connects code word input end 11 by the first switch S 1, the input end of the second complementation circuit 122 also connects code word input end 11 by second switch S2, and the output terminal of two kinds of complementation circuit is all connected to a multiplexer 13, be connected with a buffer 14 between code word input end 11 and multiplexer 13 for buffer memory code word.First complementation circuit 121, second complementation circuit 122 and buffer 14 are all exported by multiplexer 13.
In actual applications, binary BCH codes is one of the most frequently used BCH code, the code element of binary BCH codes all takes from GF (2), and each code element polynomial expression must be times formula of generator polynomial, and that is generator polynomial is the code element polynomial expression that a power is minimum.Suppose that the code length of certain scale-of-two primitive BCH code is n, information bit is long is k, and code polynomial is C (x), and generator polynomial is g (x), then have:
By t (x)=c (x) * x
n-k+ p (x) exports as the data after coding.At decoding end after channel, t (x) becomes r (x), if r (x) can be divided exactly by g (x), illustrates error-free, otherwise explanation has made mistakes, and needs to carry out error correction.The highest power of g (x) is determined by error correcting capability, and it equals the highest power of residue p (x).
The present invention for scale-of-two Bose-Chaudhuri-Hocquenghem Code device, because it has two-way complementation circuit, so corresponding two kinds of error correcting capabilities, be respectively weak error correcting capability and strong error correcting capability, meanwhile, the corresponding generator polynomial of every road complementation circuit, the weak error correcting capability respectively before correspondence and strong error correcting capability.
For better describing the present invention, suppose in an embodiment, the code length of weak error correcting capability code correspondence is n1, code polynomial is M (x), the long k1=2kByte of information bit, generator polynomial is g1 (x), and weak error correction number is t1, and residue i.e. check bit polynomial expression are Mr (x); The code length of strong error correcting capability code correspondence is n2, and code polynomial is K (x), the long k2=4Kbyte of information bit, and generator polynomial is g2 (x), and strong error correction number is t2, and residue i.e. check bit polynomial expression are Kr (x).In order to reduce the extra hardware spending that different galois fields brings, the present invention makes two kinds of error correcting capabilities be in same galois field, and gets galois field larger among both, gets GF (2 in this example
16).Figure below illustrates the codeword structure of the 4Kbyte after have passed through scale-of-two Bose-Chaudhuri-Hocquenghem Code.
Can find out from the graph, weak error correcting capability is used to code word 1, by M (x) * x
n1-k1/ g1 (x) produces Mr (x), and code word 1 and code word 2 are used in combination strong error correcting capability, by K (x) * x
n2-k2/ g2 (x) produces Kr (x).Apparent, the structure with the Bose-Chaudhuri-Hocquenghem Code device 10 of double-deck error correcting capability needing the two-way division circuit shown in Fig. 1 to form when encoding.The concrete course of work of of Bose-Chaudhuri-Hocquenghem Code device 10 of the present invention is as follows: when the first code word input, the first switch S 1 and second switch S2 all closed, two-way complementation circuit works simultaneously, is at this moment also exported by the first code word synchronization; After first code word end of input, second code word is come, at this moment, residue Mr (x) in first complementation circuit 121 (to g1 (x) complementation) is exported, S1 is disconnected simultaneously, S2 remains closed, the second code word is continued to input in the second complementation circuit 122 (to g2 (x) complementation), second code word also synchronism output simultaneously, until the second code word has inputted, again the residue Kr (x) in the second complementation circuit 122 is exported, just form the codeword structure after the coding shown in upper table whereby.
Again see Fig. 2, the invention provides a kind of BCH demoder 20, it has a code word input end 21 and decoding-calculating unit 22, and described decoding-calculating unit 22 comprises at least two-way complementation circuit, decoding all for code word calculates, the corresponding generator polynomial of every road complementation circuit.The input end that the input end of the 3rd complementation circuit 221 connects code word input end the 21, four complementation circuit 222 by the 3rd switch A also connects code word input end 21 by the 4th switch B.
Embodiments of the invention illustrate for scale-of-two BCH demoder, it comprises error message computing unit 23 and error correction unit 24, error message computing unit 23 determines the errors present information of described decoded code word for calculating, error correction unit 24, for correcting the mistake of decoded code word, particularly carries out negate error correction to the code word of the position of corresponding mistake.The output terminal that the output terminal of the 3rd complementation circuit 221 is connected to error message computing unit the 23, four complementation circuit 222 is connected to error message computing unit 23 by a buffer 223, and error message computing unit is connected to error correction unit 24.
In one embodiment of the invention, code word input end 21 is also connected to error correction unit 24 by another impact damper 25, and error message computing unit 23 comprises:
Syndrome computation subunit 231, obtain 2t syndrome for calculating according to the decoded data of decoding-calculating unit 22, t is error correction number.
Key equation solving subelement 232, for according to syndrome determination key equation, and solve, the process of key equation solving is exactly the process utilizing syndrome to solve error location polynomial.
Money search subelement 233, for obtaining the root of key equation, and output error message.The process of money search is a process of searching root, and namely substituted into by the root of all possible error location polynomial, judging whether to make error location polynomial be 0, if be 0, is then the root of error location polynomial, namely errors present.
Control subelement 234, for controlling the reference position of money search.
In one embodiment of the invention, the course of work of scale-of-two BCH demoder 20 is as follows: when the first code word input, switch A and B is all closed, two-way complementation circuit works simultaneously, and after the first code word end of input, the second code word is come, now disconnected by the 3rd switch A, the 4th switch B remains closed.For the 3rd complementation circuit 221, weak BCH decoding will be carried out, for the 4th complementation circuit 222, then continue in the second code word input the 4th complementation circuit 222, also need to carry out strong BCH decoding simultaneously, these two processes work simultaneously, but the end of the 4th complementation circuit 222 can relatively lag behind than the end of the 3rd complementation circuit 221, and therefore two-way complementation circuit shares error message computing unit 23 and the error correction unit 24 of latter half.After the money of the 3rd complementation circuit 221 has been searched for, if what search makes mistakes number not higher than the highest power of key equation, illustrate that the mistake of the first code word can be repaired, at this moment the search reference position of the 4th complementation circuit 222 money search is controlled by controlling subelement 234, make it only search for the mistake of the second code word, reduce sluggish (latency); Otherwise, if unequal, then illustrate that can not error correction miss has appearred in the first code word, at this moment, the search reference position of the 4th complementation circuit 222 just must from the first code word, by the strong error correction of the 4th complementation circuit 222, secondary error correction is carried out to the first code word, improve the error correcting capability of whole code word whereby.
In sum, the present invention passes through the Code And Decode arranging two-way complementation circuit realiration BCH respectively, better, the corresponding generator polynomial of every road complementation circuit, error correcting capabilities corresponding different respectively, when not repairable mistake appears in the code word on a road, carries out the strong error correction of secondary by another road.Whereby, encoder of the present invention, by increasing the checking data space of some BCH code, improves error-correcting performance when not increasing sluggishness.
Certainly; the present invention also can have other various embodiments; when not deviating from the present invention's spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and distortion according to the present invention, but these change accordingly and are out of shape the protection domain that all should belong to the claim appended by the present invention.
Claims (9)
1. a Bose-Chaudhuri-Hocquenghem Code device, have a code word input end and coding computing unit, it is characterized in that, described coding computing unit comprises at least two-way complementation circuit, coding all for code word calculates, and the input end of the first complementation circuit connects described code word input end by the first switch; The input end of the second complementation circuit also connects described code word input end by second switch; Described code word input end also connects a buffer, for code word described in buffer memory;
When first code word input time, described first switch and second switch all closed, two-way complementation circuit works simultaneously, and the first code word synchronization exports by described buffer;
After described first code word end of input, second code word arrives, residue in first complementation circuit is exported, described first switch disconnects simultaneously, described second switch remains closed, and continues the second code word to input in described second complementation circuit, and described buffer is by the second code word synchronism output, until the second code word has inputted, then the residue in described second complementation circuit is exported.
2. Bose-Chaudhuri-Hocquenghem Code device according to claim 1, is characterized in that, the output terminal of described first complementation circuit, the second complementation circuit and buffer is all connected to a multiplexer, and exports data by described multiplexer.
3. Bose-Chaudhuri-Hocquenghem Code device according to claim 1, is characterized in that, described first complementation circuit and each corresponding generator polynomial of the second complementation circuit.
4. Bose-Chaudhuri-Hocquenghem Code device according to claim 1, is characterized in that, described Bose-Chaudhuri-Hocquenghem Code device is scale-of-two Bose-Chaudhuri-Hocquenghem Code device.
5. a BCH demoder, have code word input end and a decoding-calculating unit, it is characterized in that, described decoding-calculating unit comprises at least two-way complementation circuit, decoding all for code word calculates, and the input end of the 3rd complementation circuit connects described code word input end by the 3rd switch; The input end of the 4th complementation circuit also connects described code word input end by the 4th switch;
When first code word input time, described 3rd switch and the 4th switch all closed, two-way complementation circuit works simultaneously, after the first code word end of input, second code word arrive, described 3rd switch disconnect, described 4th switch remains closed; By computing in the described 4th complementation circuit of the second code word input.
6. BCH demoder according to claim 5, is characterized in that, described BCH demoder also comprises
Error message computing unit, for calculating the errors present information determining described decoded code word;
Error correction unit, for carrying out error correction to described mistake;
Described 3rd complementation circuit is connected to described error message computing unit, and described 4th complementation circuit is connected to described error message computing unit by a buffer, and described error message computing unit is connected to described error correction unit.
7. BCH demoder according to claim 6, is characterized in that, described error message computing unit comprises:
Syndrome computation subunit, for calculating acquisition syndrome;
Key equation solving subelement, for according to described syndrome determination key equation, and solves;
Money search subelement, for obtaining the root of key equation, and output error message;
Control subelement, for controlling the reference position of described money search.
8. BCH demoder according to claim 5, is characterized in that, described 3rd complementation circuit and each corresponding generator polynomial of the 4th complementation circuit.
9. BCH demoder according to claim 5, is characterized in that, described BCH demoder is scale-of-two BCH demoder.
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