CN102568567A - Flash memory operation method - Google Patents
Flash memory operation method Download PDFInfo
- Publication number
- CN102568567A CN102568567A CN2010105841630A CN201010584163A CN102568567A CN 102568567 A CN102568567 A CN 102568567A CN 2010105841630 A CN2010105841630 A CN 2010105841630A CN 201010584163 A CN201010584163 A CN 201010584163A CN 102568567 A CN102568567 A CN 102568567A
- Authority
- CN
- China
- Prior art keywords
- flash memory
- fast flash
- operating
- bit
- memory bank
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a flash memory operation method. According to the operation method, when one storage bit in a plurality of storage bits has 2<n> program levels, storage bits adjacent to the storage bit are set into 2<n-1> program levels. Similarly, when another storage bit in a plurality of storage bits has 2<n-1> program levels, storage bits adjacent to the storage bit are set into 2<n> program levels. Each program level is corresponding to different critical voltage distributions. According to the program level mode, effective program levels can be efficiently utilized without increasing technological complexity.
Description
Technical field
The present invention relates to a kind of method of operating of memory body, particularly relate to the method for operating of a kind of fast flash memory bank (FLASH memory).
Background technology
The non-volatility memory technology is the most valued at present memory body technology, wherein has a kind of with oxide-nitride thing-oxide (Oxide-Nitride-Oxide; ONO) etc. the structure that has the charge-trapping effect replaces the stack memory cell of traditional memory cell, makes easily and the advantage of densification because of having, so received the great attention and the research of all circles, also can be described as charge-trapping type fast flash memory bank.In charge-trapping type fast flash memory bank, each memory cell (memory cell) but ONO in store charge, and the electric charge that stores can influence its critical voltage Vth, but and this critical voltage of sensing with the expression data.
Develop at present and to store the above mlc (Multi-levelCell of two states; MLC) memory cell; To increase storage density, its " multistage " refers to charge charging has a plurality of abilities rank (being a plurality of magnitudes of voltage), and the value that so just can store a plurality of bits is in each memory cell; As shown in Figure 1, Fig. 1 is the vertical view of a kind of charge-trapping type fast flash memory bank of existing convention.
In Fig. 1, shown character line WL0～WL2, bit line BL1～BL2 and a plurality of memory cell 10, and each memory cell 10 is corresponding to a character line and two bit lines.But; Under the more and more little development of memory body size; In single memory cell 10 two store bit 100a and 100b as there being 4 program level; Then reciprocation possibly take place each other, for example the electric field that store charge produced that stores bit 100a makes a difference by operation the time for another storage bit 100b, and causes the so-called second bit effect (2nd bit effect) 102.
And; In the operating period of programmable memory cell 10; Because programm voltage is to be applied to the memory cell that all are connected to same character line WL1, therefore makes storage bit 100a receive the left side and upset (program disturbance) 104 across the sequencing of bit line BL1.In addition; Memory body with progress below the 75nm node (node); Under the situation that distance between character line WL0～WL2 also shortens, the character line of the storage bit of two memory cells 10 disturbs (Wordline interference) 106 also can to make storage bit 100a, 100b receive up and down.
Fig. 2 is the voltage distribution plan that shows the storage bit 100a that receives above-mentioned ghost effect influence; Wherein 4 program levels distribute corresponding to different critical voltages, and critical conditions 200,202,204 and 206 has different critical voltage distribution ranges and is spaced apart from each other.Yet along with crystallite dimension is more and more little, the critical voltage that the second bit effect that two bits of single memory cell are produced each other can cause becoming big distributes 208.And, because the relation that sequencing is upset can increase critical voltage again and distribute 210.Then, under the more and more little situation of the distance between the character line, also can further strengthen critical voltage because the character line disturbs and distribute 212.Finally cause distinguishing critical conditions 200 and critical conditions 202, all memory cells become 3 program levels from 4 program levels originally in the memory body and make, and can only be used as 1 bit operation.
This shows that the method for operating of above-mentioned existing fast flash memory bank obviously still has inconvenience and defective, and demands urgently further improving in method and use.In order to solve the problem of above-mentioned existence; Relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly; But do not see always that for a long time suitable design is developed completion, and conventional method does not have appropriate method to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of method of operating of new fast flash memory bank, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The objective of the invention is to; Overcome the defective of the method for operating existence of existing fast flash memory bank; And a kind of method of operating of new fast flash memory bank is provided; Technical matters to be solved is to make it can avoid memory body to receive the second bit effect (2nd bit effect), sequencing upset (Programdisturbance) and the influence of character line interference effects such as (Wordline interference), is very suitable for practicality.
Another purpose of the present invention is; A kind of method of operating of new fast flash memory bank is provided; Technical matters to be solved is to make it increase by 1.5 times storage density (storage density) than traditional unit accurate unit (SLC) or the accurate unit of multidigit (MLC) memory body, thereby is suitable for practicality more.
The object of the invention and solve its technical matters and adopt following technical scheme to realize.The method of operating of a kind of fast flash memory bank that proposes according to the present invention; Be to be used to operate a fast flash memory bank that is made up of a plurality of storage bits that are arranged in array, said method of operating may further comprise the steps: it is 2 that a storage bit in a plurality of storage bits has number
nProgram level (program level) time, adjacent storage bit around this storage bit is made as to have number be 2
N-1Program level; Likewise, another in a plurality of storage bits stores bit to have number is 2
N-1Program level the time, this is stored around bit adjacent storage bit is made as that to have number be 2
nProgram level, wherein each program level distributes corresponding to different critical voltage.
The object of the invention and solve its technical matters and also can adopt following technical measures further to realize.
The method of operating of aforesaid fast flash memory bank, wherein said fast flash memory bank can be virtual ground memory array (virtual ground memory array) or NAND type memory body.
The method of operating of aforesaid fast flash memory bank, wherein said fast flash memory bank comprise memory body that is made up of a plurality of charge-trapping type memory cells or the memory body that is made up of a plurality of floating grid polar form memory cells.
The object of the invention and solve its technical matters and also adopt following technical scheme to realize.The method of operating of a kind of fast flash memory bank that proposes according to the present invention, this fast flash memory bank comprises many character lines, many bit lines and a plurality of memory cell, and each memory cell is corresponding to a character line and two bit lines.The aforesaid operations method comprises having 2 with being made as corresponding to a plurality of storage bits in a plurality of memory cells of same character line
nWith 2
N-1Program level alternately, and will be made as corresponding to a plurality of storage bits in a plurality of memory cells of same bit line and have 2
nWith 2
N-1Program level alternately, wherein each program level distributes corresponding to different critical voltages.
The object of the invention and solve its technical matters and also can adopt following technical measures further to realize.
The method of operating of aforesaid fast flash memory bank, wherein said fast flash memory bank comprise virtual ground memory array (virtual ground memory array).
The method of operating of aforesaid fast flash memory bank, wherein said memory cell comprise charge-trapping type memory cell or floating grid polar form memory cell.
The method of operating of aforesaid fast flash memory bank, wherein said storage bit are the accurate unit of multidigit (MLC).
The method of operating of aforesaid fast flash memory bank, wherein said storage bit comprises the accurate unit in accurate unit of multidigit and unit (SLC).
The method of operating of aforesaid fast flash memory bank, wherein said n is the positive integer more than or equal to 2, as 2,3 or 4.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, the method for operating of fast flash memory bank of the present invention has advantage and beneficial effect at least: the present invention designs on the method for operating of fast flash memory bank that to have number be 2
N-1The storage bit of program level, and use around it that to have number be 2
nThe storage bit of program level it is surrounded, having number is 2
nProgram level the storage bit around same use that to have number be 2
N-1The storage bit of program level it is surrounded; Therefore use the memory body of method of operating of the present invention can be higher than the storage density of accurate unit of unit or the accurate unit of multidigit memory body; And can alleviate ghost effect simultaneously, make program level maintain diacritic state.
In sum, the invention relates to a kind of method of operating of fast flash memory bank, in said method of operating, it is 2 that a storage bit in a plurality of storage bits has number
nProgram level the time, adjacent storage bit around this storage bit is made as to have number be 2
N-1Program level; Likewise, another in a plurality of storage bits stores bit to have number is 2
N-1Program level the time, this is stored around bit adjacent storage bit is made as that to have number be 2
nProgram level, wherein each program level distributes corresponding to different critical voltage.Such program level pattern can be utilized effective program level efficiently and not increase process complexity.The present invention has obvious improvement technically, has tangible good effect, really is the new design of a novelty, progress, practicality.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of instructions, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Fig. 1 is the vertical view of a kind of charge-trapping type fast flash memory bank of existing convention.
Fig. 2 is the voltage distribution plan that shows the memory cell that receives the ghost effect influence.
Fig. 3 is the vertical view according to a kind of fast flash memory bank of one embodiment of the invention.
Fig. 4 is that the n of the storage bit of displayed map 3 is the voltage distribution plan of 2: first memory cells.
Fig. 5 is the vertical view according to a kind of fast flash memory bank of another embodiment of the present invention.
Fig. 6 is the vertical view according to a kind of floating grid fast flash memory bank of one embodiment of the invention.
A1, A2, A3: active region
BL1, BL2, BL3: bit line
WL0, WL1, WL2, WL3, WL4: character line
10,30a～30i, 50a～50i, 60a～60l: memory cell
100a, 100b, 300a, 300b, 302a, 302b, 304a, 304b, 306b, 308a, 500～516,600～622: store bit
102: the second bit effects
104: sequencing is upset
106: the character line disturbs
200,202,204,206,400,402,404,406: critical conditions
208,210,212,408,410,412: critical voltage distributes
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To its embodiment of method of operating, method, step, characteristic and the effect thereof of the fast flash memory bank that proposes according to the present invention, specify as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to appear in the following detailed description that cooperates with reference to graphic preferred embodiment.Through the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to get one more deeply and concrete understanding to the present invention, yet the appended graphic usefulness that only provides reference and explanation be not to be used for the present invention is limited.
Fig. 3 is the vertical view according to a kind of fast flash memory bank of one embodiment of the invention.
See also shown in Figure 3ly, the method for operating of the fast flash memory bank of present embodiment is to be used to operate the fast flash memory bank that is made up of a plurality of memory cells that are arranged in array.For instance; The fast flash memory bank of present embodiment is to be made up of many character line WL0, WL1 and WL2, many bit line BL1 and BL2 and a plurality of charge-trapping type memory cell 30a～30i; And each memory cell among the figure is corresponding to a character line and two bit lines, so the fast flash memory bank of present embodiment is virtual ground memory array (virtualground memory array).The method of operating of the fast flash memory bank of present embodiment be with corresponding to the storage bit 306b among memory cell 30d, 30e and the 30f of same character line WL1,300a, 300b, 308a is made as has 2
nWith 2
N-1Program level alternately, and will be corresponding to storage bit 302a, 300a among memory cell 30b, 30e and the 30h of same bit line BL1,304a is made as has 2
nWith 2
N-1Program level alternately, wherein each program level distributes corresponding to different critical voltages.
Because the number that has in the foregoing description is 2
nThe storage bit 300a of program level around be 2 by the program level number
N-1Storage bit 300b, 302a, 304a and 306b surround, so can reduce ghost effect (parasitic effect), avoid that the position is accurate reduces; By the program level number is 2
nThe number that has that surrounds of storage bit 300a, 302b, 308a and 304b be 2
N-1The storage bit 300b of program level then can bear bigger ghost effect and not fall low level.In other words, to have at least half the memory cell can carry out number be 2 to whole fast flash memory bank
nThe operation of program level, so the foregoing description increases by 1.5 times storage density (storage density) than the mode of the accurate unit of traditional whole applying units (SLC) memory cell.In addition, if with itself can do the accurate unit of multidigit (multi-levelcell, memory body MLC) is compared, the foregoing description also can increase by 1.5 times storage density.
In the above-described embodiments, the n value in the program level number can be the positive integer more than or equal to 2, as 2,3 or 4.Therefore, the storage bit 300a of memory cell 30e is the accurate unit of multidigit; Be the accurate unit of unit when n=2, be 3 or belong to the accurate unit of multidigit when above and store bit 300b at n.
Fig. 4 is that the n of the storage bit of displayed map 3 is the voltage distribution plan of 2: first memory cells.In Fig. 4, four program levels distribute corresponding to different critical voltages, and each all has critical conditions 400 (zero-bit is accurate), 402 (first standard), 404 (second standard) and 406 (the 3rd standard) clearly the critical voltage distribution range and be spaced apart from each other.Because surrounded by the storage bit of program level number little (like 2 program levels) around the storage bit 300a of program level number big (like 4 program levels); So can alleviate result from that the critical voltage of the second bit effect (2nd bit effect) distributes 408, critical voltage that (Program disturbance) upset in the sequencing that results from distribute 410 with result from the character line and disturb the critical voltage of (Wordline interference) to distribute 412, and make program level (critical conditions 400) maintain diacritic state.
In addition, the method for operating of fast flash memory bank of the present invention also may be used on NAND type memory body.
Fig. 5 is the vertical view according to a kind of fast flash memory bank of another embodiment of the present invention.See also shown in Figure 5ly, the method for operating of the fast flash memory bank of present embodiment is to be used to operate the fast flash memory bank that is made up of a plurality of memory cells that are arranged in array.For instance; The fast flash memory bank of present embodiment can be a NAND type fast flash memory bank; It is to be made up of many character line WL1, WL2 and WL3, many active regions (activeregion) A1, A2 and A3 and a plurality of memory cell 50a～50i; And each memory cell among the figure is between a character line and active region, and wherein memory cell 50a～50i can be charge-trapping type memory cell or floating grid polar form memory cell.The method of operating of present embodiment is that to have number be 2 to the storage bit 508 as memory cell 50e
nProgram level the time, adjacent storage bit 502,506,510 and 514 around it is made as to have number be 2
N-1Program level.Likewise, be 2 when storage bit 502 has number
N-1Program level the time, need storage bit 500,504,508 adjacent around it etc. is made as that to have number be 2
nProgram level.Thus, the storage bit 508 of Fig. 5 is that 2 o'clock voltage distributes also will be identical with Fig. 4 at n.
Fig. 6 is the vertical view according to a kind of floating grid fast flash memory bank of one embodiment of the invention.Fast flash memory bank in Fig. 6 is to be made up of many character line WL1～WL4, many bit line BL1～BL3 and a plurality of floating grid polar form memory cell 60a～60l; And each memory cell among the figure is exactly one and stores bit, so the fast flash memory bank of present embodiment also can be regarded the NOR type floating grid polar form memory array that is made up of a plurality of storage bits 600～622 that are arranged in array as.
The method of operating of the fast flash memory bank of Fig. 6 is the storage bit 600,602,604 corresponding to same character line WL1 to be made as have 2
nWith 2
N-1Program level alternately, and will be made as corresponding to the storage bit 600,606,612,618 of same bit line BL1 and have 2
nWith 2
N-1Program level alternately, wherein each program level distributes corresponding to different critical voltages.Such operational design is because program level number big (2
n) storage bit 608 around little by (2 by the program level number
N-1) storage bit 602,606,610 and 614 surround, result from critical voltage that sequencing upsets and distribute and result from the critical voltage that the character line disturbs and distribute so can alleviate, and make program level maintain diacritic state.
In sum, design concept proposed by the invention is to be 2 having number
N-1The storage bit of program level around to use the program level number be 2
nThe storage bit it is surrounded, reduce so that the position of avoiding storing bit is accurate.Therefore, to have at least half the memory cell can carry out number be 2 to whole fast flash memory bank
nThe operation of program level, with tradition all the mode of the accurate unit of applying unit (SLC) and the accurate unit of multidigit (MLC) memory cell compare and have higher storage density (storage density).On the other hand, the program level number is big (as 2
n) the storage bit then little (as 2 with the program level number
N-1) the storage bit surround, to alleviate ghost effect, make program level maintain diacritic state.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the technology contents of above-mentioned announcement capable of using is made a little change or is modified to the equivalent embodiment of equivalent variations; In every case be not break away from technical scheme content of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. the method for operating of a fast flash memory bank is characterized in that it is to be used to operate a fast flash memory bank that is made up of a plurality of storage bits that are arranged in array, and said method of operating may further comprise the steps:
It is 2 that in these a plurality of storage bits storage bit has number
nProgram level the time, adjacent storage bit around this storage bit is made as to have number be 2
N-1Program level; And
It is 2 that another storage bit in these a plurality of storage bits has number
N-1Program level the time, store around the bit adjacent storage bit with this another and be made as that to have number be 2
nProgram level, wherein
Each program level distributes corresponding to different critical voltages.
2. the method for operating of fast flash memory bank according to claim 1 is characterized in that wherein said fast flash memory bank comprises virtual ground memory array or NAND type memory body.
3. the method for operating of fast flash memory bank according to claim 1 is characterized in that wherein said fast flash memory bank comprises memory body that is made up of a plurality of charge-trapping type memory cells or the memory body that is made up of a plurality of floating grid polar form memory cells.
4. the method for operating of a fast flash memory bank; It is characterized in that this fast flash memory bank comprises many character lines, many bit lines and a plurality of memory cell; And each memory cell corresponding to one in said a plurality of character lines with said a plurality of bit lines in a pair of, said method of operating may further comprise the steps:
To be made as corresponding to a plurality of storage bits of said a plurality of memory cells of same character line and have 2
nWith 2
N-1Program level alternately; And
To be made as corresponding to a plurality of storage bits of said a plurality of memory cells of same bit line and have 2
nWith 2
N-1Program level alternately, wherein
Each program level distributes corresponding to different critical voltages.
5. according to the method for operating of claim 1 or 4 described fast flash memory banks, it is characterized in that wherein said a plurality of storage bit is the accurate unit of multidigit.
6. according to the method for operating of claim 1 or 4 described fast flash memory banks, it is characterized in that wherein said a plurality of storage bit comprises the accurate unit in accurate unit of multidigit and unit.
7. according to the method for operating of claim 1 or 4 described fast flash memory banks, it is characterized in that wherein said n is the positive integer more than or equal to 2.
8. the method for operating of fast flash memory bank according to claim 7 is characterized in that wherein said n is 2,3 or 4.
9. the method for operating of fast flash memory bank according to claim 4 is characterized in that wherein said fast flash memory bank comprises the virtual ground memory array.
10. the method for operating of fast flash memory bank according to claim 4 is characterized in that wherein said a plurality of memory cell comprises charge-trapping type memory cell or floating grid polar form memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010584163.0A CN102568567B (en) | 2010-12-07 | 2010-12-07 | Flash memory operation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010584163.0A CN102568567B (en) | 2010-12-07 | 2010-12-07 | Flash memory operation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102568567A true CN102568567A (en) | 2012-07-11 |
| CN102568567B CN102568567B (en) | 2015-06-17 |
Family
ID=46413776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010584163.0A Active CN102568567B (en) | 2010-12-07 | 2010-12-07 | Flash memory operation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102568567B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060002167A1 (en) * | 2004-06-30 | 2006-01-05 | Micron Technology, Inc. | Minimizing adjacent wordline disturb in a memory device |
| CN1811990A (en) * | 2005-01-25 | 2006-08-02 | 旺宏电子股份有限公司 | Method of dynamically controlling program verify levels in multilevel memory cells |
| CN201040966Y (en) * | 2006-06-08 | 2008-03-26 | 上海八安建筑工程有限公司 | Anti-theft lock |
| TW200903498A (en) * | 2007-07-03 | 2009-01-16 | Macronix Int Co Ltd | Double programming methods of multi-level-cell nonvolatile memory |
-
2010
- 2010-12-07 CN CN201010584163.0A patent/CN102568567B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060002167A1 (en) * | 2004-06-30 | 2006-01-05 | Micron Technology, Inc. | Minimizing adjacent wordline disturb in a memory device |
| CN1811990A (en) * | 2005-01-25 | 2006-08-02 | 旺宏电子股份有限公司 | Method of dynamically controlling program verify levels in multilevel memory cells |
| CN201040966Y (en) * | 2006-06-08 | 2008-03-26 | 上海八安建筑工程有限公司 | Anti-theft lock |
| TW200903498A (en) * | 2007-07-03 | 2009-01-16 | Macronix Int Co Ltd | Double programming methods of multi-level-cell nonvolatile memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102568567B (en) | 2015-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102270501B (en) | Utilize flush memory device and the system of programming sequencer, and programmed method | |
| US10430262B2 (en) | Identifying asynchronous power loss | |
| JP5631750B2 (en) | Compound memory | |
| CN102625948B (en) | 3D memory devices decoding and routing systems and methods | |
| CN102163456A (en) | Nonvolatile memory device, operating method thereof, and memory system including the same | |
| CN107015760A (en) | The operating method of accumulator system and accumulator system | |
| KR20120107336A (en) | Memory system and addressing method thereof | |
| TW201419280A (en) | Nonvolatile memory device having near/far memory cell groupings and data processing method | |
| CN108463852B (en) | Apparatus and method including establishing negative body potential in a memory cell | |
| US8976583B2 (en) | Non-volatile semiconductor memory device and reading method thereof | |
| CN104641418A (en) | Memory system | |
| CN106920570B (en) | Memory system and operating method thereof | |
| JP4004809B2 (en) | Semiconductor device and operation method thereof | |
| CN107204203B (en) | Memory array and reading, programming and erasing operation method thereof | |
| CN106775442A (en) | Accumulator system and its operating method | |
| CN106504791A (en) | The method of storage device, storage system, operating memory device and storage system | |
| CN103000218A (en) | Memory circuit | |
| TW201419287A (en) | Memory devices and operating methods for a memory device | |
| CN103903650B (en) | Memory array and its control method and flash memory | |
| US9299442B2 (en) | Dynamic data caches, decoders and decoding methods | |
| CN107481758A (en) | A kind of operating method of memory | |
| CN107025177A (en) | Accumulator system and its operating method | |
| CN105931667A (en) | Programming method for flash memory | |
| CN102568567B (en) | Flash memory operation method | |
| KR20110041285A (en) | Flash memory device and program and channel pre-charge methods thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |