CN102547291B - Field programmable gate array (FPGA)-based joint photographic experts group (JPEG) 2000 image decoding device and method - Google Patents
Field programmable gate array (FPGA)-based joint photographic experts group (JPEG) 2000 image decoding device and method Download PDFInfo
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Abstract
The embodiment of the invention discloses a field programmable gate array (FPGA)-based joint photographic experts group (JPEG) 2000 image decoding device, which comprises a decoding controller, a code stream input cache, a code stream resolver, an embedded block coding with optimized truncation (EBCOT) decoder, an inverse quantizer, an external memory controller, an inverse wavelet transform arithmetic unit, a multi-component converter and a pixel output cache. The invention also discloses an FPGA-based JPEG2000 image decoding method. By the device and the method, high-bit rate and high-frame rate real-time decoding output of the JPEG2000 image can be realized, and the device and the method are highly flexible.
Description
Technical field
The present invention relates to technical field of image processing, particularly a kind of JPEG2000 picture decoding apparatus and method based on FPGA.
Background technology
JPEG2000 standard is a kind of high-quality still image coding standard, and the image coding and decoding algorithm of the different compression quality grades from Lossless Compression to lossy compression method can be provided.Along with the develop rapidly of digital technology, the digitlization process of the film whole world advances fast.U.S.'s digital camera is advocated tissue (DCI) and has been issued DCIv1.0 standard in 2005, and according to this standard, digital movie adopts the first (ISO/IEC15444-1) of JPEG2000 standard as Standard of image compression.
Because JPEG2000 coding standard has compressed image quality height, algorithm complex is high simultaneously, thereby the decoded portion employing of the Play System of digital cinema devices manufacturer release realizes based on ASIC (application-specific integrated circuit (ASIC)) or high-end DSP (digital signal processor).
The scheme that represents based on ASIC is generally to realize based on multi-disc ADV202 process chip at present, in the 2K resolution epoch, uses wider.And along with digital movie, by 2K resolution, to the even higher 8K resolution of 4K, developed the follow-up developments that system is complicated, the defects such as obvious very flexible that power consumption is high and permanent circuit designs have directly hindered this scheme that adopt multi-disc ASIC to bring.
Although realize distinctive high flexibility and scheme based on High Performance DSP possesses software, but for high-resolution digital film, due to DSP internal hardware unit not for the EBCOT compression/de-compression of JPEG2000 and just/contrary DWT convert and design, be difficult to tackle the film broadcasting application in real time of high code check, high data rate, thereby mainly use in non real-time applications such as medical treatment.
Therefore, at digital movie, under the background of more high-resolution and the development of Geng Gao frame per second, existing traditional JPEG2000 decoding chip can not meet higher code check disposal ability, higher frame per second fan-out capability, and flexibility and requirement of real-time.
Summary of the invention
In view of this, the invention provides a kind of JPEG2000 picture decoding apparatus and method based on field programmable gate array (FPGA), can carry out the JPEG2000 image real-time decoding output of high code check, high frame per second, also possess the flexibility of height simultaneously.
For reaching above-mentioned purpose, technical scheme of the present invention is specifically achieved in that
A kind of JPEG2000 picture decoding apparatus based on on-site programmable gate array FPGA, this device comprises: decode controller, code stream input-buffer, code stream analyzing device, built-in optimization blocks coding EBCOT decoder, inverse quantizer, external storage controller, inverse wavelet transform arithmetic unit, many minutes energy converters and pixel output buffer memory;
Wherein, decode controller is connected with pixel output buffer memory with code stream input-buffer, code stream analyzing device, EBCOT decoder, inverse quantizer, external storage controller, inverse wavelet transform arithmetic unit, many minutes energy converters respectively, for carrying out the control of each assembly;
Code stream input-buffer, code stream analyzing device, EBCOT decoder, inverse quantizer are connected successively with external storage controller, and input, code stream analyzing and the parameter extraction, code block data decompression, the code block data inverse that complete successively JPEG2000 code stream quantize and subband data reconstruction and storage;
External storage controller, inverse wavelet transform arithmetic unit, many minutes energy converters are connected successively with pixel output buffer memory, complete successively subband data and read in the many components conversions with inverse wavelet transform, view data, last output pixel data and correlation timing signal;
External storage controller is connected with inverse wavelet transform arithmetic unit with inverse quantizer, is connected again in addition with exterior storage, realizes the access control of decoded data.
Preferably, described code stream analyzing device comprises: resolve kernel, geometry coprocessor and code block packed data buffer memory;
Resolve kernel and from code stream, extract image level global geometric parameters, and the geometric parameter of each code block providing according to geometry coprocessor extracts code block packed data and the code block decoding parametric of each code block in code stream; Code block packed data and code block decoding parametric are sent into code block packed data buffer memory to be cushioned; How much coprocessors calculate the geometric parameter of each code block in code stream according to the image level global geometric parameters of described parsing kernel extraction, and provide it to code stream analyzing kernel.
Preferably, described EBCOT decoder comprises: arithmetic decoder, bit plane modeling device and code block bit plane memory;
Arithmetic decoder is extracted code block packed data and code block decoding parametric from code block packed data buffer memory, and and bit plane modeling device coordinated the decoding computing of code block packed data, obtain bit-plane data and the affiliated information of code block of code block, and deposit bit plane memory in;
Bit plane memory is delivered to inverse quantizer by data.
Preferably, described inverse quantizer comprises: inverse quantization unit, frame memory interface, code block wavelet data buffer memory;
Inverse quantization unit is obtained the relative decoding parameters such as quantization table the code block bit-plane data receiving from described bit plane memory is carried out to re-quantization calculating from decode controller;
Frame memory interface completes corresponding subband wavelet data address according to information under code block and converts, and the code block wavelet data after re-quantization deposits external memory storage according to corresponding subband wavelet data address in by external storage controller after cushioning via inner code block wavelet data buffer memory.
Preferably, described inverse wavelet transform arithmetic unit comprises: computing controller, Data Management Unit, inverse wavelet transform kernel unit;
Calculation control unit generates the scheduling controlling of whole computational process according to image and subband geometric parameter and wavelet transformation progression, coordinate to control the parallel running of Data Management Unit and inverse wavelet transform kernel unit;
Data Management Unit completes the required data memory access of inverse wavelet transform and data buffering storage under scheduling controlling arrangement;
Inverse wavelet transform kernel unit is carried out inverse wavelet transform calculating, and will finally export and deliver to many minutes energy converters and carry out component conversion.
Preferably, this device comprises the parallel running of a plurality of EBCOT decoder, and a plurality of EBCOT decoders read separately required code block packed data according to time-sharing multiplex from code block packed data buffer memory; And each EBCOT decoder output decoding progress indication is for inquiry and control;
The bit-plane data of described inverse quantizer from a plurality of EBCOT decoder receipt decodings, by inquiring about the completion status of each EBCOT decoder, reads current ready code block bit-plane data carry out re-quantization from corresponding EBCOT decoder.
A JPEG2000 picture decoding method based on FPGA, the method comprises:
Code stream input-buffer receives the JPEG2000 bit stream data row buffering of going forward side by side from outside code stream generator, and the JPEG2000 code stream after buffering is sent into code stream analyzing device;
Code stream analyzing device is resolved JPEG2000 code stream, obtains each code block packed data and code block decoding parametric;
EBCOT decoder reads each code block packed data and code block decoding parametric from code stream analyzing device, carries out the decompression calculations of the bit-plane data of each code block;
Inverse quantizer reads the bit-plane data of EBCOT decoder output and carries out re-quantization calculating according to quantization step, obtains the code block wavelet data after re-quantization; Code block wavelet data after described re-quantization is written to external memory storage to rebuild each subband wavelet coefficient of image;
Inverse wavelet transform arithmetic unit reads in each subband wavelet coefficient and carries out two-dimentional inverse wavelet transform calculating from exterior storage, and result of calculation exports many minutes energy converters to and carries out component conversion;
Within many minutes, energy converter carries out component conversion operations according to decoding parametric, and the pixel component data after component conversion are sent into pixel output buffer memory;
Pixel output buffer memory receives pixel component data from many minutes energy converters, and carries out view data output according to definite pixel output clock speed, sends the capable frame sequential indication of associated picture simultaneously.
Preferably, described code stream analyzing device is resolved JPEG2000 code stream, obtains each code block packed data and code block decoding parametric, comprising:
Code stream analyzing device reads JPEG2000 bit stream data from code stream input-buffer, recovers the global solution code parameters information that code stream includes; The concrete geological information that calculates current each code block of code stream according to the progressive parameter in global solution code parameters, geometric parameter information and wavelet transform DWT progression parameter call inner geometry coprocessor, inner code stream analyzing kernel is resolved code stream and then is extracted each code block packed data and code block decoding parametric on code block geological information basis.
Preferably, described EBCOT decoder reads each code block packed data and code block decoding parametric from code stream analyzing device, carries out the decompression calculations of the bit-plane data of each code block, comprising:
EBCOT decoder reads each code block packed data and code block decoding parametric from the code block packed data buffer memory of code stream analyzing device inside, arithmetic decoder and bit plane modeling device code-aiming block by EBCOT decoder inside carry out the calculating of bit plane one by one, will use code block packed data and code block decoding parametric as decoding input in this computational process.
Preferably, described inverse quantizer reads the bit-plane data of EBCOT decoder output and carries out re-quantization calculating according to quantization step, obtains the code block wavelet data after re-quantization, comprising:
Inverse quantizer obtains the quantization parameter of current code block to calculate current quantization step according to code block decoding parametric, read the bit-plane data of EBCOT decoder output and by inner inverse quantization unit, carry out re-quantization calculating according to quantization step, obtaining the code block wavelet data after re-quantization.
As seen from the above technical solution, this JPEG2000 picture decoding apparatus and method based on FPGA of the present invention, the perfect hardware logic electric circuit resource possessing by FPGA, realized and met JPEG2000 image decoding standard, and be exclusively used in the logical circuit of JPEG2000 image decoding, reach high code check, the requirement of the JPEG2000 image real-time decoding output of high frame per second, the hardware programmable characteristic of while based on FPGA, make its flexibility very high, do not changing under the prerequisite of chip, be easy to realize by revising Logic Circuit Design the lifting of performance and function, follow-up developments space is very large.
Accompanying drawing explanation
Fig. 1 is the JPEG2000 picture decoding apparatus structural representation of the embodiment of the present invention.
Fig. 2 is the JPEG2000 picture decoding method flow chart of the embodiment of the present invention.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The present invention is mainly the perfect hardware logic electric circuit resource possessing based on FPGA, designed the logical circuit that is exclusively used in JPEG2000 image decoding, realized the JPEG2000 image real-time decoding output of high code check, high frame per second, the hardware programmable characteristic of while based on FPGA, make its flexibility very high, do not changing under the prerequisite of chip, be easy to realize by revising Logic Circuit Design the lifting of performance and function, follow-up developments space is very large.
Specific design as shown in Figure 1, comprise: decode controller 100, code stream input-buffer 200, code stream analyzing device 300, built-in optimization blocks coding (EBCOT) decoder 400, inverse quantizer 500, external storage controller 600, inverse wavelet transform arithmetic unit 700, within many minutes, energy converter 800, pixel output buffer memory 900;
Decode controller 100 is connected with pixel output buffer memory 900 with code stream input-buffer 200, code stream analyzing device 300, EBCOT decoder 400, inverse quantizer 500, external storage controller 600, inverse wavelet transform arithmetic unit 700, many minutes energy converters 800 respectively, according to the various control commands that receive from outside, complete the decoding of JPEG2000 image code stream is controlled;
Code stream input-buffer 200, code stream analyzing device 300, EBCOT decoder 400, inverse quantizer 500 and external storage controller 600 are connected successively, and input, code stream analyzing and the parameter extraction, code block data decompression, the code block data inverse that complete JPEG2000 code stream quantize and subband data reconstruction and storage;
External storage controller 600, inverse wavelet transform arithmetic unit 700, many minutes energy converters 800 are connected successively with pixel output buffer memory 900, complete subband data and read in the many components conversion with inverse wavelet transform, view data, last output pixel data and correlation timing signal;
External storage controller 600 is connected with inverse wavelet transform arithmetic unit 700 with inverse quantizer 500, is connected again in addition with exterior storage (being generally SDRAM), realizes the access control of decoded data.
Wherein decode controller 100 is set up communication by external interface and outside main control system, receive outside decoding control command and externally return to decoded state information, code stream input-buffer 200, code stream analyzing device 300, EBCOT decoder 400, inverse quantizer 500, external storage controller 600, inverse wavelet transform arithmetic unit 700, many minutes energy converters 800 and pixel output buffer memory 900 are controlled and coordinated to decode controller 100, completes the hardware decoding of JPEG2000 image.
Code stream input-buffer 200 completes the input adaptation of outside JPEG2000 image code stream and the code stream after buffering is delivered to code stream analyzing device 300, and pixel output buffer memory 900 completes the buffer-stored of pixel data output so that the output of the pixel data after adaptation to be provided.
Wherein code stream analyzing device 300 comprises: resolve kernel 310, how much coprocessors 320, code block packed data buffer memory 330;
Code stream analyzing device 300 is resolved by resolving 310 pairs of code streams of kernel according to JPEG2000 standard, code stream analyzing device 300 needs the geometric parameter information of each code block in resolving, in code stream analyzing device 300 inside, comprise how much coprocessors 320, how much coprocessors 320 calculate the geometric parameter of each code block in code stream according to the image level global geometric parameters of resolving extraction, provide it to the correct extraction that code stream analyzing kernel 310 completes code block packed data and code block decoding parametric.Resolve kernel 310 and extract code block packed data and relative decoding parameter, and by delivering to EBCOT decoder 400 after inner code block packed data buffer memory 330 bufferings.Resolving the relative decoding parameter of kernel 310 extractions delivers to decode controller 100 simultaneously and by decode controller 100, delivers to other decoding function modules and use.Decoding capability high-resolution, high code check and high frame per second being required for possessing reply digital film domain, when the code stream analyzing of JPEG2000, can use dynamic memory management by district technology code-aiming block packed data buffer memory 330 effectively to use, code block packed data buffer memory 330 can be stored at internal damping packed data and the code block decoding parametric of a plurality of code blocks, effectively reduce the capacity requirement to buffer memory, dynamic memory management by district complete the inner minute panel region of storage idle mark, write mark, ready mark and usage flag.
EBCOT decoder 400 comprises: arithmetic decoder 410, bit plane modeling device 420, code block bit plane memory 430;
EBCOT decoder 400 completes the decoding computing of code block packed data by internal arithmetic decoder 410 and bit plane modeling device 420, deposit information under bit-plane data and code block in local bit plane memory 430, local bit plane memory 430 is delivered to inverse quantizer 500 again by data.Wherein, the packed data of the required code block of decoding and code block decoding parametric can obtain from code block packed data buffer memory 330, and in addition, decoding parametric also can obtain from decode controller 100; In better enforcement, by adopting the parallel running of a plurality of EBCOT decoder can greatly improve the EBCOT decoding capability of system, a plurality of EBCOT decoders can read separately required code block packed data from code block packed data buffer memory 330 according to time-sharing multiplex.Therefore in concrete enforcement, the actual use number of EBCOT decoder can be adjusted as required, is not limited to only use an example.
Inverse quantizer 500 comprises: inverse quantization unit 510, frame memory interface 520, code block wavelet data buffer memory 530;
Inverse quantizer 500 obtains the relative decoding parameters such as quantization table from decode controller 100, the code block bit-plane data of 510 pairs of receptions of inverse quantization unit carries out re-quantization calculating, frame memory interface 520 completes corresponding subband wavelet data address according to information under code block and converts, code block wavelet data after re-quantization deposits outside SDRAM according to corresponding subband wavelet data address in by external storage controller 600 after cushioning via inner code block wavelet data buffer memory 530, this buffer storage 530 is used dynamic memory management by district technology that the buffer-stored of a plurality of code block wavelet coefficients is provided, 500 pairs of ready code block wavelet data of inverse quantizer write external memory storage with the subband wavelet data at different levels of reconstructed image by external storage controller 600 after scheduling.The bit-plane data that inverse quantizer 500 can be from a plurality of EBCOT decoder receipt decodings in better enforcement, by inquiring about the completion status of each EBCOT decoder, current ready code block bit-plane data is read and carried out re-quantization from corresponding EBCOT decoder, can support thus the parallel running of many EBCOT decoder.
The actual physics accessing operation that external storage controller 600 is realized external memory storage, invents by external memory storage the multi-channel parallel I/O that a multiport memory is realized decoder.The subband wavelet data that external memory storage can be stored multiple image, realizes the water operation of image level with this.
Inverse wavelet transform arithmetic unit 700 comprises: computing controller 710, Data Management Unit 720, inverse wavelet transform kernel unit 730.
Inverse wavelet transform arithmetic unit 700 inside are by calculation control unit 710, Data Management Unit 720 and inverse wavelet transform kernel unit 730 form, calculation control unit 710 generates the scheduling controlling of whole computational process according to image and subband geometric parameter and wavelet transformation progression, Data Management Unit 720 completes the required data memory access of inverse wavelet transform and the locally buffered storage of data under scheduling controlling arrangement, inverse wavelet transform kernel unit 730 adopts the streamline based on Lifting Scheme to realize, inverse wavelet transform kernel module is concrete to be used 9/7 Lifting Wavelet framework and possesses 16 station accuracies.Calculation control unit 710 coordinates to control the parallel running of Data Management Unit 720 and inverse wavelet transform kernel unit 730, completes at a high speed the inverse wavelet transform evaluation works at different levels of image.
The final output of inverse wavelet transform arithmetic unit 700 is delivered to many minutes energy converters 800 and is carried out component conversion, the inner real-time component conversion of using Pixel-level streamline to realize pixel data of energy converter 800 in many minutes, and within many minutes, energy converter 700 possesses 16 station accuracies.Pixel output buffer memory 900 receives pixel component data and cushions for external device (ED) and read in inside from many minutes energy converters 800, and decode controller 100 is set pixel output clock speed and by pixel output buffer memory 900, sends the capable frame sequential of associated picture and indicate according to image geometry parameter and output image frame per second.
Utilize above-mentioned decoding device when carrying out the decoding of JPEG2000 image code stream, concrete decoding process as shown in Figure 2, comprises the steps:
Step 201, receives and buffer memory code stream;
Code stream input-buffer 200 receives the JPEG2000 bit stream data row buffering of going forward side by side according to the control of decode controller 100 from outside code stream generator, and the JPEG2000 code stream after buffering will be sent into code stream analyzing device 300.
Wherein, code stream input-buffer 200 can adopt the buffering method of first in first out (FIFO).
Step 202, code stream analyzing
Code stream analyzing device 300 is according to after the data ready that is controlled at code stream input 200 of decode controller 100, JPEG2000 code stream being resolved.
Code stream analyzing device 300 reads JPEG2000 bit stream data from code stream input-buffer 200 and carries out code stream analyzing, recovers the global solution code parameters information that code stream includes; According to the progressive parameter in global solution code parameters, geometric parameter information and wavelet transform (DWT) progression parameter etc., call the concrete geological information that geometry coprocessor 320 calculates current each code block of code stream, code stream analyzing kernel 310 is resolved code stream and then is extracted each code block packed data and code block decoding parametric on code block geological information basis, and by delivering to EBCOT decoder 400 after code block packed data buffer memory 330 bufferings.
Wherein, code block packed data buffer memory 330 can carry out effective usage data buffer memory by dynamic memory management by district technology.
Step 203, EBCOT decoding
EBCOT decoder 400 is according to carrying out the decompression calculations of code block bit-plane data after the data ready that is controlled at code block packed data buffer memory 330 of decode controller 100.
EBCOT decoder 400 reads each code block packed data and code block decoding parametric from the code block packed data buffer memory 330 of code stream analyzing device 300 inside, carry out the decompression calculations of the bit-plane data of each code block, particularly, arithmetic decoder 410 and bit plane modeling device 420 code-aiming blocks by EBCOT decoder 400 inside carry out the calculating of bit plane one by one, in this computational process, will use code block packed data and code block decoding parametric as decoding input, after the bit-plane data of code block all calculates, the bit-plane data of code block and code block decoding parametric are stored to bit plane memory 430, by bit plane memory 430, data are delivered to inverse quantizer 500 again.
Wherein, EBCOT decoder 400 can have a plurality of, a plurality of EBCOT decoders 400 can utilize the interblock independence of code block packed data to carry out the parallel decoding of a plurality of code blocks, functional independence between each EBCOT decoder 400, for realizing the coordination between a plurality of EBCOT decoders 400, each EBCOT decoder can be exported the indication of decoding progress for inquiry and control.
Step 204, re-quantization and image reconstruction
Inverse quantizer 500, according to the control of decode controller 100, carries out re-quantization and image reconstruction after the ready indication of code block bit-plane data that inquires 400 outputs of EBCOT decoder.
Inverse quantizer 500 obtains the quantization parameter of current code block to calculate current quantization step from decode controller 100 according to code block decoding parametric, read the bit-plane data of EBCOT decoder output and by inverse quantization unit 510, carry out re-quantization calculating according to quantization step, code block wavelet data after re-quantization is stored in code block wavelet data buffer memory 530, frame memory interface 520 completes the conversion of outside subband wavelet data memory address corresponding to current code block data according to code block decoding parametric, and by external storage controller 600, the code block wavelet data after re-quantization is written to external memory storage to rebuild each subband wavelet coefficient of image,
Wherein, the actual physics accessing operation that data external storage control 600 is realized external memory storage, receives data access request and responds from inverse quantizer 500, and the code block wavelet data of carrying out after re-quantization is write out operation; From inverse wavelet transform arithmetic unit 700, receive data access request and respond, completing the memory access with intermediate data of reading of each subband wavelet coefficient; The subband wavelet data that external memory storage 600 can be stored multiple image, realizes the data isolation of image level water operation with this.
Step 205, inverse wavelet transform
Inverse wavelet transform arithmetic unit 700 is according to the calculating that each subband wavelet coefficient in exterior storage carries out two-dimentional inverse wavelet transform after ready that is controlled at of decode controller 100.
The wavelet transformation progression that computing controller 710 provides according to decode controller 100 and each subband geometric parameter generate computational process and control, the Data Management Unit 720 of inverse wavelet transform arithmetic unit 700 inside is controlled the accessing operation that carries out subband wavelet coefficient by external storage controller 600 according to computational process, the inverse wavelet transform kernel unit 730 of inverse wavelet transform arithmetic unit inside is carried out inverse wavelet transforms at different levels to each subband wavelet coefficient under computational process is controlled, inverse wavelet transform kernel module tool can be used 9/7 Lifting Wavelet framework to realize, possess 16 station accuracies, the final output of inverse wavelet transform arithmetic unit 700 is delivered to many minutes energy converters 800 and is carried out component conversion.
Step 206, component conversion
Within many minutes, energy converter 800 carries out pixel component conversion according to the control of decode controller 100.
The decoding parametric that many minutes energy converters 800 provide according to decode controller 100 carries out parameter configuration to the component change-over circuit of its inside, be specially and set the matrix parameter that internal matrix vector is taken advantage of circuit, within many minutes, energy converter 800 completes the component conversion operations of regulation according to pixel flowing mode, it possesses 16 station accuracies, and the pixel component data after component conversion are sent into pixel output buffer memory 900;
Step 207, decoded bit stream output
Pixel output buffer memory 900 carries out the output of decoded bit stream according to the control of decode controller 100.
Pixel output buffer memory 900 receives the output of pixel component data flowing water and cushions for external device (ED) and read in inside from many minutes energy converters 800, and by image geometry parameter and the definite pixel output clock speed of output image frame per second, carry out view data output according to decode controller 100, send the capable frame sequential indication of associated picture simultaneously.
From the above embodiments, because FPGA technology has in recent years obtained great development, now can be towards the high compute-intensive applications of complexity from being transformed into towards the alternative application of pure logic on a small scale at first.In present stage FPGA device, except being integrated with abundant configurable logic block resource (CLB), also comprise a large amount of DSP embedded hardware capability unit (as DSP48) towards computation-intensive application, block RAM (block RAM), distributed memory, Clock management module (DCM) and for the serial Transmit-Receive Unit of high-speed communication.Simultaneously around FPGA, design and develop flow process, each FPGA manufacturer released a series of front and back end developing instrument and FPGA at sheet logic analysis testing tool, on software and hardware, guaranteed to realize reliably high-performance calculation on FPGA.Therefore, this JPEG2000 picture decoding apparatus and method based on FPGA of the present invention, can reach the requirement of the JPEG2000 image real-time decoding output of high code check, high frame per second completely, the hardware programmable characteristic of while based on FPGA, make its flexibility very high, do not changing under the prerequisite of chip, be easy to realize by revising Logic Circuit Design the lifting of performance and function, follow-up developments space is very large.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (8)
1. the JPEG2000 picture decoding apparatus based on on-site programmable gate array FPGA, it is characterized in that, this device comprises: decode controller, code stream input-buffer, code stream analyzing device, built-in optimization blocks coding EBCOT decoder, inverse quantizer, external storage controller, inverse wavelet transform arithmetic unit, many minutes energy converters and pixel output buffer memory;
Wherein, decode controller is connected with pixel output buffer memory with code stream input-buffer, code stream analyzing device, EBCOT decoder, inverse quantizer, external storage controller, inverse wavelet transform arithmetic unit, many minutes energy converters respectively, for carrying out the control of each assembly;
Code stream input-buffer, code stream analyzing device, EBCOT decoder, inverse quantizer are connected successively with external storage controller, and input, code stream analyzing and the parameter extraction, code block data decompression, the code block data inverse that complete successively JPEG2000 code stream quantize and subband data reconstruction and storage;
External storage controller, inverse wavelet transform arithmetic unit, many minutes energy converters are connected successively with pixel output buffer memory, complete successively subband data and read in the many components conversions with inverse wavelet transform, view data, last output pixel data and correlation timing signal;
External storage controller is connected with inverse wavelet transform arithmetic unit with inverse quantizer, is connected again in addition with exterior storage, realizes the access control of decoded data;
Described code stream analyzing device comprises: resolve kernel, geometry coprocessor and code block packed data buffer memory;
Resolve kernel and from code stream, extract image level global geometric parameters, and the geometric parameter of each code block providing according to geometry coprocessor extracts code block packed data and the code block decoding parametric of each code block in code stream; Code block packed data and code block decoding parametric are sent into code block packed data buffer memory to be cushioned;
How much coprocessors calculate the geometric parameter of each code block in code stream according to the image level global geometric parameters of described parsing kernel extraction, and provide it to parsing kernel.
2. device as claimed in claim 1, is characterized in that, described EBCOT decoder comprises: arithmetic decoder, bit plane modeling device and code block bit plane memory;
Arithmetic decoder is extracted code block packed data and code block decoding parametric from code block packed data buffer memory, and and bit plane modeling device coordinated the decoding computing of code block packed data, obtain bit-plane data and the affiliated information of code block of code block, and deposit bit plane memory in;
Bit plane memory is delivered to inverse quantizer by data.
3. device as claimed in claim 2, is characterized in that, described inverse quantizer comprises: inverse quantization unit, frame memory interface, code block wavelet data buffer memory;
Inverse quantization unit is obtained relative decoding parameter from decode controller the code block bit-plane data receiving from described bit plane memory is carried out to re-quantization calculating; Described relative decoding parameter at least comprises quantization table;
Frame memory interface completes corresponding subband wavelet data address according to information under code block and converts, and the code block wavelet data after re-quantization deposits external memory storage according to corresponding subband wavelet data address in by external storage controller after cushioning via inner code block wavelet data buffer memory.
4. device as claimed in claim 1, is characterized in that, described inverse wavelet transform arithmetic unit comprises: computing controller, Data Management Unit, inverse wavelet transform kernel unit;
Calculation control unit generates the scheduling controlling of whole computational process according to image and subband geometric parameter and wavelet transformation progression, coordinate to control the parallel running of Data Management Unit and inverse wavelet transform kernel unit;
Data Management Unit completes the required data memory access of inverse wavelet transform and data buffering storage under scheduling controlling arrangement;
Inverse wavelet transform kernel unit is carried out inverse wavelet transform calculating, and will finally export and deliver to many minutes energy converters and carry out component conversion.
5. device as claimed in claim 1, is characterized in that, this device comprises the parallel running of a plurality of EBCOT decoder, and a plurality of EBCOT decoders read separately required code block packed data according to time-sharing multiplex from code block packed data buffer memory; And each EBCOT decoder output decoding progress indication is for inquiry and control;
The bit-plane data of described inverse quantizer from a plurality of EBCOT decoder receipt decodings, by inquiring about the completion status of each EBCOT decoder, reads current ready code block bit-plane data carry out re-quantization from corresponding EBCOT decoder.
6. the JPEG2000 picture decoding method based on FPGA, is characterized in that, the method comprises:
Code stream input-buffer receives the JPEG2000 bit stream data row buffering of going forward side by side from outside code stream generator, and the JPEG2000 code stream after buffering is sent into code stream analyzing device;
Code stream analyzing device reads JPEG2000 bit stream data from code stream input-buffer, recovers the global solution code parameters information that code stream includes; The concrete geological information that calculates current each code block of code stream according to the progressive parameter in global solution code parameters, geometric parameter information and wavelet transform DWT progression parameter call inner geometry coprocessor, inner code stream analyzing kernel is resolved code stream and then is extracted each code block packed data and code block decoding parametric on code block geological information basis;
EBCOT decoder reads each code block packed data and code block decoding parametric from code stream analyzing device, carries out the decompression calculations of the bit-plane data of each code block;
Inverse quantizer reads the bit-plane data of EBCOT decoder output and carries out re-quantization calculating according to quantization step, obtains the code block wavelet data after re-quantization; Code block wavelet data after described re-quantization is written to external memory storage to rebuild each subband wavelet coefficient of image;
Inverse wavelet transform arithmetic unit reads in each subband wavelet coefficient and carries out two-dimentional inverse wavelet transform calculating from exterior storage, and result of calculation exports many minutes energy converters to and carries out component conversion;
Within many minutes, energy converter carries out component conversion operations according to decoding parametric, and the pixel component data after component conversion are sent into pixel output buffer memory;
Pixel output buffer memory receives pixel component data from many minutes energy converters, and carries out view data output according to definite pixel output clock speed, sends the capable frame sequential indication of associated picture simultaneously.
7. method as claimed in claim 6, is characterized in that, described EBCOT decoder reads each code block packed data and code block decoding parametric from code stream analyzing device, carries out the decompression calculations of the bit-plane data of each code block, comprising:
EBCOT decoder reads each code block packed data and code block decoding parametric from the code block packed data buffer memory of code stream analyzing device inside, arithmetic decoder and bit plane modeling device code-aiming block by EBCOT decoder inside carry out the calculating of bit plane one by one, will use code block packed data and code block decoding parametric as decoding input in this computational process.
8. method as claimed in claim 6, is characterized in that, described inverse quantizer reads the bit-plane data of EBCOT decoder output and carries out re-quantization calculating according to quantization step, obtains the code block wavelet data after re-quantization, comprising:
Inverse quantizer obtains the quantization parameter of current code block to calculate current quantization step according to code block decoding parametric, read the bit-plane data of EBCOT decoder output and by inner inverse quantization unit, carry out re-quantization calculating according to quantization step, obtaining the code block wavelet data after re-quantization.
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