CN102546305A - Method and device for accessing error detection of bidirectional linked list - Google Patents
Method and device for accessing error detection of bidirectional linked list Download PDFInfo
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Abstract
An embodiment of the invention provides a method and a device for accessing error detection of a bidirectional linked list. The method includes that a current pointer and a previous pointer of the bidirectional linked list are stored in a logic controller, the current pointer is used for identifying a bidirectional linked list node which needs to be accessed by this time, the previous pointer is used for identifying a bidirectional linked list node which is accessed by last time, and the initial direction of the current pointer points to a first node of the bidirectional linked list. The method includes: obtaining nodes of the bidirectional linked list according to the current pointer, and determining that accessing of the bidirectional linked list makes mistakes when a precursor node pointer of the obtained nodes of the bidirectional linked list is unequal to the previous pointer. A device for accessing error detection of the bidirectional linked list is further provided. The method and the device can perform real-time error detection on linked list accessing to avoid system breakdown caused by linked list accessing errors when application programs access the linked list through a field programmable gata array (FPGA).
Description
Technical field
The embodiment of the invention relates to communication technical field, relates in particular to a kind of method and device of doubly linked list visit error detection.
Background technology
(Field Programmable Gate Array FPGA) is used to handle the business that becomes increasingly complex to current field programmable gate array, and FPGA is more and more frequent with use to the chain table handling.Fig. 1 is a kind of common doubly linked list structural representation; As shown in Figure 1, this doubly linked list has n+1 node, and node 0 is the first node of chained list; Node n is the tail node of chained list; Each chained list node has three attributes: data, forerunner's node pointer and descendant node pointer, and wherein, data are exactly the data of chained list node management; Forerunner's node pointer is being deposited the memory address of forerunner's node adjacent with this node on this chained list, and for node 0, this address is a null value, points to node 0 for node 1 its forerunner's node pointer; The descendant node pointer is being deposited the memory address of descendant node adjacent with this node on this chained list, and for node n, this address is a null value, points to node 2 for node 1 its follow-up node pointer.When chained list being managed with FPGA because the chained list complicated operation, use frequent, easy error, operation wrong back occurs and is difficult to find at once, and causes system crash easily.When FPGA realizes the management to chained list; The reason that causes the chained list access errors mainly contains three kinds: 1, the external memory storage of storage chained list bit (bit) saltus step occurs and causes the chained list content false, for instance, and in Fig. 1; Wrong bit saltus step appears if external memory storage is deposited the corresponding position of descendant node pointer of node 0; Then this descendant node pointer possibly become illegal pointer, when FPGA makes amendment to this descendant node pointer content or visits, will cause system crash; 2, the application program read-write is crossed the border and is caused the chained list content to be rewritten; For instance, like Fig. 1, when the application program write-overflow is rewritten as illegal pointer with the descendant node pointer of node 0; When FPGA makes amendment to this descendant node pointer content or visits, will cause system crash; 3, FPGA external memory controller error causes reading and writing unexpected chained list node address.FPGA can the chained list that arrives of record current accessed in the chained list access process the pointer of node, and this pointer is stored in the logic controller of FPGA.When FPGA continues visit; Can continue the visit chained list from this pointer, can operate external memory storage through the outer memory controller of FPGA during the visit chained list, outer memory controller is used for the access request of RL controller to external memory storage; And external memory storage is carried out corresponding visit according to this access request; In this access process, if the external memory controller error, possibly cause returning to the chained list node of FPGA mistake, as shown in Figure 1; When FPGA has access to chained list node 1; Can the pointer of node 1 be stored in the logic controller of FPGA, when this chained list of the follow-up continuation visit of FPGA, utilize the pointer of the node 1 of the last time chain table access of storing in this logic controller to pass through the chained list in the external memory controller access external memory storage; If the peripheral control unit mistake causes other nodes of the non-node 1 of access external memory, these other node contents are made amendment or visit may cause system crash.At present; Usually can utilize the method for pointer redundancy backup to realize real-time error detection; When the storage chains list index, FPGA can store two parts of identical chained lists simultaneously, when chained list node is visited; The data content of two parts of chained list nodes only reading is identical thinks that just the chain table access is correct; Otherwise think that the chain table access has taken place unusually, it is more effective that this method the cross the border chained list access errors that causes the chained list content to be changed to cause of bit saltus step and application program read-write occurs for the external memory storage that prevents to store chained list, but cause reading and writing chained list access errors that unexpected chained list node address causes and inapplicable for FPGA external memory controller error; Because just relatively whether the data content of two parts of chained list nodes is identical, can not explain whether the chain list index of being visited is correct.
Summary of the invention
The embodiment of the invention provides a kind of method and device of doubly linked list visit error detection; FPGA to the chained list management process in; Solution is in application program during through FPGA visit doubly linked list, the chained list access errors occurs and can't in time, effectively detect, and causes the problem of system crash.
For achieving the above object, the embodiment of the invention provides a kind of method of doubly linked list visit error detection, and said method comprises:
In logic controller, deposit the current pointer of said doubly linked list and pointer last time; Said current pointer is used to identify the said doubly linked list node of this less important visit; Said last time pointer is used to identify the last time said doubly linked list node of visit; The first node of the said doubly linked list of said current pointer initial directional, said method comprises:
Obtain the node of said doubly linked list according to said current pointer;
Forerunner's node pointer of the node of the said doubly linked list that obtains and said last time when pointer is unequal confirms that said doubly linked list visit makes mistakes.
The embodiment of the invention provides a kind of device of doubly linked list visit error detection, and said device comprises:
Initialization unit; Be used for when doubly linked list generates; In logic controller, deposit the current pointer of said doubly linked list and pointer last time; Said current pointer is used to identify the said doubly linked list node of this less important visit, and said last time pointer is used to identify the last time said doubly linked list node of visit, the first node of the said doubly linked list of said current pointer initial directional;
Acquiring unit is used for obtaining according to said current pointer the node of said doubly linked list;
Confirm the unit, be used for forerunner's node pointer of node of the said doubly linked list that obtains and said last time when pointer is unequal, confirm that said doubly linked list visit makes mistakes.
To sum up, the embodiment of the invention provides the method and the device of a kind of doubly linked list visit error detection, when application program conducts interviews to chained list through FPGA, can carry out in time the chain table access, effective error detection.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a kind of common doubly linked list structural representation in the prior art;
Fig. 2 is the method flow sketch map of a kind of doubly linked list visit error detection that provides of the embodiment of the invention one;
Fig. 3 is a doubly linked list sketch map in the method for a kind of doubly linked list visit error detection that provides of the embodiment of the invention;
Fig. 4 is the method medium chain sketch map after pointer and the current pointer renewal last time of a kind of doubly linked list visit error detection that provides of the embodiment of the invention;
Fig. 5 is an another kind of doubly linked list sketch map in the method for a kind of doubly linked list visit error detection that provides of the embodiment of the invention;
Fig. 6 is the device sketch map of first kind of doubly linked list access detection providing of the embodiment of the invention two;
Fig. 7 is the device sketch map of second kind of doubly linked list access detection providing of the embodiment of the invention two;
Fig. 8 is the device sketch map of the third doubly linked list access detection of providing of the embodiment of the invention two.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer; To combine the accompanying drawing in the embodiment of the invention below; Technical scheme in the embodiment of the invention is carried out clear, intactly description; Obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one:
The embodiment of the invention provides a kind of method of doubly linked list visit error detection, and referring to Fig. 2, Fig. 2 is the method flow diagram of the embodiment of the invention, comprising:
102, obtain the node of said doubly linked list according to current pointer;
104, forerunner's node pointer of the node of the doubly linked list of said acquisition confirms that said doubly linked list visit makes mistakes when last time pointer was unequal.
When programming device was managed chained list, chained list left in the external memory storage.Programming device comprises logic controller and outer memory controller etc.Programming device can be FPGA or application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit; ASIC); The embodiment of the invention is that example is described with FPGA, and FPGA is through the chained list in logic controller and the external memory controller access external memory storage.Logic controller is deposited the pointer of the chained list node of last time visiting and the pointer of the current chained list node that will visit.When FPGA receives the request of the chained list node in the application access external memory storage, according to the current chained list node pointer of depositing in the logical storage that will visit, through the chained list node in the external memory controller access external memory storage of FPGA.In this process, if the external memory controller error, possibly cause the chained list node of access errors.After doubly linked list generates, in logic controller, deposit the current pointer of doubly linked list and pointer last time, this current pointer is used to identify this doubly linked list node of this less important visit; This last time pointer be used to identify last time this doubly linked list node of visit; The first node of this doubly linked list is pointed in this current pointer initialization, this last time pointer be initialized as null value, so-called initialization is meant after chained list generates; Before to the chain table handling, to the initial value setting of the variable relevant with chained list.For instance, as shown in Figure 3, Fig. 3 is this doubly linked list sketch map, and wherein forerunner's node pointer of node 0 is a null value, and the descendant node pointer of node 0 is initialized as node 1, and node 0 is pointed in the current pointer initialization, and last time null value was pointed in the pointer initialization.When application program was visited this doubly linked list through FPGA, FPGA utilized the current pointer of depositing in the logic controller to pass through this doubly linked list of external memory controller access of FPGA.When application program is visited this doubly linked list through FPGA; According to this doubly linked list of the visit of this current pointer in the logic controller, obtain the node of this doubly linked list, forerunner's node pointer of judging this node with this last time pointer whether equate; If unequal then definite this chain table access makes mistakes; Further, if confirming that this chain table access makes mistakes can notify the visit of this doubly linked list of webmaster to make mistakes, and stop the visit of application program to this doubly linked list.If forerunner's node pointer of this node with this last time pointer equate, then with this last time pointer make amendment, the value of amended last time pointer is the value of this current pointer.Revise current pointer then, the value of amended current pointer is the value of the descendant node pointer of this node.As shown in Figure 4, Fig. 4 is forerunner's node pointer of confirming this node when last time pointer equated with this, the sketch map after this current pointer and the pointer modified last time, and last time pointer modified is a sensing node 0, current pointer is revised as sensing node 1.When next time, application program was through this doubly linked list of FPGA visit; FPGA is according to the node 1 of the external memory controller access of this current pointer in the logic controller through FPGA this doubly linked list in the external memory storage; Whether and last time forerunner's node pointer through decision node 1 pointer equates to judge whether chained list makes mistakes; If forerunner's node pointer of decision node 1 and last time pointer equate that then last time pointer modified is for pointing to node 1 with this, this current pointer is revised and is pointed to node 2.When this application program continues the subsequent node of this doubly linked list of visit through FPGA, its operating process and above-mentioned to node 0 or node 1 class of operation seemingly, do not giving unnecessary details at this.Preferably, when the doubly linked list initialization, the first node of this doubly linked list of forerunner's node pointer initial directional of the first node of doubly linked list, the first node of the said doubly linked list of said last time pointer initial directional.As shown in Figure 5, forerunner's node pointer of doubly linked list node 0 can initialization point to node 0, and node 0 is pointed in the current pointer initialization; Last time node 0 was pointed in the pointer initialization, realized that like this advantage is, had improved the accuracy in detection to the first node of this doubly linked list; When node 0 was detected, forerunner's node pointer value of last time pointer that compares and current pointer all was the address of node 0, rather than null value; In the operation of internal memory, the content initialization of internal memory all is to be set to null value usually, like this; When outer memory controller is made mistakes, through current pointer visit possibly not be node 0, and have access to another internal memory; And the content of this memory address all is a null value just, then can't judge the chained list access errors.And the address of node 0 is unique in the memory externally; The probability that occurs the value identical with this address in other core positions is very little; Therefore, through forerunner's node pointer of the first node of doubly linked list and last time the first node of pointer initial directional doubly linked list can improve accuracy in detection to the first node of this doubly linked list.
The method benefit of the chained list error detection that the embodiment of the invention provides is; When each FPGA visits the doubly linked list of external memory through logic controller; There is individual expected results in the capital, and this expected results judges through pointer last time, if last time pointer was unequal for forerunner's node pointer of the node of the doubly linked list of the external memory storage that obtains through logic controller and this; Think that then obtaining chained list node does not satisfy expected results, therefore can judge this doubly linked list mistake.Can solve like this because the problem of the chained list access errors that the external memory controller error of FPGA causes; For instance; If like Fig. 3 application program during, during this doubly linked list of external memory controller access through FPGA of the current pointer that utilizes logic controller, if the outer memory controller of FPGA is made mistakes through this doubly linked list of FPGA visit; Cause to visit the node 1 of this doubly linked list; But wrong visit the node n of this doubly linked list because forerunner's node pointer of node n is that last time the address of pointed node 0 was unequal with this address of node n-1, can judge then that this doubly linked list is visited to make mistakes.Simultaneously; The technical scheme that the embodiment of the invention provides is for because the read-write of wrong BIT position saltus step or application program appears in external memory storage crosses the border and cause chained list node forerunner node pointer suitable equally by the chained list access errors that rewriting causes, for instance, as shown in Figure 3; Wrong bit saltus step appears if external memory storage is deposited the corresponding position of forerunner's node pointer of node 1; This forerunner's node pointer becomes illegal pointer, so when application program during through this doubly linked list of FPGA visit, when utilizing the current pointer of logic controller to obtain the node 1 of this doubly linked list; Because forerunner's node pointer of node 1 has become illegal pointer; Last time pointer will be unequal with forerunner's node pointer of node 1 for this, therefore, can judge this doubly linked list access errors.
It is thus clear that; The method that provides through the embodiment of the invention; When application program is visited doubly linked list through FPGA; Can carry out real-time error detection to the visit of doubly linked list, when the chain table access makes mistakes, report webmaster and stop application program, can effectively solve the chain table access and make mistakes and cause the problem of system crash the chain table access.
Embodiment two:
The embodiment of the invention provides a kind of device of doubly linked list visit error detection, and referring to Fig. 6, Fig. 6 is the device sketch map of the embodiment of the invention, and this device comprises: initialization unit 602, acquiring unit 604 is confirmed unit 606.
Confirm unit 606, the forerunner's node pointer and the said last time pointer of node that is used for the said doubly linked list that obtains is unequal, confirms that then said doubly linked list visit makes mistakes.
When programming device was managed chained list, chained list left in the external memory storage.Programming device comprises logic controller and outer memory controller etc.Programming device can be FPGA or application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit; ASIC); The embodiment of the invention is that example is described with FPGA, and FPGA is through the chained list in logic controller and the external memory controller access external memory storage.Logic controller is deposited the pointer of the chained list node of last time visiting and the pointer of the current chained list node that will visit.When FPGA receives the request of the chained list node in the application access external memory storage, according to the current chained list node pointer of depositing in the logical storage that will visit, through the chained list node in the external memory controller access external memory storage of FPGA.In this process, if the external memory controller error, possibly cause the chained list node of access errors.After doubly linked list generates; Initialization unit 602 is deposited the current pointer of doubly linked list and pointer last time in logic controller; This current pointer is used to identify this doubly linked list node of this less important visit, this last time pointer be used to identify last time this doubly linked list node of visit, the first node of this doubly linked list is pointed in this current pointer initialization; This last time pointer be initialized as null value; So-called initialization is meant after chained list generates, before to the chain table handling, to the initial value setting of the variable relevant with chained list.For instance, as shown in Figure 3, Fig. 3 is this doubly linked list sketch map, and wherein forerunner's node pointer of node 0 is a null value, and the descendant node pointer of node 0 is initialized as node 1, and node 0 is pointed in the current pointer initialization, and last time null value was pointed in the pointer initialization.When application program was visited this doubly linked list through FPGA, FPGA utilized the current pointer of depositing in the logic controller to pass through this doubly linked list of external memory controller access of FPGA.When application program is visited this doubly linked list through FPGA; Acquiring unit 604 is according to this this doubly linked list of current pointer visit in the logic controller; Obtain the node of this doubly linked list; Forerunner's node pointer of confirming to judge this node in unit 606 with this last time pointer whether equate, if unequal then confirm that this chain table access makes mistakes.When next time, application program was through this doubly linked list of FPGA visit; Acquiring unit 604 is according to the node 1 of this current pointer in the logic controller through external memory controller access this doubly linked list in the external memory storage; Confirm the forerunner node pointer of unit 606 through decision node 1 whether and last time pointer equate to judge whether chained list makes mistakes; If forerunner's node pointer of decision node 1 and last time pointer equate that last time pointer modified is for pointing to node 1 for this, this current pointer is revised and is pointed to node 2.When this application program continues the subsequent node of this doubly linked list of visit through FPGA, its operating process and above-mentioned to node 0 or node 1 class of operation seemingly, do not giving unnecessary details at this.Preferably, when the doubly linked list initialization, initialization unit 602 can be with the first node of this doubly linked list of forerunner's node pointer initial directional of the first node of doubly linked list, the first node of the said doubly linked list of said last time pointer initial directional.As shown in Figure 5, forerunner's node pointer of doubly linked list node 0 can initialization point to node 0, and node 0 is pointed in the current pointer initialization; Last time node 0 was pointed in the pointer initialization, realized that like this advantage is, had improved the accuracy in detection to the first node of this doubly linked list; When node 0 was detected, forerunner's node pointer value of last time pointer that compares and current pointer all was the address of node 0, rather than null value; In the operation of internal memory, the content initialization of internal memory all is to be set to null value usually, like this; When outer memory controller is made mistakes, through current pointer visit possibly not be node 0, and have access to another internal memory; And the content of this memory address all is a null value just, then can't judge the chained list access errors.And the address of node 0 is unique in the memory externally; The probability that occurs the value identical with this address in other core positions is very little; Therefore, through forerunner's node pointer of the first node of doubly linked list and last time the first node of pointer initial directional doubly linked list can improve accuracy in detection to the first node of this doubly linked list.
The method benefit of the chained list error detection that the embodiment of the invention provides is; When each FPGA visits the doubly linked list of external memory through logic controller; There is individual expected results in the capital, and this expected results judges through pointer last time, if last time pointer was unequal for forerunner's node pointer of the node of the doubly linked list of the external memory storage that obtains through logic controller and this; Think that then obtaining chained list node does not satisfy expected results, therefore can judge this doubly linked list mistake.Can solve like this because the problem of the chained list access errors that the external memory controller error of FPGA causes; For instance; If like Fig. 3 application program during, during this doubly linked list of external memory controller access through FPGA of the current pointer that utilizes logic controller, if the outer memory controller of FPGA is made mistakes through this doubly linked list of FPGA visit; Cause to visit the node 1 of this doubly linked list; But wrong visit the node n of this doubly linked list because forerunner's node pointer of node n is that last time the address of pointed node 0 was unequal with this address of node n-1, can judge then that this doubly linked list is visited to make mistakes.Simultaneously; The technical scheme that the embodiment of the invention provides is for because the read-write of wrong BIT position saltus step or application program appears in external memory storage crosses the border and cause chained list node forerunner node pointer suitable equally by the chained list access errors that rewriting causes, for instance, as shown in Figure 3; Wrong bit saltus step appears if external memory storage is deposited the corresponding position of forerunner's node pointer of node 1; This forerunner's node pointer becomes illegal pointer, so when application program during through this doubly linked list of FPGA visit, when utilizing the current pointer of logic controller to obtain the node 1 of this doubly linked list; Because forerunner's node pointer of node 1 has become illegal pointer; Last time pointer will be unequal with forerunner's node pointer of node 1 for this, therefore, can judge this doubly linked list access errors.
This device can also comprise processing unit 702, be used for when forerunner's node pointer of this node with this last time pointer equate, with this last time pointer make amendment, the value of amended last time pointer is the value of this current pointer.Revise current pointer then, the value of amended current pointer is the value of the descendant node pointer of this node.As shown in Figure 4, Fig. 4 is forerunner's node pointer of confirming this node when last time pointer equated with this, the sketch map after this current pointer and the pointer modified last time, and last time pointer modified is a sensing node 0, current pointer is revised as sensing node 1.
Further, this device can also comprise notification unit 802, and is as shown in Figure 8.
The device that the embodiment of the invention provides can be realized that the network equipment can be router or switch by the network equipment or Programmable Logic Controller, and Programmable Logic Controller can be FPGA or ASIC.
It is thus clear that; Implement the device provide through the present invention; When application program is visited doubly linked list through programming device; Can carry out real-time error detection to the visit of doubly linked list, when the chain table access makes mistakes, report webmaster and stop application program, can effectively solve the chain table access and make mistakes and cause the problem of system crash the chain table access.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be accomplished through the relevant hardware of program command; Aforementioned program can be stored in the computer read/write memory medium; This program the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
What should explain at last is: above embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although with reference to previous embodiment the present invention has been carried out detailed explanation, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (10)
1. the method for doubly linked list visit error detection; It is characterized in that; In logic controller, deposit the current pointer of said doubly linked list and pointer last time, said current pointer is used to identify the said doubly linked list node of this less important visit, and said last time pointer is used to identify the last time said doubly linked list node of visit; The first node of the said doubly linked list of said current pointer initial directional, said method comprises:
Obtain the node of said doubly linked list according to said current pointer;
Forerunner's node pointer of the node of the said doubly linked list that obtains and said last time when pointer is unequal confirms that said doubly linked list visit makes mistakes.
2. method according to claim 1 is characterized in that, this method further comprises:
The first node of the said doubly linked list of forerunner's node pointer initial directional of the first node of said doubly linked list, the first node of the said doubly linked list of said last time pointer initial directional.
3. method according to claim 1 is characterized in that, this method further comprises:
Forerunner's node pointer of the first node of said doubly linked list is initially null value, and said last time pointer is initially null value.
4. according to the arbitrary described method of claim 1 to 3, it is characterized in that this method further comprises:
Forerunner's node pointer of the node of the doubly linked list of said acquisition is with said last time when pointer equates; Said last time pointer content is made amendment; The value of amended said last time pointer is the value of said current pointer; And said current pointer made amendment, the value of amended said current pointer is the value of descendant node pointer of node of the doubly linked list of said acquisition.
5. according to each described method of claim 1 to 4, it is characterized in that, after said doubly linked list visit makes mistakes, further comprise:
The said doubly linked list visit of notice webmaster makes mistakes, and stops the visit to said doubly linked list.
6. the device of a doubly linked list visit error detection is characterized in that, comprising:
Initialization unit; Be used for when doubly linked list generates; In logic controller, deposit the current pointer of said doubly linked list and pointer last time; Said current pointer is used to identify the said doubly linked list node of this less important visit, and said last time pointer is used to identify the last time said doubly linked list node of visit, the first node of the said doubly linked list of said current pointer initial directional;
Acquiring unit is used for obtaining according to said current pointer the node of said doubly linked list;
Confirm the unit, be used for forerunner's node pointer of node of the said doubly linked list that obtains and said last time when pointer is unequal, confirm that said doubly linked list visit makes mistakes.
7. device according to claim 6 is characterized in that, further comprises:
Said initialization unit is provided with the first node of the said doubly linked list of forerunner's node pointer initial directional of the first node of said doubly linked list, the first node of the said doubly linked list of said last time pointer initial directional.
8. device according to claim 6 is characterized in that, further comprises:
Forerunner's node pointer that said initialization unit is provided with the first node of said doubly linked list is initially null value, and said last time pointer is initially null value.
9. according to the described device of the arbitrary claim of claim 6 to 8, it is characterized in that, comprising:
Processing unit; Be used for when forerunner's node pointer of the node of the doubly linked list of said acquisition with said last time when pointer equates; Said last time pointer content is made amendment; The value of amended said last time pointer is the value of said current pointer, and said current pointer is made amendment, and the value of amended said current pointer is the value of descendant node pointer of node of the doubly linked list of said acquisition.
10. according to the described device of the arbitrary claim of claim 6 to 9, it is characterized in that, comprising:
Notification unit is used for after the said doubly linked list visit of said judgment unit judges makes mistakes, and the said doubly linked list visit of notice webmaster makes mistakes, and stops the visit to said doubly linked list.
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| CN103713962B (en) * | 2012-10-09 | 2017-07-18 | 南京中兴软件有限责任公司 | One kind detection data link table method and electronic equipment |
| CN103279398A (en) * | 2013-05-31 | 2013-09-04 | 华为技术有限公司 | Linked list dequeuing troubleshooting method and linked list dequeuing troubleshooting device |
| CN103279398B (en) * | 2013-05-31 | 2016-11-16 | 华为技术有限公司 | Chained list goes out group malfunction elimination method and relevant apparatus |
| CN107665409A (en) * | 2017-11-01 | 2018-02-06 | 飞友科技有限公司 | A kind of front and rear sequence flight structure and fault-tolerant method |
| CN107665409B (en) * | 2017-11-01 | 2021-02-26 | 飞友科技有限公司 | Method for constructing and fault-tolerant front-and-back flight |
| CN115794838A (en) * | 2023-02-07 | 2023-03-14 | 深圳开源互联网安全技术有限公司 | Method and device for storing bidirectional linked list, terminal equipment and storage medium |
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Application publication date: 20120704 |