CN102545680A - Field programmable gate array (FPGA)-driving-based cascaded multilevel converter - Google Patents
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Abstract
The invention discloses a field programmable gate array (FPGA)-driving-generation-based cascaded multilevel converter, which comprises a frequency conversion controller and an FPGA connected with the frequency conversion controller. The FPGA comprises a bus interface module, a frequency division module, a sinusoidal wave generation module, a carrier generation module and a driving signal generation module. A phase shift carrier sinusoidal pulse width modulation (SPWM) technology is adopted, and N carriers are compared with a three-phase modulated wave respectively, so that N bi-level three-phase SPWM signals are obtained. The characteristics of the FPGA are fully utilized, and a data storage circuit, an address generation circuit, a control circuit and the like which are required by the generation of the SPWM signals are all integrated into a chip, so that a frequency conversion system has a high integration level, low cost and high reliability, and comprises a few parts; and a device resource utilization rate is high, switching frequency is reduced, a sideband harmonic order is increased, and the frequency conversion system is low in switching loss and low in harmonic content.
Description
Technical field
The invention belongs to the frequency conversion control technique field, be specifically related to a kind of cascading multiple electrical level frequency converter that takes place that drives based on FPGA (field programmable gate array).
Background technology
The application of alternating frequency conversion technique in middle high-power speed-adjusting device become one of focus of domestic and international Alternating Current Governor System.There are following problems in traditional two level converters in high-power is used: (1) switching frequency is high, and switching loss is big; (2) required transformer price is high, volume is big, energy consumption is high; (3) adopt the device series connection, need complicated dynamic voltage-balancing etc.The multi-level frequency conversion device adopts novel circuit topological structure, when having reduced output transformer and dynamic voltage-balancing, only needs lower switching frequency just can obtain high-quality output waveform, has improved the frequency conversion system operational efficiency.
The circuit topology of present multi-level frequency conversion device inversion part is the most commonly used with the cascade connection type inverter circuit with independent DC power supply.Every grade of unit is made up of the independent full-bridge circuit of supplying power of No. one DC power supply in the sort circuit.Export two level (0,1) logic like each unit, then the frequency converter of three-phase N level N+1 level needs 3*N road SPWM (Sinusoidal PWM) signal.Export three level (0,1 ,-1) logic like each unit, then the frequency converter of three-phase N level 2*N+1 level needs 6*N road SPWM signal.Therefore, the generation of multichannel independence SPWM signal is the necessary condition that the cascading multiple electrical level frequency converter is realized.In practical application, as powerful, the dsp chip TMS320C2812 that is suitable for Electric Machine Control at most also can only provide 12 tunnel pulses; Therefore the limited independent SPWM signal limitations of number the level number of multi-level frequency conversion device, also limited the lifting of frequency converter performance.
Summary of the invention
To the above-mentioned technological deficiency of existing in prior technology, the invention provides a kind of cascading multiple electrical level frequency converter that driving takes place based on FPGA, can produce multichannel SPWM drive signal, circuit structure is simple, compact.
A kind of cascading multiple electrical level frequency converter that driving takes place based on FPGA comprises frequency-variable controller, and described frequency-variable controller is connected with FPGA;
Described FPGA comprises bus interface module, frequency division module, sinusoidal wave generating module, carrier wave generating module and drive signal generating module; Wherein: bus interface module links to each other with sinusoidal wave generating module with frequency-variable controller, and frequency division module links to each other with the carrier wave generating module with sinusoidal wave generating module, and the drive signal generating module links to each other with the carrier wave generating module with sinusoidal wave generating module.
Described bus interface module is used to receive the control information that frequency-variable controller provides, and is transmitted to sinusoidal wave generating module to control information.
Described frequency division module is used to receive given high frequency clock, and high frequency clock is carried out frequency division handle the back provides low frequency to sinusoidal wave generating module and carrier wave generating module clock information; Frequency division module is a frequency divider.
Described sinusoidal wave generating module is used for according to described control information and clock information, produces the three-phase sine-wave signal; Described sinusoidal wave generating module comprises a gate-controlled switch, an address register, a memory, a multiplier and two adders; Wherein: the input of first gate-controlled switch links to each other with frequency division module, and control end receives given enable signal, and output links to each other with the control end of address register and the control end of first memory; The input of first adder links to each other with bus interface module, and output links to each other with the input of address register; The output of address register links to each other with the addend end of first adder and the addend end of second adder; Three inputs of second adder receive three groups of given phase control words respectively, and three outputs link to each other with three inputs of first memory respectively; Three outputs of first memory link to each other with three inputs of multiplier respectively; The multiplier end of multiplier links to each other with bus interface module, and three outputs link to each other with the drive signal generating module.
Described carrier wave generating module is used for according to described clock information, produces N road triangular carrier signal, and N is the progression of multi-level frequency conversion device; Described carrier wave generating module comprises a gate-controlled switch, a counter, an adder and a memory; Wherein: the input of second gate-controlled switch links to each other with frequency division module, and control end receives given enable signal, and output links to each other with the control end of counter and the control end of second memory; The N of the 3rd an adder input receives given N group phase control words respectively, and the addend end links to each other with the output of counter, and N output links to each other with N input of second memory respectively; The N of a second memory output links to each other with the drive signal generating module.
Store sine waveform and triangular carrier waveform in described first memory and the second memory respectively.
Described drive signal generating module is used for described three-phase sine-wave signal and N road triangular carrier signal are compared, and produces the drive signal of N to complementation; Described drive signal generating module is by 3N signal cell array of N * 3 formed of synthesis unit relatively; The described signal relatively first input end of synthesis unit links to each other with sinusoidal wave generating module; Second input links to each other with the carrier wave generating module, and two outputs are exported the drive signal of a pair of complementation.
Described signal comparison synthesis unit comprises a comparator, a delayer, one and a door and a NOR gate; Wherein: two inputs of comparator are respectively relatively two inputs of synthesis unit of signal, the input of output and delayer, link to each other with the first input end of door and the first input end of NOR gate; The output of delayer with link to each other with second input of door and second input of NOR gate; Be respectively relatively two outputs of synthesis unit of signal with the output of door and the output of NOR gate.
Beneficial effect of the present invention is:
(1) the present invention's high speed performance of utilizing FPGA and itself integrated up to ten thousand logics and embedded memory device; The SPWM signal required storage takes place, the address takes place and control circuit etc. is all integrated advances in the chip piece, makes that the frequency conversion system integrated level is high, number of components is few, cost is low, reliability is high; And the FPGA operating frequency is high, and general purpose I/O aboundresources can satisfy the system real time requirement, but each road signal parallel processing and being independent of each other.
(2) the present invention adopts phase shift carrier wave SPWM technology, has reduced switching frequency, has improved sideband harmonic wave order, makes that the frequency conversion system switching loss is lower, and harmonic content still less.
(3) the present invention adopts relatively composite structure of matrix form signal, and the device resource utilance is high, has improved the operating efficiency of FPGA, has alleviated the burden of control system, and then realizes also being suitable for the output of multichannel SPWM drive signal for the frequency converter that surpasses five level.
(4) because FPGA realizes logical reconstruction easily,, simplified the exploitation and the escalation process of system so the present invention is easy to in-system programming and numerous powerful eda software supports are arranged.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2 is the structural representation of sinusoidal wave generating module.
Fig. 3 is the structural representation of carrier wave generating module.
Fig. 4 is the structural representation of drive signal generating module.
Fig. 5 compares the structural representation of synthesis unit for signal.
Embodiment
In order to describe the present invention more particularly, technical scheme of the present invention and relative theory thereof are elaborated below in conjunction with accompanying drawing and embodiment.
As shown in Figure 1, a kind of cascading multiple electrical level frequency converter that drives generation based on FPGA comprises frequency-variable controller and the FPGA that links to each other with frequency-variable controller; In the present embodiment, it is the chip of EP3SL150 that FPGA adopts the Stratix III of altera corp serial model No., and it is the MCU chip of STM32F103 that frequency-variable controller adopts ST company model.
FPGA comprises bus interface module, frequency division module, sinusoidal wave generating module, carrier wave generating module and drive signal generating module; Wherein:
Bus interface module is used to receive the control information that frequency-variable controller provides, and is transmitted to sinusoidal wave generating module to control information; It links to each other with sinusoidal wave generating module with frequency-variable controller.
Frequency division module is used to receive given high frequency clock, and high frequency clock is carried out frequency division handle the back provides low frequency to sinusoidal wave generating module and carrier wave generating module clock information; It links to each other with the carrier wave generating module with sinusoidal wave generating module; In the present embodiment, frequency division module is a frequency divider.
Sinusoidal wave generating module is used for according to control information and clock information, produces the three-phase sine-wave signal; It links to each other with the drive signal generating module; As shown in Figure 2, sinusoidal wave generating module comprises a gate-controlled switch, an address register, a memory, a multiplier and two adders; Wherein: the input of first gate-controlled switch links to each other with frequency division module and receives low-frequency clock CLK, and control end receives given enable signal, and output links to each other with the control end of address register and the control end of first memory; The input of first adder J1 links to each other with bus interface module and the receive frequency control information, and output links to each other with the input of address register; The output of address register links to each other with the addend end of first adder J1 and the addend end of second adder J2; Three inputs of second adder J2 receive three groups of given phase control words respectively, and three outputs link to each other with three inputs of first memory respectively; Three outputs of first memory link to each other with three inputs of multiplier respectively; The multiplier end of multiplier links to each other with bus interface module and receives the amplitude control information, and three outputs link to each other with the drive signal generating module and export three-phase sine-wave signal (SineA, SineB, SineC); Store sine waveform in the first memory respectively.
Sinusoidal wave generating module adopts direct frequency synthesis (DDS) technology, realizes the sinusoidal modulation signal output of three-phase SPWM, one-period the sinusoidal waveform data be that the address is stored in the first memory in advance with the phase place; Address register is according to frequency control word rolling OPADD sign indicating number, and the three-phase phase sign indicating number is obtained by address code and the summation of three-phase phase control word; Read Wave data according to corresponding units in the three-phase phase sign indicating number visit first memory, and regulate back output according to the amplitude control word through multiplier.
The carrier wave generating module is used for according to clock information, produces N road triangular carrier signal; It links to each other with the drive signal generating module, and N is the progression of multi-level frequency conversion device; As shown in Figure 3, the carrier wave generating module comprises a gate-controlled switch, a counter, an adder and a memory; Wherein: the input of second gate-controlled switch links to each other with frequency division module and receives low-frequency clock CLK, and control end receives given enable signal, and output links to each other with the control end of counter and the control end of second memory; The N of the 3rd an adder J3 input receives given N group phase control words respectively, and the addend end links to each other with the output of counter, and N output links to each other with N input of second memory respectively; The N of a second memory output links to each other with the drive signal generating module and exports N road triangular carrier signal (Carrier1, Carrier2 ... CarrierN); Store the triangular carrier waveform in the second memory respectively.
The carrier wave generating module reads Wave data output through the effect of N different phase control word from second memory, form N the evenly triangular carrier of phase shift.
The drive signal generating module is used for three-phase sine-wave signal and N road triangular carrier signal are compared, and produces the drive signal of N to complementation; It links to each other with external drive circuit; As shown in Figure 4; The drive signal generating module is by 3N signal cell array of N * 3 formed of synthesis unit D relatively; The arbitrary signal that i is capable in the cell array relatively first input end of synthesis unit links to each other with sinusoidal wave generating module and receives corresponding one sine wave signal mutually; Second input links to each other with the carrier wave generating module and receives i triangular carrier signal, and two outputs link to each other with external drive circuit and export the drive signal of a pair of complementation.
The drive signal generating module is carried out numeric ratio with the three phase sine modulating wave with N phase shift triangular carrier respectively through matrix-style, and 3N comparative result is through the two-valued function form output of dead band control with complementation.
As shown in Figure 5, signal comparison synthesis unit comprises a comparator, a delayer, one and a door and a NOR gate; Wherein: two inputs of comparator are respectively two inputs of signal comparison synthesis unit and receive sine wave signal and the triangular carrier signal, the input of output and delayer, link to each other with the first input end of door and the first input end of NOR gate; The output of delayer with link to each other with second input of door and second input of NOR gate; Be respectively two outputs of signal comparison synthesis unit and export the drive signal of a pair of complementation with the output of door and the output of NOR gate.
Triangular carrier and sinusoidal modulation wave signal comparative result through time-delay after again with former comparison signal carry out with the NOR-logic computing; Two operation results are the part of the upper and lower brachium pontis drive signal of band dead band control; Be exactly Dead Time time of delay, generally depends on the turn-off time of power switch pipe.
Claims (5)
1. a cascading multiple electrical level frequency converter that drives generation based on FPGA comprises frequency-variable controller; It is characterized in that: described frequency-variable controller is connected with FPGA;
Described FPGA comprises bus interface module, frequency division module, sinusoidal wave generating module, carrier wave generating module and drive signal generating module; Wherein: bus interface module links to each other with sinusoidal wave generating module with frequency-variable controller, and frequency division module links to each other with the carrier wave generating module with sinusoidal wave generating module, and the drive signal generating module links to each other with the carrier wave generating module with sinusoidal wave generating module.
2. the cascading multiple electrical level frequency converter that driving takes place based on FPGA according to claim 1, it is characterized in that: described sinusoidal wave generating module comprises a gate-controlled switch, an address register, a memory, a multiplier and two adders; Wherein: the input of first gate-controlled switch links to each other with frequency division module, and control end receives given enable signal, and output links to each other with the control end of address register and the control end of first memory; The input of first adder links to each other with bus interface module, and output links to each other with the input of address register; The output of address register links to each other with the addend end of first adder and the addend end of second adder; Three inputs of second adder receive three groups of given phase control words respectively, and three outputs link to each other with three inputs of first memory respectively; Three outputs of first memory link to each other with three inputs of multiplier respectively; The multiplier end of multiplier links to each other with bus interface module, and three outputs link to each other with the drive signal generating module.
3. the cascading multiple electrical level frequency converter that driving takes place based on FPGA according to claim 1, it is characterized in that: described carrier wave generating module comprises a gate-controlled switch, a counter, an adder and a memory; Wherein: the input of second gate-controlled switch links to each other with frequency division module, and control end receives given enable signal, and output links to each other with the control end of counter and the control end of second memory; The N of the 3rd an adder input receives given N group phase control words respectively, and the addend end links to each other with the output of counter, and N output links to each other with N input of second memory respectively; The N of a second memory output links to each other with the drive signal generating module; N is the progression of multi-level frequency conversion device.
4. the cascading multiple electrical level frequency converter that takes place that drives based on FPGA according to claim 1; It is characterized in that: described drive signal generating module is the cell array of N * 3 be made up of 3N signal comparison synthesis unit; The described signal relatively first input end of synthesis unit links to each other with sinusoidal wave generating module; Second input links to each other with the carrier wave generating module, and two outputs are exported the drive signal of a pair of complementation; N is the progression of multi-level frequency conversion device.
5. the cascading multiple electrical level frequency converter that drive to take place based on FPGA according to claim 4 is characterized in that: described signal comparison synthesis unit comprise a comparator, a delayer, one with and a NOR gate; Wherein: two inputs of comparator are respectively relatively two inputs of synthesis unit of signal, the input of output and delayer, link to each other with the first input end of door and the first input end of NOR gate; The output of delayer with link to each other with second input of door and second input of NOR gate; Be respectively relatively two outputs of synthesis unit of signal with the output of door and the output of NOR gate.
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| CN103219971A (en) * | 2013-04-19 | 2013-07-24 | 上海大学 | Sinusoidal pulse width modulation (SPWM) impulse wave production system based on modulating wave period normalization |
| CN103457584A (en) * | 2013-09-05 | 2013-12-18 | 上海大学 | Sinusoidal pulse width modulation normalization address generator |
| CN107357197A (en) * | 2017-06-20 | 2017-11-17 | 上海交通大学 | A kind of system and method that servo corner simple harmonic motion is realized based on FPGA |
| CN107403030A (en) * | 2017-06-15 | 2017-11-28 | 上海交通大学 | A kind of method that the superposition simple harmonic motion of servo corner is realized based on FPGA |
| US10218285B2 (en) | 2015-10-19 | 2019-02-26 | Siemens Aktiengesellschaft | Medium voltage hybrid multilevel converter and method for controlling a medium voltage hybrid multilevel converter |
| CN109490839A (en) * | 2018-10-29 | 2019-03-19 | 北京遥感设备研究所 | A kind of temperature feedback phase-correcting circuit and method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219971A (en) * | 2013-04-19 | 2013-07-24 | 上海大学 | Sinusoidal pulse width modulation (SPWM) impulse wave production system based on modulating wave period normalization |
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| US10218285B2 (en) | 2015-10-19 | 2019-02-26 | Siemens Aktiengesellschaft | Medium voltage hybrid multilevel converter and method for controlling a medium voltage hybrid multilevel converter |
| CN107403030A (en) * | 2017-06-15 | 2017-11-28 | 上海交通大学 | A kind of method that the superposition simple harmonic motion of servo corner is realized based on FPGA |
| CN107357197A (en) * | 2017-06-20 | 2017-11-17 | 上海交通大学 | A kind of system and method that servo corner simple harmonic motion is realized based on FPGA |
| CN107357197B (en) * | 2017-06-20 | 2020-05-08 | 上海交通大学 | System and method for realizing servo corner simple harmonic motion based on FPGA |
| CN109490839A (en) * | 2018-10-29 | 2019-03-19 | 北京遥感设备研究所 | A kind of temperature feedback phase-correcting circuit and method |
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