CN102543760B - Method for increasing shallow trench isolating compressive stress and improving NMOS electron mobility - Google Patents
Method for increasing shallow trench isolating compressive stress and improving NMOS electron mobility Download PDFInfo
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- CN102543760B CN102543760B CN201210047378.8A CN201210047378A CN102543760B CN 102543760 B CN102543760 B CN 102543760B CN 201210047378 A CN201210047378 A CN 201210047378A CN 102543760 B CN102543760 B CN 102543760B
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Abstract
The invention discloses a method for increasing shallow trench isolating compressive stress and improving NMOS (N-Mental-Oxide-Semiconductor) electron mobility. The method comprises the following steps: an oxide layer and a first silicon nitride layer are sequentially formed on a substrate; photoresist is spirally coated on the first silicon nitride layer to achieve photoetching of the first silicon nitride layer, the oxide layer and the substrate to form shallow trenches, and after that, the photoresist is removed; second nitride layers grow on the surfaces of the shallow trenches; the shallow trenches are subject to quick thermal annealing technology; the second silicon nitride layer is etched, and the photoresist is removed; mat oxidizing layers grow on the surfaces of the shallow trenches; third silicon nitride layers grows on the surfaces of the mat oxidizing layers; an insulating medium is filled in each shallow trench, and meanwhile, the insulating medium covers the surface of the substrate; and the shallow trenches are subject to high-temperature annealing technology. Compressive stress is led into the STI (Shallow Trench Isolate) technology, transmitted to device channels and then converted into tensile stress in the channels, so as to improve the electron mobility in the NMOS (N-Mental-Oxide-Semiconductor) devices, and promote the performance of the NMOS devices.
Description
Technical field
The present invention relates generally to ic manufacturing technology field, or rather, the present invention relates to a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility.
Background technology
Along with integrated circuit characteristic line breadth narrows down to below 90nm, can not meet the requirement of technique by gate, gate dielectric constant and junction depth raising device performance, even if gate is controlled at 5 atomic layers, and junction depth also only has 10nm.Comply with the requirement of switching speed, heavily stressed silicon nitride technology is studied widely, follows heavily stressed that silicon nitride applies in grid mechanism, and the carrier mobility of MOS device can be greatly improved.Particularly, the structural compression of PMOS can improve the mobility in hole, and the structural tensile stress of NMOS can improve the mobility of electronics.
STI(shallow trench isolate) technique, i.e. shallow trench isolation technology, utilizes this technology to isolate active area device in integrated circuit, eliminates parasitic brilliant pipe thereby reach, and reduces electric capacity and suppresses latch-up texts.
In STI technique, typical cmos device STI manufacture craft is the silicon dioxide pad oxide of first growing after etching groove completes, and then uses silica-filled groove, then with the oxygen atmosphere densification of annealing.In annealing densification process, oxygen can diffuse into pad oxide, increases the compression of STI to device channel with pasc reaction, and the carrier mobility of device is impacted.
Summary of the invention
For the problem of above-mentioned existence, the object of the present invention is to provide a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility, by improving STI manufacture craft, in STI, introduce internal compressive stress, and make this compression be transmitted to the tension stress that is converted to raceway groove in device channel, thereby electron mobility in raising nmos device, improves nmos device performance, is specifically achieved through the following technical solutions:
Increase the method that shallow trench isolation tripping stress improves NMOS electron mobility, comprising: on substrate, form successively oxide skin(coating) and the first nitride layer; Spin coating photoresist on described the first nitride layer, carries out photoetching to described the first nitride layer, described oxide layer and described substrate, forms shallow trench, and removes photoresist; Wherein, further comprising the steps of:
Step 1: at superficial growth one deck second nitride layer of described shallow trench;
Step 2: described shallow trench is carried out to rapid thermal anneal process;
Step 3: the second silicon nitride layer described in etching, remove photoresist;
Step 4: at described shallow trench superficial growth one deck pad oxide;
Step 5: at described pad oxide superficial growth one deck the 3rd nitride layer;
Step 6: fill dielectric in described shallow trench, meanwhile, described dielectric covers described substrate surface;
Step 7: described shallow trench is carried out to high-temperature annealing process;
A kind of above-mentioned method that increases shallow trench isolation tripping stress raising NMOS electron mobility, wherein, described the first nitride, the second nitride and described the second nitride are silicon nitrides.
A kind of above-mentioned method that increases shallow trench isolation tripping stress raising NMOS electron mobility, wherein, described dielectric is silicon dioxide.
A kind of above-mentioned method that increases shallow trench isolation tripping stress raising NMOS electron mobility wherein, is to carry out in pure nitrogen gas atmosphere chamber at high-temperature annealing process.
A kind of above-mentioned method that increases shallow trench isolation tripping stress raising NMOS electron mobility, wherein, described pad oxide is silica.
A kind of above-mentioned method that increases shallow trench isolation tripping stress raising NMOS electron mobility, wherein, adopts high density plasma CVD method at described shallow trench and described substrate surface deposit megohmite insulant.
A kind of above-mentioned method that increases shallow trench isolation tripping stress and improve NMOS electron mobility, wherein, can adopt high vertical wide than technique megohmite insulant in described groove and described in institute's substrate surface deposit.
A kind of above-mentioned method that increases shallow trench isolation tripping stress raising NMOS electron mobility, wherein, adopts high density plasma CVD method at pad oxide described in described shallow trench superficial growth one deck.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after accompanying drawing, the advantage of these and other aspects of the present invention undoubtedly will be apparent.
The present invention increases step---and the silicon nitride that is compression in flute surfaces deposit one deck inside also carries out rapid thermal treatment annealing, has strengthened the tension stress of semiconductor device channel; In addition, in the present invention, be also included in growth pad oxide after again at pad oxide superficial growth one deck silicon nitride, then by silicon nitride surface growth pad oxide with fill dielectric and carry out high-temperature annealing process, further strengthen the tension stress of semiconductor device channel, thereby strengthened the electron mobility of nmos device.
Finally, carrying out in high-temperature annealing process, adopt the annealing of pure nitrogen gas atmosphere, can stop in STI annealing process gas inwardly diffusion react and cause the tensile stress of STI inside.
Brief description of the drawings
Figure 1A-Fig. 1 E is the flowage structure schematic diagram of a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility of the present invention.
Embodiment
With reference to appended accompanying drawing, to describe more fully embodiments of the invention, but appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
The most preferred embodiment main process of a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility of the present invention is:
Step S1: deposit successively from lower to upper one deck oxide skin(coating) 2 and one deck the first silicon nitride layer 3 on 1 on substrate, and spin coating one deck photoresist on the first silicon nitride layer 3, successively the first silicon nitride layer 3, oxide layer 2 and substrate 1 are carried out to photoetching, form shallow trench 4, and remove photoresist.
In this step, can select Cl
2, HBr and O
2gas, as etching gas, in etching process, is conducive to the control of the shape to shallow trench 4 more.
Step S2: in reaction chamber, be the second silicon nitride layer 5 of compression in sidewall and lower surface deposit one deck inside of shallow trench 4.
Step S3: the temperature of reaction chamber is risen to certain hot environment, shallow trench 4 is carried out to rta technique, now, to active area, this stress is transmitted to the tension stress that is converted to raceway groove in device channel by stress transfer.
Step S4: at the surperficial spin coating one deck of the second silicon nitride layer 5 photoresist, etching the second silicon nitride layer 5, to removing when the second silicon nitride layer 5, stops etching, and photoresist is removed in ashing;
Step S5: utilize thermal oxidation at shallow trench 4 superficial growth one deck pad oxides 6, wherein, this pad oxide 6 in the surface deposition growth of shallow trench 4 can be silicon dioxide pad oxide or silicon oxide pad oxide layer, thereby can strengthen the adhesive force between dielectric and substrate in groove.
Step S6: be the 3rd silicon nitride layer 7 of compression in pad oxide long one deck of 6 surface regeneration inside.
Step S7: fill dielectric 8 in shallow trench 4, meanwhile, dielectric 8 covers substrate 1 surface.
In this step, can adopt high density plasma CVD method (HDPCVD), with the high-density plasma source of the forms such as electron cyclotron resonace ECR, induction coupled plasma ICP, taking gases such as silane, oxygen and argon gas as reacting gas source, at the surface deposition silicon dioxide of substrate 1 and shallow trench 4.Can also adopt high vertical wide than technique (HARP) at the surface deposition silicon dioxide at substrate 1 and shallow trench 4.
Step 7: shallow trench 4 is carried out to high-temperature annealing process, and now, the compression of the 3rd silicon nitride layer 7 is also transmitted in the raceway groove of semiconductor device, is converted into the tension stress in raceway groove.Wherein, this annealing process can adopt in the processing chamber of oxygen atmosphere and carry out, and preferably, is chosen in the reaction chamber of pure nitrogen gas atmosphere and carries out high-temperature annealing process, can further reduce the STI tensile stress that has oxygen annealing to cause.
By explanation and accompanying drawing, provide the exemplary embodiments of the ad hoc structure of embodiment, therefore, although foregoing invention has proposed existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as, and within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (7)
1. increase the method that shallow trench isolation tripping stress improves NMOS electron mobility, comprising: on substrate, form successively oxide skin(coating) and the first nitride layer; Spin coating photoresist on described the first nitride layer, carries out photoetching to described the first nitride layer, described oxide layer and described substrate, forms shallow trench, and removes photoresist; It is characterized in that, further comprising the steps of:
Step 1: at superficial growth one deck second nitride layer of described shallow trench;
Step 2: described shallow trench is carried out to rapid thermal anneal process;
Step 3: the second nitride layer described in etching, remove photoresist;
Step 4: at described shallow trench superficial growth one deck pad oxide;
Step 5: at described pad oxide superficial growth one deck the 3rd nitride layer;
Step 6: fill dielectric in described shallow trench, meanwhile, described dielectric covers described substrate surface;
Step 7: described shallow trench is carried out to high-temperature annealing process.
2. a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility according to claim 1, is characterized in that, described the first nitride, the second nitride and described the 3rd nitride are silicon nitrides.
3. a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility according to claim 1, is characterized in that, described dielectric is silicon dioxide.
4. according to a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility described in claim 1 or 3, it is characterized in that employing high density plasma CVD method dielectric in described shallow trench and described in described substrate surface deposit.
5. a kind of method that increases shallow trench isolation tripping stress and improve NMOS electron mobility according to described in claim 1 or 3, is characterized in that, can adopt high vertical wide than technique megohmite insulant in described groove and described in institute's substrate surface deposit.
6. a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility according to claim 1, is characterized in that, is to carry out in pure nitrogen gas atmosphere chamber at high-temperature annealing process.
7. a kind of method that increases shallow trench isolation tripping stress raising NMOS electron mobility according to claim 1, is characterized in that, described pad oxide is silica.
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| KR100319620B1 (en) * | 1999-05-10 | 2002-01-05 | 김영환 | Isolation structure for semiconductor device and fabricating method thereof |
| KR100338767B1 (en) * | 1999-10-12 | 2002-05-30 | 윤종용 | Trench Isolation structure and semiconductor device having the same, trench isolation method |
| US20030129839A1 (en) * | 2002-01-04 | 2003-07-10 | Shyh-Dar Lee | Method of forming a liner in shallow trench isolation |
| KR100571405B1 (en) * | 2003-12-24 | 2006-04-14 | 동부아남반도체 주식회사 | Device Separator Formation Method of Semiconductor Device |
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