CN102543749A - Method for manufacturing power semiconductor assembly with super interface - Google Patents
Method for manufacturing power semiconductor assembly with super interface Download PDFInfo
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- CN102543749A CN102543749A CN2011100306028A CN201110030602A CN102543749A CN 102543749 A CN102543749 A CN 102543749A CN 2011100306028 A CN2011100306028 A CN 2011100306028A CN 201110030602 A CN201110030602 A CN 201110030602A CN 102543749 A CN102543749 A CN 102543749A
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
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Abstract
The invention discloses a method for manufacturing a power semiconductor component with a super interface, which comprises the following steps: providing a substrate with a first conductive type; forming at least one grid structure and at least one mask layer arranged on the grid structure on the substrate; forming a gap wall on the side walls of the grid structure and the mask layer, and exposing a part of the substrate; removing part of the exposed substrate to form at least one trench; filling a dopant source layer in the trench, wherein the dopant source layer comprises a plurality of dopants having a second conductivity type; and performing a thermal drive-in process to diffuse the dopant into the substrate to form a body doped region having the second conductivity type. Therefore, a smooth super interface can be formed without being influenced by the flatness of the side wall of the groove, and the voltage-resisting capacity of the power semiconductor component is effectively improved.
Description
Technical field
The present invention relates to a kind of method of making power semiconductor assembly, be specifically related to the method that a kind of making has the power semiconductor assembly of ultra interface.
Background technology
In the power transistor assembly, the size of conducting resistance RDS (on) is directly proportional with the power consumption of assembly between drain electrode and source electrode, therefore reduces the power that the big I minimizing power transistor assembly of conducting resistance RDS (on) is consumed.In conducting resistance RDS (on), be used for the shared ratio of the withstand voltage resistance value that epitaxial loayer caused for the highest.Though the doping content of conductive materials can reduce the resistance value of epitaxial loayer in the increase epitaxial loayer, acting as of epitaxial loayer is used to bear high voltage.If increase the breakdown voltage that doping content can reduce epitaxial loayer, thereby reduce the voltage endurance capability of power transistor assembly.Therefore develop and a kind of power transistor assembly, to have high voltage endurance capability and low on-resistance concurrently with ultra interface (super junction).
Please refer to Fig. 1 to Fig. 6, Fig. 1 to Fig. 6 has illustrated and has made known method sketch map with power transistor assembly of ultra interface.As shown in Figure 1, at first, deposition one N type epitaxial loayer 12 on a N type base material 10, and utilize one first mask on N type epitaxial loayer 12, to etch a plurality of grooves 14 then.As shown in Figure 2, then deposition one P type epitaxial loayer 16 in each groove 14 trims the upper surface of P type epitaxial loayer 16 and the upper surface of N type epitaxial loayer 12.As shown in Figure 3, on N type epitaxial loayer 12 and P type epitaxial loayer 16, cover an insulating barrier 18 subsequently.Afterwards, utilize one second mask on insulating barrier 18, to form a plurality of gate electrodes 20, and gate electrode 20 is located on the N type epitaxial loayer 12.As shown in Figure 4; As mask P type epitaxial loayer 16 and N type epitaxial loayer 12 are carried out a P type ion implantation technology with gate electrode 20; In N type epitaxial loayer 12 and P type epitaxial loayer 16, to form P mold base doped region 22; And carry out a hot injection process, to extend to gate electrode 20 P mold base doped region 22 overlapping.Then, utilize one the 3rd mask to carry out a N type ion implantation technology, in each P mold base doped region 22 of contiguous each gate electrode 20, to form two N type source doping region 24.As shown in Figure 5, next on gate electrode 20 and insulating barrier 18, cover a dielectric layer 26 and a boron-phosphorosilicate glass layer 28 in regular turn.Then; Utilize one the 4th mask; To be positioned at dielectric layer 26 on each P mold base doped region 22, boron-phosphorosilicate glass layer 28 carries out a photoetching and etch process with insulating barrier 18, on each P mold base doped region 22, forming a contact hole 30 respectively, and exposes P mold base doped region 22.As shown in Figure 6, then, carry out a P type ion implantation technology, in each P mold base doped region 22, form a P type contact doping district 32, and carry out a hot injection process, P type contact doping district 32 is contacted with each N type source doping region 24.At last, in each contact hole 30, insert contact plunger 34, and on boron-phosphorosilicate glass layer 28 and contact plunger 34, form one source pole metal level 36, and form a drain metal layer 38 10 times in N type base material.Hence one can see that; The manufacture method of known power transistor assembly with ultra interface is through etching the groove 14 with certain depth on N type epitaxial loayer 12; And then in groove 14, insert P type epitaxial loayer 16; Make each N type epitaxial loayer 12 constitute a vertical PN and connect face, also be called ultra interface, and each PN connects face and is arranged alternately in regular turn along horizontal direction with each P type epitaxial loayer 16.
Because the size downsizing gradually of power transistor assembly, the width that makes P type epitaxial loayer are also along with reduction, so the depth-to-width ratio of groove also needs big more.Yet, utilize the depth-to-width ratio of the produced groove of at present known etch process that certain restriction is arranged, even and the depth-to-width ratio of groove meet actual requirement, the sidewall of produced groove also can't be flat surface.Moreover when the depth-to-width ratio of groove increased, P type epitaxial loayer also was difficult for complete being filled in the groove, and easily in wherein producing the space, makes ultra interface defectiveness.In addition, because the sidewall of groove is the out-of-flatness surface, so the interface that P type epitaxial loayer contacts with N type epitaxial loayer also can't be flat surface.Whereby, the also out-of-flatness of depletion region between P type epitaxial loayer and the N type epitaxial loayer, and then the voltage endurance capability of the ultra interface of reduction.
In addition; Because ion implantation technology is limited with the degree of depth that admixture injects epitaxial loayer; Therefore there is utilization repeatedly to carry out the mode of N type brilliant technology of heap of stone and P type ion implantation technology in addition; The storehouse multilayer has the N type epitaxial loayer of P type doped region on N type base material in regular turn, makes the P type doped region of storehouse form a P type column doped region, to constitute ultra interface with adjacent storehouse N type epitaxial loayer.Yet the produced ultra interface of method also can't have flat surface thus, and must repeatedly build brilliant technology and ion implantation technology, the step of making the power transistor assembly is increased, and then promote the complexity and the cost of manufacture of technology.
In view of this, a kind of manufacture method with power semiconductor assembly of ultra interface is provided, also forms the ultra interface with smooth interface, the target of making great efforts for industry in fact with the complexity of simplifying technology.
Summary of the invention
Main purpose of the present invention is to provide a kind of making to have the method for the power semiconductor assembly of ultra interface, has the ultra interface that level and smooth PN connects face and perfect crystal structure with complexity and the formation of simplifying technology.
For reaching above-mentioned purpose, the present invention provides a kind of making to have the method for the power semiconductor assembly of ultra interface.At first, a substrate is provided, and substrate has one first conduction type.Then, in substrate, form at least one grid structure and at least one mask layer, and mask layer is located on the grid structure.Then, at least one sidewall of grid structure and mask layer, form a clearance wall, and expose the part substrate.Subsequently, remove the substrate that part exposes, to form at least one groove.Then, in groove, insert admixture source layer, wherein admixture source layer includes a plurality of admixtures, and admixture has one second conduction type.Then, carry out a hot injection process, dopant diffusion to substrate, is had a matrix doped region of second conduction type with formation, and constitute between matrix doped region and the substrate and one surpass interface.
The present invention carries out self-registered technology through forming earlier grid structure and the mask layer that is used for the grill-protected electrode structure, and on the sidewall of grid structure and mask layer, forming clearance wall, and the while definable goes out the width and the position of second groove.And; The present invention further utilizes hot injection process; To substrate, further can not receive the influence of the sidewall evenness of second groove to form smooth ultra interface, the dopant diffusion in the admixture source layer of inserting second groove with the voltage endurance capability of effective bring to power semiconductor subassembly.
Description of drawings
Fig. 1 to Fig. 6 has illustrated the method sketch map that known making has the power transistor assembly of ultra interface.
The making that Fig. 7 to Figure 15 has illustrated the preferred embodiment of the present invention has the method sketch map of the power semiconductor assembly of ultra interface.
Wherein, description of reference numerals is following:
10 N type base materials, 12 N type epitaxial loayers
14 grooves, 16 P type epitaxial loayers
18 insulating barriers, 20 gate electrodes
22 P mold base doped regions, 24 N type source doping region
26 dielectric layers, 28 boron-phosphorosilicate glass layers
32 P type contact doping districts, 30 contact holes
34 contact plungers, 36 source metal
102 substrates of 100 power semiconductor assemblies
104 base materials, 106 epitaxial loayers
108 grid structures, 110 mask layers
112 first grooves, 114 gate insulators
116 grid conducting layers, 118 dielectric layers
120 first hard mask layers, 122 clearance walls
124 first oxide skin(coating)s, 126 second hard mask layers
128 second oxide skin(coating)s, 130 second grooves
132 admixtures source layer 134 matrix doped region
136 source doping region, 138 source metal
140 drain metal layer
Embodiment
Please refer to Fig. 7 to Figure 15, the making that Fig. 7 to Figure 15 has illustrated one embodiment of the present invention has the method sketch map of the power semiconductor assembly of ultra interface.At first, as shown in Figure 7, a substrate 102 is provided, wherein substrate 102 has one first conduction type, and substrate 102 includes a base material 104 and is located at the epitaxial loayer 106 on the base material 104.Therefore, base material 104 also has first conduction type with epitaxial loayer 106.In present embodiment, first conduction type is the N type, but is not limited thereto.And N type epitaxial loayer 106 is formed on the N type base material 104 through a brilliant technology of heap of stone, but is not limited thereto.
Then, as shown in Figure 8, utilize one first photomask; In N type substrate 102, form a plurality of grid structures 108 and a plurality of mask layers 110; Make between two adjacent grid structures 108 and the mask layer 110 to have one first groove 112, and expose part N type substrate 102, wherein each mask layer 110 is located at respectively on each grid structure 108; And cover each grid structure 108, with mask as subsequent etch technology.Each grid structure 108 is made up of a gate insulator 114 and 116 of grid conducting layers, and gate insulator 114 is located between grid conducting layer 116 and the N type substrate 102, with grid conducting layer 116 and the N type substrate 102 of being electrically insulated.And each mask layer 110 includes a dielectric layer 118 and one first hard mask layer 120, and first hard mask layer 120 is located on the dielectric layer 118.In present embodiment, grid structure 108 can form with mask layer 110 simultaneously, but the invention is not restricted to this.Gate insulator of the present invention 114, grid conducting layer 116, dielectric layer 118 also can separate with first hard mask layer 120 and form.In addition, the quantity of grid structure 108 of the present invention and mask layer 110 is not limited to a plurality of, also can only have single respectively.
And; In present embodiment, the material that forms gate insulator 114 and dielectric layer 118 can be made up of the oxide with insulation characterisitic, for example silica; The material that forms grid conducting layer 116 can be made up of the silicon that is doped with the conduction admixture; For example be doped with the polysilicon or the amorphous silicon of P type or N type admixture, and the material that forms first hard mask layer 120 can include silicon nitride, but the invention is not restricted to this.
Next, as shown in Figure 9, respectively at formation one clearance wall 122 on two sidewalls of each grid structure 108 and each mask layer 110, and expose part N type substrate 102.In present embodiment; Each clearance wall 122 is a sandwich construction; Wherein each sandwich construction includes one first oxide skin(coating) 124, one second hard mask layer 126 and one second oxide skin(coating) 128; And first oxide skin(coating) 124, second hard mask layer 126 and second oxide skin(coating) 128 are located on each sidewall of corresponding grid structure 108 and mask layer 110 in regular turn, make each clearance wall 122 can include the composite construction of monoxide/nitride/oxide (ONO) layer.And; The material that forms first oxide skin(coating) 124 and second oxide skin(coating) 128 can be made up of the oxide with insulation characterisitic; Silica for example; And the material that forms second hard mask layer 126 can include silicon nitride, but the material of the present invention's first oxide skin(coating), second oxide skin(coating) and second hard mask layer is not limited thereto.In addition; The step that forms clearance wall can deposit one silica layer, a silicon nitride layer and one silica layer earlier in regular turn in mask layer and the substrate of N type; Carry out a comprehensive etch process then, for example the dry etching process of anisotropic is positioned at mask layer and the suprabasil silicon oxide layer of part N type, silicon nitride layer and silicon oxide layer to remove; And the formation clearance wall, but the invention is not restricted to this.In other embodiments of the invention, the step that forms each clearance wall also can be carried out three depositions respectively in regular turn and on each sidewall, formed first oxide skin(coating), second hard mask layer and second oxide skin(coating) with etch back process.
In addition; In present embodiment; First oxide skin(coating) 124 contacts with dielectric layer 118; And 126 of second hard mask layers contact with first hard mask layer 120, and first hard mask layer 120 and second hard mask layer 126 that makes first oxide skin(coating) 124 that includes oxide and dielectric layer 118 and include silicon nitride be wrapped-gate electrode structure 108 in regular turn, is damaged in subsequent etch technology to avoid grid structure 108.Second oxide skin(coating) 128 trims with second hard mask layer 126 in fact.And, the invention is not restricted to form clearance wall 122 respectively on two sidewalls of each grid structure 108 and each mask layer 108, also can at least one sidewall of each grid structure 108 and each mask layer 110, form clearance wall 122.
Then; Shown in figure 10; As mask, carry out N type substrate 102 and second oxide skin(coating) 128 are had a comprehensive etch process of high etching selectivity with clearance wall 122 and mask layer 108, that is the etch process that is carried out to the etch-rate of N type substrate 102 greater than etch-rate to second oxide skin(coating) 128 and first hard mask layer 120; Remove the N type substrate 102 that part exposes, between wantonly two adjacent segment walls 122, to form one second groove 130.Then; Carry out second oxide skin(coating) 128 and N type substrate 102 are had a comprehensive etch process of high etching selectivity; That is to the etch-rate of second oxide skin(coating) 128 greater than etch-rate, to remove second oxide skin(coating) 128 to the N type substrate 102 and first hard mask layer 120.In present embodiment, second groove 130 has a depth-to-width ratio, and depth-to-width ratio is in fact greater than 5, in subsequent technique, to form the ultra interface with enough degree of depth effectively.
It should be noted that; Forming only needs in the step of second groove 130 with established second oxide skin(coating) 128 and first hard mask layer 120 as mask; And do not need extra photomask to define the position of second groove 130; The comprehensive etch process that is carried out whereby capable of using to N type substrate 102 with to the different positions of voluntarily aiming at second groove 130 of second oxide skin(coating) 128, in N type substrate 102, to form second groove 130 with the etch-rate of first hard mask layer 120.It should be noted that in addition; In the step that forms clearance wall 122; The width of the N type substrate 102 that is exposed between the wantonly two adjacent segment walls 122 is same as the width of second groove 130 in fact, whereby with clearance wall 122 with mask layer 110 during as mask definable go out the width of second groove 130.And, in the step that forms clearance wall 122, further can form time of clearance wall 122 through control, adjust institute and expose the width of N type substrate 102, and then reach the width of second groove 130 of institute's desire formation.
In other embodiments of the invention; N type substrate 102 is not limited to separate with second oxide skin(coating) 128 and removes; Can also first hard mask layer 120 and second hard mask layer 126 be mask; Simultaneously etching is carried out in the N type substrate 102 and second oxide skin(coating) 128, and adjustment is to the etch-rate of N type substrate 102 etch-rate greater than second oxide skin(coating) 128, to form the second enough dark groove 130.
Then, shown in figure 11, in each second groove 130, insert admixture source layer 132, and each admixture source layer 132 includes a plurality of admixtures, wherein each admixture has one second conduction type.Then; Carry out a hot injection process; In dopant diffusion to N type substrate 102,, make that formation one vertical PN connects face between each matrix doped region 134 and the N type substrate 102 in the N type substrate 102 around each second groove 130, to form a matrix doped region 134 with second conduction type; Also be one to surpass interface, and.In present embodiment, second conduction type is the P type, but is not limited thereto, and first conduction type of the present invention and second conduction type are also interchangeable.And the material that forms admixture source layer 132 includes Pyrex, and (boron-silicate glass BSG), but is not limited thereto.It should be noted that the admixture source layer 132 that includes Pyrex is a fluid, in the time of therefore in inserting each second groove 130, can't too highly because of the depth-to-width ratio of second groove 130 can't fill up second groove 130 fully.And; Each P mold base doped region 134 utilizes hot injection process will be arranged in P type dopant diffusion to the N type substrate 102 of admixture source layer 132 and forms; Therefore the PN between each P mold base doped region 134 and the N type substrate 102 connects the ultra interface that face constitutes and can be a level and smooth interface; Although and second groove 130 has irregular sidewall, present embodiment still can have smooth interface under the situation because of thermal diffusion by the ultra interface that is constituted between each P mold base doped region 134 and the N type substrate 102.In addition; P mold base doped region utilizes 102 formation of P type dopant diffusion to N type substrate; Therefore the crystal structure of P mold base doped region and the substrate of N type 102 are made up of same crystal structure, make formed PN connect face and can have a complete crystal structure, further can effectively promote voltage endurance capability.Moreover; The doping content of each P mold base doped region 134 also can be because of each P mold base doped region 134 be low more near N type substrate 102 along with more by the formation of hot injection process, and each P mold base doped region 134 of therefore contiguous second groove 130 can be used as a P type contact doping district.
Subsequently; Shown in figure 12, be mask with first hard mask layer 120 and second hard mask layer 126, carry out a comprehensive etch process; The dry etching process of anisotropic for example; Only removing the admixture source layer 132 that is positioned at second groove, 130 tops, and stay the admixture source layer 130 that is arranged in second groove 130, and expose the part P mold base doped region 134 that is positioned at second groove, 130 both sides.Then; Be mask with first hard mask layer 120 and second hard mask layer 126 again; Carry out a N type ion implantation technology and a hot injection process; In each P mold base doped region 134 of second groove, 130 both sides, form two N type source doping region 136 respectively, make each N type source doping region 136 be positioned at the below of corresponding first oxide skin(coating) 124 and second hard mask layer 126, and overlap with corresponding grid structure 108.Whereby, each N type source doping region 136 can be used as the one source pole of power semiconductor assembly, and N type substrate 102 can be used as a drain electrode of power semiconductor assembly.Between each N type source doping region 136 and N type substrate 102 and the P mold base doped region 134 of contiguous corresponding grid structure 108 can be used as a channel region of power semiconductor assembly.It should be noted that; Before forming N type source doping region 136; The admixture source layer 132 that is arranged in second groove 130 does not remove; And can be in order to cover the effect of N type ion implantation technology, receiving N type ion with the N type substrate 102 of avoiding second groove, 130 bottoms injects, and then influences the usefulness of power semiconductor assembly.
Then, shown in figure 13, be mask with first hard mask layer 120 and second hard mask layer 128 again, carry out an etch process, wet etching process for example is to remove the admixture source layer 132 that is positioned at second groove 130.Because each P mold base doped region 134 of contiguous second groove 130 can be used as P type contact doping district; Therefore the P mold base doped region 134 of present embodiment does not need in each P mold base doped region 134 of each N type source doping region 136 below, to inject a P type contact doping district, but the invention is not restricted to this.In other embodiments of the invention; Also can be behind the source of the admixture in removing second groove 130 layer 132; Carry out a P type ion implantation technology again; In each P mold base doped region 134 of each N type source doping region 136 below, to form a P type contact doping district, make the doping content of the doping content in P type contact doping district greater than P mold base doped region 134.
Then, shown in figure 14, carry out an etch process, for example wet etching process removes first hard mask layer 120 and second hard mask layer 126.At last; Shown in figure 15, utilize one second photomask, in N type substrate 102, form one source pole metal level 138; And source metal 138 is inserted in each second groove 130, to be electrically connected to each N type source doping region 136 and P mold base doped region 134 as P type contact doping district.And, form a drain metal layer 140 102 times in the substrate of N type, so that N type substrate 102 is electrically connected to the external world.So far accomplished the power semiconductor assembly 100 of present embodiment.
In sum, the present invention carries out self-registered technology through forming earlier grid structure and the mask layer that is used for the grill-protected electrode structure, and on the sidewall of grid structure and mask layer, forming clearance wall, and the while definable goes out the width and the position of second groove.And, second groove can clearance wall and mask layer be that mask forms, do not define and need not spend photomask.Moreover; The present invention further utilizes the admixture source layer with fluid properties and admixture to insert second groove; And impose hot injection process; Further can not receive the influence of the sidewall evenness of second groove to form ultra interface smooth and tool perfect crystal structure, with the voltage endurance capability of effective bring to power semiconductor subassembly.In addition; The present invention further has the clearance wall and first hard mask layer with silicon nitride of ONO layer through formation; Make etch process and ion implantation technology can not damage grid structure, and need not expend extra photomask, can in substrate, form doped region; And then simplify the method for making power semiconductor assembly, and effectively reduce cost of manufacture with ultra interface.
The above is merely the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. a making has the method for the power semiconductor assembly of ultra interface, it is characterized in that, includes:
One substrate is provided, and said substrate has one first conduction type;
In said substrate, form at least one grid structure and at least one mask layer, and said mask layer is located on the said grid structure;
On at least one sidewall of said grid structure and said mask layer, form a clearance wall, and expose the said substrate of part;
Remove the said substrate that part exposes, to form at least one groove;
In said groove, insert admixture source layer, wherein said admixture source layer includes a plurality of admixtures, and said admixture has one second conduction type; And
Carry out a hot injection process, these dopant diffusion to the said substrate, have a matrix doped region of said second conduction type with formation, and formation one are surpassed interface between said matrix doped region and the said substrate.
2. the method for claim 1 is characterized in that, said mask layer includes one first hard mask layer and a dielectric layer.
3. method as claimed in claim 2 is characterized in that the material that forms said first hard mask layer includes silicon nitride.
4. the method for claim 1 is characterized in that, in the step that forms said clearance wall, the width of the said substrate that exposes is same as the width of said groove in fact.
5. the method for claim 1 is characterized in that, said groove has a depth-to-width ratio, and said depth-to-width ratio is greater than 5.
6. the method for claim 1 is characterized in that, the step that forms said groove comprises carries out an etch process, and said etch process to the etch-rate of said substrate greater than etch-rate to said mask layer and said clearance wall.
7. method as claimed in claim 6 is characterized in that, said etch process is a mask with said mask layer and said clearance wall.
8. the method for claim 1 is characterized in that, said clearance wall is a sandwich construction.
9. method as claimed in claim 8; It is characterized in that; Said sandwich construction includes one first oxide skin(coating), one second hard mask layer and one second oxide skin(coating), and said first oxide skin(coating), said second hard mask layer and said second oxide skin(coating) are located on the said sidewall of said grid structure and said mask layer in regular turn.
10. method as claimed in claim 9 is characterized in that the material that forms said second hard mask layer includes silicon nitride.
11. method as claimed in claim 9 is characterized in that, between the step that forms said groove and the step of inserting said admixture source layer, said method also includes and removes said second oxide skin(coating).
12. method as claimed in claim 9; It is characterized in that; After said hot injection process, said method also includes formation one source pole doped region in the said matrix doped region of said groove one side, and said source doping region has said first conduction type.
13. method as claimed in claim 12 is characterized in that, the step that forms said source doping region is a mask with said mask layer and said second hard mask layer.
14. method as claimed in claim 12 is characterized in that, after the step that forms said source doping region, said method also includes:
Remove said admixture source layer and said second hard mask layer; And
In said substrate, form the one source pole metal level, and said source metal is inserted in the said groove.
15. the method for claim 1 is characterized in that, said admixture source layer is made up of Pyrex.
16. the method for claim 1 is characterized in that, said first conduction type is the N type, and said second conduction type is the P type.
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| TW099147022 | 2010-12-30 | ||
| TW99147022A TWI405271B (en) | 2010-12-30 | 2010-12-30 | Method of manufacturing power semiconductor device with super junction |
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| US20040137666A1 (en) * | 2001-07-05 | 2004-07-15 | International Rectifier Corporation | Low voltage super junction mosfet simulation and experimentation |
| CN1823423A (en) * | 2003-12-26 | 2006-08-23 | 罗姆股份有限公司 | Semiconductor device and its manufacturing method |
| CN101814436A (en) * | 2009-11-05 | 2010-08-25 | 苏州博创集成电路设计有限公司 | Method for preparing longitudinal high-pressure deep-slot transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6627949B2 (en) * | 2000-06-02 | 2003-09-30 | General Semiconductor, Inc. | High voltage power MOSFET having low on-resistance |
| US6656797B2 (en) * | 2001-12-31 | 2003-12-02 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation |
| US20050145915A1 (en) * | 2004-01-06 | 2005-07-07 | Badredin Fatemizadeh | Selective epi-region method for integration of vertical power MOSFET and lateral driver devices |
| US7378317B2 (en) * | 2005-12-14 | 2008-05-27 | Freescale Semiconductor, Inc. | Superjunction power MOSFET |
| US7476591B2 (en) * | 2006-10-13 | 2009-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral power MOSFET with high breakdown voltage and low on-resistance |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1128474C (en) * | 1997-06-10 | 2003-11-19 | 三星电子株式会社 | Method for manufacturing semiconductor memory device for preventing bit line oxidation and semiconductor memory device |
| US20040137666A1 (en) * | 2001-07-05 | 2004-07-15 | International Rectifier Corporation | Low voltage super junction mosfet simulation and experimentation |
| CN1823423A (en) * | 2003-12-26 | 2006-08-23 | 罗姆股份有限公司 | Semiconductor device and its manufacturing method |
| CN101814436A (en) * | 2009-11-05 | 2010-08-25 | 苏州博创集成电路设计有限公司 | Method for preparing longitudinal high-pressure deep-slot transistor |
Also Published As
| Publication number | Publication date |
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| TW201227829A (en) | 2012-07-01 |
| TWI405271B (en) | 2013-08-11 |
| CN102543749B (en) | 2014-10-29 |
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