CN102543737A - Preparation method for double-gate VDMOS (vertical double-diffused metal oxide semiconductor) with self-aligned metallic silicide technology - Google Patents
Preparation method for double-gate VDMOS (vertical double-diffused metal oxide semiconductor) with self-aligned metallic silicide technology Download PDFInfo
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Abstract
The invention discloses a preparation method for double-gate VDMOS (vertical double-diffused metal oxide semiconductor) with a self-aligned metallic silicide technology, which includes the steps: 1) forming control gates and a shield gate, and partially superposing the control gates and the shield gate, wherein the shield gate is positioned above a drift region between wells, and the control gates are isolated from the shield gate through insulating layers; 2) depositing a dielectric layer after the wells and source regions are formed, and etching the dielectric layer to form spacers on one side of each control gate and on two sides of the shield gate; and 3) forming metallic silicides on the surfaces of the shield gate, the control gates and the source regions by means of the self-aligned metallic silicide forming technology. The VDMOS device prepared by the method has lower drain-source on resistance.
Description
Technical field
The present invention relates to the preparation method of a kind of VDMOS, particularly a kind of preparation method with double grid VDMOS of self-aligned metal silicate technology.
Background technology
Along with the continuous development of semiconductor fabrication process, the conversion efficiency and the dimensional requirement of power-supply management system improved day by day.The dwindling of integrated circuit size makes chip operation voltage reduce, so the conversion efficiency of system and size are even more important.The parasitic capacitance of switch is to hinder one of key factor that power-supply system efficient improves and size reduces in the Switching Power Supply.
VDMOS (longitudinal double diffusion metal oxide semiconductor field effect transistor) structure is the switching device commonly used of power-supply management system.Tradition VDMOS has only one deck grid, works to control switch conduction and shutoff, and the electric capacity between its grid leak becomes device most critical parasitic capacitance for this reason because of the Miller effect, and the reducing of this electric capacity plays very important effect to the raising of switch reduction in power consumption and speed.Reduction in power consumption makes efficient improve, and the raising of speed makes inductance and capacitor size in the system reduce.
Therefore, the VDMOS device architecture with low parasitic capacitance needs.
Summary of the invention
The technical problem that the present invention will solve provides a kind of preparation method with double grid VDMOS of self-aligned metal silicate technology, and its prepared V DMOS has on state resistance between lower drain-source.
For solving the problems of the technologies described above, the preparation method with double grid VDMOS of self-aligned metal silicate technology of the present invention comprises the steps:
1) formation of control gate and shield grid, said shield grid are on the drift region between the tagma, and said control gate and said shield grid partial stack, isolate through insulating barrier between said control gate and the said shield grid;
2) and after tagma and source region form, dielectric layer deposited, then the said dielectric layer of etching is at said control gate and shield grid both sides formation side wall;
3) carry out self-aligned metal silicate afterwards and form technology, at said shield grid, control gate and surface, source region form metal silicide.
Adopt method prepared V DMOS device of the present invention,, make gate resistance reduce greatly, thereby improve the switching speed of device greatly owing on basis, increased the autoregistration silication technique for metal with control gate and shield grid.The autoregistration metal silication also makes the on state resistance between the device drain-source reduce greatly, thus the power consumption when reducing break-over of device greatly.Fig. 1 and Fig. 2 are the VDMOS structure with double grid, and the adding of shield grid has reduced the parasitic capacitance of device to a certain extent.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is a kind of VDMOS structural representation;
Fig. 2 is another kind of VDMOS structural representation;
Fig. 3 is the VDMOS structural representation with autoregistration silication technique for metal;
Fig. 4 is another kind of VDMOS structural representation with autoregistration silication technique for metal;
Fig. 5 accomplishes source region structural representation afterwards among the preparation method of the present invention;
Fig. 6 is the structural representation of preparation method of the present invention after the intact dielectric layer of deposit;
Fig. 7 is the structural representation of preparation method of the present invention after forming side wall;
Fig. 8 is the structural representation of preparation method of the present invention after forming metal silicide;
Fig. 9 is a method flow sketch map of the present invention;
Figure 10 is an examples preparation schematic flow sheet of the present invention.
Figure 11 is another example process sketch map of control gate among the present invention and shield grid formation.
Embodiment
Preparation method with double grid VDMOS of self-aligned metal silicate technology comprises the steps (seeing Fig. 9 and Figure 10):
1) the formation (see figure 5) of control gate and shield grid, said shield grid is positioned on the drift region, and said control gate and said shield grid partial stack, isolates through insulating barrier between said control gate and the said shield grid.
2) and after tagma and source region form, the dielectric layer deposited (see figure 6), thickness can be the 100-10000 dust, and then the etching dielectric layer forms the side wall (see figure 7) on control gate and shield grid both sides, and exposes surperficial by the polysilicon surface of side wall protection and source.Etching generally adopts the dry etching method.Dielectric layer can be silicon nitride or silicon oxide layer.
3) carry out self-aligned metal silicate afterwards and form technology, at shield grid, control gate and surface, source region form the metal silicide (see figure 8).The object lesson that metal silicide forms is: first deposit titanium (also optional other metal) is to substrate surface; Then carry out making titanium and pasc reaction greater than 700 ℃ high-temperature process; Wet method is removed unreacted titanium; Carry out high-temperature process afterwards once more, generate the low-resistance titanium silicide.This step is carried out the autoregistration silication technique for metal for utilizing side wall, and metal also can be cobalt or nickel.
All the other steps are identical with traditional handicraft: the deposit tunic; Form contact hole through photoetching, the dried quarter, with the metal filling perforation, with dried quarter or cmp removing unnecessary metal; The depositing metal film carries out photoetching, does and carve the formation front description metal film; In that silicon wafer thinning back side, the back side are formed metallic film etc., finally form VDMOS structure as shown in Figure 3.In another embodiment, form VDMOS structure as shown in Figure 4.Wherein shield grid can form with the source region and be electrically connected, and also can float.
The idiographic flow that above-mentioned control gate and shield grid form can be (see figure 10):
(1) after the control gate preparation was accomplished, at whole silicon wafer surface deposition insulating barrier, said insulating barrier covered said control gate;
(2) follow deposit second layer polysilicon;
(3) second layer polysilicon is carried out chemical wet etching, form shield grid, shield grid is positioned on the drift region in the middle of the control gate, and the both sides of shield grid superpose respectively and are set in place on the control gate of the VDMOS on its both sides device.
The idiographic flow that control gate and shield grid form also can be (seeing Figure 11):
(1) after the grid oxygen of VDMOS device forms, deposit ground floor polysilicon, chemical wet etching forms shield grid, and this shield grid is positioned on the drift region;
(2) at whole silicon wafer surface deposition insulating barrier, insulating barrier covers shield grid;
(3) follow deposit second layer polysilicon, second layer polysilicon is carried out chemical wet etching, form control gate, control gate is positioned at the both sides of shield grid, and control gate has on the said shield grid of partial stack.
Preparation method of the present invention, the combination through autoregistration silication technique for metal and double grid VDMOS device architecture makes gate resistance reduce greatly, thereby improves the switching speed of device greatly.The adding of autoregistration silication technique for metal also makes the on state resistance between the device drain-source reduce greatly, thus the power consumption when reducing break-over of device greatly.
Claims (7)
1. the preparation method with double grid VDMOS of self-aligned metal silicate technology is characterized in that, comprises the steps:
1) formation of control gate and shield grid, said shield grid are on the drift region between the tagma, and said control gate and said shield grid partial stack, isolate through insulating barrier between said control gate and the said shield grid;
2) and after tagma and source region form, dielectric layer deposited, then the said dielectric layer of etching is at said control gate and shield grid both sides formation side wall;
3) carry out self-aligned metal silicate afterwards and form technology, at said shield grid, control gate and surface, source region form metal silicide.
2. preparation method as claimed in claim 1 is characterized in that: said dielectric layer is silicon nitride layer or silicon oxide layer.
3. preparation method as claimed in claim 1 is characterized in that: the thickness of said dielectric layer is the 100-10000 dust.
4. like each described preparation method in the claim 1 to 3, it is characterized in that: the flow process that said control gate and shield grid form is:
(1) after the control gate preparation was accomplished, at whole silicon wafer surface deposition insulating barrier, said insulating barrier covered said control gate;
(2) follow deposit second layer polysilicon;
(3) said second layer polysilicon is carried out chemical wet etching, form shield grid, and the both sides of said shield grid superpose respectively and are set in place on the control gate of the VDMOS on its both sides device.
5. preparation method as claimed in claim 4 is characterized in that: the formation technology of said metal silicide is: first deposit titanium, cobalt metal or nickel metal are to substrate surface; Then carry out making metal and pasc reaction greater than 700 ℃ high-temperature process; Wet method is removed unreacted metal; Carry out high-temperature process afterwards once more, generate the low resistance metal silicide.
6. like each described preparation method in the claim 1 to 3, it is characterized in that: the flow process that said control gate and shield grid form is:
(1) after the grid oxygen of VDMOS device forms, deposit ground floor polysilicon, chemical wet etching forms shield grid, and said shield grid is positioned on the drift region;
(2) at whole silicon wafer surface deposition insulating barrier, said insulating barrier covers said shield grid;
(3) follow deposit second layer polysilicon, said second layer polysilicon is carried out chemical wet etching, form control gate, said control gate is positioned at the both sides of said shield grid, and said control gate has on the said shield grid of partial stack.
7. preparation method as claimed in claim 6 is characterized in that: the formation technology of said metal silicide is: first deposit titanium, cobalt metal or nickel metal are to substrate surface; Then carry out making metal and pasc reaction greater than 700 ℃ high-temperature process; Wet method is removed unreacted metal; Carry out high-temperature process afterwards once more, generate the low resistance metal silicide.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716186A (en) * | 2014-01-16 | 2015-06-17 | 黎茂林 | Planar field effect transistor, method of manufacturing the same, and charge retention |
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| US20030190787A1 (en) * | 2001-12-14 | 2003-10-09 | Stmicroelectronics S.R.L. | Process for realizing a channel scaled and small body gradient VDMOS for high current densities and low driving voltages |
| US6825531B1 (en) * | 2003-07-11 | 2004-11-30 | Micrel, Incorporated | Lateral DMOS transistor with a self-aligned drain region |
| CN1691295A (en) * | 2004-04-23 | 2005-11-02 | 中国科学院微电子研究所 | Self-aligning silicide method for RF lateral diffusion field-effect transistor |
| CN101692426A (en) * | 2009-10-14 | 2010-04-07 | 上海宏力半导体制造有限公司 | Method for preparing vertical double-diffusion MOS transistor |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030190787A1 (en) * | 2001-12-14 | 2003-10-09 | Stmicroelectronics S.R.L. | Process for realizing a channel scaled and small body gradient VDMOS for high current densities and low driving voltages |
| US6825531B1 (en) * | 2003-07-11 | 2004-11-30 | Micrel, Incorporated | Lateral DMOS transistor with a self-aligned drain region |
| CN1691295A (en) * | 2004-04-23 | 2005-11-02 | 中国科学院微电子研究所 | Self-aligning silicide method for RF lateral diffusion field-effect transistor |
| CN101692426A (en) * | 2009-10-14 | 2010-04-07 | 上海宏力半导体制造有限公司 | Method for preparing vertical double-diffusion MOS transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716186A (en) * | 2014-01-16 | 2015-06-17 | 黎茂林 | Planar field effect transistor, method of manufacturing the same, and charge retention |
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