CN102543673A - Wafer structure and manufacturing method of alignment mark of same - Google Patents
Wafer structure and manufacturing method of alignment mark of same Download PDFInfo
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- CN102543673A CN102543673A CN2010106053841A CN201010605384A CN102543673A CN 102543673 A CN102543673 A CN 102543673A CN 2010106053841 A CN2010106053841 A CN 2010106053841A CN 201010605384 A CN201010605384 A CN 201010605384A CN 102543673 A CN102543673 A CN 102543673A
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- alignment mark
- dot matrix
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Abstract
The invention relates to a wafer structure which comprises a dielectric layer and an alignment mark which is arranged on the dielectric layer and used for alignment during wafer photoetching, wherein the alignment mark is composed of a dot matrix. The invention also relates to a manufacturing method of the alignment mark. The alignment mark of the dot matrix in the invention can be used for effectively avoiding grain packing, in addition, the punctated alignment mark can achieve a good polishing effect through a chemical mechanical grinding method, thereby guaranteeing the perfect alignment when a wafer is stacked, and improving the qualification rate of the manufactured wafer.
Description
[technical field]
The present invention relates to semiconductor chip and make the field, especially relate to a kind of manufacture method and corresponding crystal circle structure of alignment mark.
[background technology]
In ic manufacturing process, need frequently carry out photoetching.The pattern alignment that the photoetching of each level all will stay the figure and the previous level of this level before exposure.The purpose of the process of contraposition be with the figure maximal accuracy on the reticle cover on the disk on the already present figure.The sandwich construction of wafer can be divided into line level and hole level, and alignment mark comprises the alignment mark of line level and the alignment mark of hole level.
During the conventional semiconductor chip is integrated; Interconnection between each wafer sandwich construction is through realizing at contact hole or through hole filling metallic conductor; Therefore each interlayer is extremely important in the connection of contact hole or through hole; If incorrect the connection then can be caused situation about opening circuit, cause whole system to lose efficacy.Because the integrated level of circuit is very high on the wafer, so the sandwich construction middle level just needs accurately aim at during with the interlayer complex superposition, avoids the interlayer connection to go wrong.For auxiliary level to level alignment, need on dielectric layer, print alignment mark, make follow-up metal level aim at stack with dielectric layer according to alignment mark.Alignment mark is generally wire, can judge in the alignment case at two ends whether dielectric layer is aimed at reticle through the wire alignment mark.In the process of planarization, usually need carry out cmp (CMP) like the tungsten metal level to metal level.Normally, the wire alignment mark is owing to the hole that abrasion produces can be filled by some abrasive materials, like grinding agent.Thereby cause linear alignment mark to be destroyed easily, and and then in photoetching, can cause wafer alignment to lose efficacy, serious even make wafer can't accomplish stack, and used by the machine refusal.And though special grinding step to the hole is arranged in the cmp program, the grinding step in this hole is not suitable for the grinding of wire mark, can produce the wire mark to destroy, and cause one deck alignment failure down.
[summary of the invention]
Given this, being necessary can't precise superposing and the technical problem that is wasted to occurring alignment failure or wafer in traditional wafer complex superposition technology, and a kind of crystal circle structure and corresponding alignment mark manufacture method of accurately aiming at of realizing is provided.
A kind of crystal circle structure comprises dielectric layer and is located at the alignment mark of aiming at when being used for wafer photolithography on the dielectric layer that said alignment mark is made up of dot matrix.
A kind of manufacture method of alignment mark comprises:
Making has the mask of alignment mark, and said alignment mark is a lattice structure;
The coating photoresist;
Said alignment mark is made public on said photoresist;
The said photoresist of etching.
Technique effect of the present invention is: the alignment mark of dot matrix can be avoided the filling of abrasive grains effectively; The alignment mark of point-like can reach good polishing effect through the method for cmp in addition, thereby guarantees that wafer can accurately aim at when range upon range of, reduces the ratio that wafer is wasted.
[description of drawings]
Fig. 1 is the form of alignment mark on the traditional wafer;
Fig. 2 is the form according to alignment mark on the wafer of one embodiment of the present invention.
Fig. 3 is the manufacture method flow process according to the alignment mark of one embodiment of the present invention.
[embodiment]
As shown in Figure 1, be the form of alignment mark 1 on traditional wafer.This alignment mark 1 is the wire of space.Traditional wire alignment mark 1 is printed on the dielectric layer, when carrying out cmp, because grinding agent mainly is a particulate material, clogs gap between line easily, causes aiming at unusual.In addition, owing to the hole of the wire alignment mark that produces of abrasion also can be stopped up by the abrasion material, and then cause to aim to lead and often reach photoetching and fail.
Shown in Figure 2ly be the alignment mark figure on the crystal circle structure that provides according to one embodiment of the present invention.This crystal circle structure comprises dielectric layer and is located at the alignment mark of aiming at when being used for wafer photolithography on the dielectric layer 2.This alignment mark 2 is made up of dot matrix.This dot matrix is preferably homodisperse form, whole rectangular arranging.The sandwich construction that forms semiconductor device is realized aiming at by alignment mark 2, injects through photoetching or ion to form again.
The each point aperture of this alignment mark 2 is less than the abrasive grains diameter, thereby guarantees that each point can not filled by abrasive grains, causes the inefficacy of alignment mark 2.In other optional execution modes, the spacing between alignment mark 2 each points can make it be not easy to clog impurity through selecting suitable dot spacing greater than the abrasive grains diameter.
Whole rectangular the arranging of the dot matrix of this alignment mark 2.In one embodiment, dot matrix is evenly to be arranged in and is distributed on the dielectric layer on horizontal stroke, the vertical Cutting Road.The spot diameter scope of alignment mark 2 each dot matrix is 0.2 micron to 0.4 micron, and the dot spacing scope is 0.12 micron to 0.4 micron.
Shown in Figure 3 is manufacture method according to a kind of alignment mark of another embodiment of the present invention.In conjunction with shown in Figure 2, the manufacture method of this alignment mark comprises:
Step S302 makes the mask with alignment mark, and this alignment mark is a lattice structure;
Step S304 is coated with photoresist on wafer;
Step S306, with the graph exposure of alignment mark on the aforementioned mask on wafer;
Step S308, this has the wafer of alignment mark figure etching, forms the alignment mark of lattice-like.
Present embodiment adopts the alignment mark 2 of dot matrix, selects suitable dot spacing to be not easy to clog material.And after polishing,, also can clean easily, can not influence the accurate aligning of each interlayer of wafer, and the alignment mark of point-like more help polishing even there is material residual.
The above embodiment has only expressed several kinds of execution modes of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art under the prerequisite that does not break away from the present invention's design, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with accompanying claims.
Claims (10)
1. a crystal circle structure comprises dielectric layer and is located at the alignment mark of aiming at when being used for wafer photolithography on the dielectric layer, and it is characterized in that, said alignment mark is made up of dot matrix.
2. crystal circle structure as claimed in claim 1 is characterized in that, said dot matrix is rectangular arranges.
3. crystal circle structure as claimed in claim 1 is characterized in that, the dot spacing of said dot matrix is 0.12 micron to 0.4 micron.
4. crystal circle structure as claimed in claim 3 is characterized in that, the abrasive grains diameter of the gap clearance that said dot matrix forms when grinding said dielectric layer.
5. crystal circle structure as claimed in claim 1 is characterized in that, the diameter of the point of said dot matrix is 0.2 micron to 0.4 micron.
6. crystal circle structure as claimed in claim 5 is characterized in that, the abrasive grains diameter of the diameter of the point of said dot matrix when grinding said dielectric layer.
7. the crystal circle structure that is used to make semiconductor chip as claimed in claim 1 is characterized in that, said lattice site is being uniformly distributed on the said dielectric layer on horizontal stroke, the vertical Cutting Road.
8. the manufacture method of an alignment mark is characterized in that, comprising:
Making has the mask of alignment mark, and said alignment mark is a lattice structure;
The coating photoresist;
Said alignment mark is made public on said photoresist;
The said photoresist of etching.
9. alignment mark manufacture method as claimed in claim 8 is characterized in that, the dot spacing of said dot matrix is 0.12 micron to 0.4 micron.
10. alignment mark manufacture method as claimed in claim 8 is characterized in that, the diameter of the point of said dot matrix is 0.2 micron to 0.4 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106053841A CN102543673A (en) | 2010-12-27 | 2010-12-27 | Wafer structure and manufacturing method of alignment mark of same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106053841A CN102543673A (en) | 2010-12-27 | 2010-12-27 | Wafer structure and manufacturing method of alignment mark of same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102543673A true CN102543673A (en) | 2012-07-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010106053841A Pending CN102543673A (en) | 2010-12-27 | 2010-12-27 | Wafer structure and manufacturing method of alignment mark of same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104608265A (en) * | 2014-12-31 | 2015-05-13 | 广州兴森快捷电路科技有限公司 | High multilayer semiconductor test board perforating method |
| CN111933618A (en) * | 2020-08-13 | 2020-11-13 | 武汉新芯集成电路制造有限公司 | Wafer assembly with alignment mark, forming method thereof and wafer alignment method |
| CN113471061A (en) * | 2021-06-30 | 2021-10-01 | 颀中科技（苏州）有限公司 | Preparation method of wafer surface dielectric layer, wafer structure and forming method of bump |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146969A (en) * | 1999-01-19 | 2000-11-14 | Chartered Semiconductor Manufacturing Ltd. | Printing optimized global alignment mark at contact/via layers |
| KR20020002653A (en) * | 2000-06-30 | 2002-01-10 | 박종섭 | Alignment mark for exposure process |
| CN1967837A (en) * | 2005-11-16 | 2007-05-23 | 国际商业机器公司 | Alignment mark with improved resistance to dicing induced cracking and delamination in the scribe region |
-
2010
- 2010-12-27 CN CN2010106053841A patent/CN102543673A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146969A (en) * | 1999-01-19 | 2000-11-14 | Chartered Semiconductor Manufacturing Ltd. | Printing optimized global alignment mark at contact/via layers |
| KR20020002653A (en) * | 2000-06-30 | 2002-01-10 | 박종섭 | Alignment mark for exposure process |
| CN1967837A (en) * | 2005-11-16 | 2007-05-23 | 国际商业机器公司 | Alignment mark with improved resistance to dicing induced cracking and delamination in the scribe region |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104608265A (en) * | 2014-12-31 | 2015-05-13 | 广州兴森快捷电路科技有限公司 | High multilayer semiconductor test board perforating method |
| CN104608265B (en) * | 2014-12-31 | 2016-09-14 | 广州兴森快捷电路科技有限公司 | The boring method of high multi-lager semiconductor test board |
| CN111933618A (en) * | 2020-08-13 | 2020-11-13 | 武汉新芯集成电路制造有限公司 | Wafer assembly with alignment mark, forming method thereof and wafer alignment method |
| CN111933618B (en) * | 2020-08-13 | 2022-01-28 | 武汉新芯集成电路制造有限公司 | Wafer assembly with alignment mark, forming method thereof and wafer alignment method |
| CN113471061A (en) * | 2021-06-30 | 2021-10-01 | 颀中科技（苏州）有限公司 | Preparation method of wafer surface dielectric layer, wafer structure and forming method of bump |
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Free format text: FORMER OWNER: WUXI HUARUN SHANGHUA TECHNOLOGY CO., LTD. Effective date: 20131218 |
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Effective date of registration: 20131218 Address after: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Applicant after: Wuxi CSMC Semiconductor Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Applicant before: Wuxi CSMC Semiconductor Co., Ltd. Applicant before: Wuxi Huarun Shanghua Technology Co., Ltd. |
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Application publication date: 20120704 |