CN102543212B - Data management in the flash memory of the probability of use electric charge disturbance - Google Patents
Data management in the flash memory of the probability of use electric charge disturbance Download PDFInfo
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- CN102543212B CN102543212B CN201110435900.5A CN201110435900A CN102543212B CN 102543212 B CN102543212 B CN 102543212B CN 201110435900 A CN201110435900 A CN 201110435900A CN 102543212 B CN102543212 B CN 102543212B
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Abstract
Describe flash memory system and the data managing method of the history that use system disturbs the sensitivity operated and the electric charge performed by system interference to operate for electric charge.In embodiments of the present invention, the sensitivity for electric charge interference operation is implemented with interference strength matrix, and wherein institute's selection operation has the numerical value being associated, and it is the estimation of relative intensity of this operation causing the interference in the electric charge causing error in data.Interference strength matrix can also include indicating electric charge to increase or the direction of the mistake of loss.Interference strength matrix can be determined by the device carrying out self-test, wherein triggers electric charge interference mistake by execution institute selection operation, until there is the mistake that can detect that.In alternative embodiment, determine interference strength matrix by testing the selected unit from community of interest.
Description
Related application
Related application (it the is commonly assigned application) entitled " NOR flash memory of present inventor
The early stage detection of middle deterioration ".Serial number will provide when obtaining.
Entitled " the NAND sudden strain of a muscle of related application (it is commonly assigned application) of present inventor
Deposit the early stage detection of middle deterioration ".Serial number will provide when obtaining.
Technical field
The disclosure relates generally to nonvolatile semiconductor memory, relates more specifically to the mistake inspection of flash memory
Survey and alignment technique.
Background technology
EEPROM and flash memory (NOR and NAND) use floating boom (floating gate, FG) to deposit
Storage electric charge is to represent information.(it can be durable for device in the program/erase cycle for these memory devices
Erasing-programming number of operations is applied with restriction) suffer degradation mechanisms afterwards.Multilevel-cell (MLC,
Multi-Level Cell) flush memory device typically than single layer cell (SLC, Single-Level Cell) device have
There is the lowest program/erase cycle ruggedness.
Various programming and erasing operations may result in increase or the loss of the electric charge in adjacent cells, and this is referred to as " dry
Disturb ".When the result as the programming that neighbouring unit is performed or read operation, the initial/programming shape of unit
When state changes, interference mistake occurs.Interference mistake is soft error.When by reading with interference unit in shape
On body, another unit close or Compliance control line occurs " reading when changing the quantity of electric charge in memory element
Take interference ".Single reading interference incident may will not produce enough changes with impact in electric charge content
Mistake, but the reading interference of accumulation may ultimately result in so.Read the cumulative effect of interference by wiping
Division operation resets.The particular matrix framework of nand flash memory causes more more than NOR flash memory " reading dry
Disturb ".Programming interference mistake causes, during page program, position is set to improper value.Bit-errors can be just
It is programmed that the page (page) is upper to occur, but can also occur on the different pages in block.
In US patent 5715193 (on February 3rd, 1998), Robert Norman describes one
Method, for monitoring the interference effect for memory cell block, wherein when erasing block is wiped,
Controller solves the counting of each other erasing block in code block by being added to by interference unit and will wipe block
Count resets be zero update comprise erasing block solve code block table.Norman also indicates that, controller is
Good each erasing block that interference counting reaches predetermined maximum carries out refresh operation.In the refresh operation phase
Between, carry out the recovery process of any necessity, suitable electric charge to be reset into each unit of erasing block
Floating boom, thus prevent otherwise will in the case of not performing refresh operation (due to interference effect) send out
Any mistake of raw data reads.
Multilevel-cell (MLC) flush memory device can by the floating boom of transistor is charged to different selected by
Threshold voltage (VT) level to store multiple positions, thus by bit pattern (bit for each memory element
The analog feature of unit is used when pattern) being mapped to specific voltage level.Situation at nand flash memory
Under, the V of MLC deviceTConceptually by sequentially by selected read voltage (VREAD) level
It is applied to the floating boom of each unit and is read.Usually, choosing is brought with the safety between each scope
Select voltage range, to assist in ensuring that normal VTDistribution will not be overlapping.
In NOR flash memory, each unit is parallel-connected to bit line, and this allows by being in known state
Other transistors all of series connection individually read and program each unit.Therefore, in NOR flash memory, have
The serial transistor of the memory element being just queried is the transistor being only associated with addressing function.
The disclosed U.S. Patent application 20080307270 (on December 11st, 2008) of Tieniu Li is retouched
State the mechanism for detecting the most emerging bad block that host apparatus is implemented,
It is at least some of history of errors during including holding read operation.
The disclosed U.S. Patent application 20100214847 of Nishihara et al. describes nand flash memory system
System, it is it is said that pass through the reading electricity including comprising for storing and retrieve the correction for storage control
The parts of pressure, reduce the change reading interference characteristic of each chip chamber.Storage control is held for flash memory
Row data input/output control and data management, add error correcting code (ECC), and reading when write
Time analyze error correcting code.
Solid-state drive (SSD) is the replacement of function being typically designed as conventional hard disc drive (HDD)
Data storage device, but SSD use solid-state memory storage data.Term SSD the most only uses
In referring to device based on flash memory.SSD generally uses the command interface identical with hard disk drive to allow
SSD is used to replace HDD and do not require software correction in numerous applications.Special including HDD and SSD
The hybrid device levying the two is also possible.
Assuming that the deterioration of memory content is progressive with the quantity in program/erase cycle and not over time
Evitable, there is exploitation and can utilize the basic physical process of flash chip and effectively entangling of details of operation
The demand of error code.These effective error correcting codes need to utilize and are reading time retrievable Soft Inform ation, and not
Deteriorate flash memory and read performance.Invention described below relates to the early stage deterioration detection of commonly referred to as flash memory
(EDD) invention in other application described in the related applications above part of system.The present invention is permissible
Independent, or EDD system can be supplemented, to increase reliability and the operation lifetime of flash memory further.
Summary of the invention
Embodiments of the present invention include use based on system for electric charge interference operation sensitivity and by
The flush memory device (e.g., solid-state drive (SSD)) of the probability of the history of the electric charge interference operation that system performs
Method with data management.In embodiments of the present invention, for electric charge interference operation sensitivity with
Interference strength matrix is implemented, and the operation selected in it has the numerical value being associated, and it may be led for causing
The estimation of the relative intensity of this operation of the interference in the electric charge of cause error in data.Interference strength matrix is also
Can include indicating increasing or the wrong direction (direction) of loss of electric charge.At an embodiment
In, interference strength matrix is determined by the device carrying out self-test, is wherein triggered by execution institute selection operation
, until there is the mistake that can detect that in electric charge interference mistake.Electric charge can be caused potentially to disturb
All operations can include in testing.In embodiments of the present invention, the interference strength of operation will
The interference (position change) that can detect that caused by the change in the electric charge content producing flash cell is required
Operation amount determine.Operation amount needed for causing mistake is the highest, then interference strength is the lowest.
In alternative embodiment, determine interference by testing the selected unit from community of interest
Intensity matrix.The use of relatively small selected sample device group allows test to be destructive, i.e. includes holding
Row shortens or exhausts the operation in device service life.
In alternative embodiment, by the drift of deadline (TTC) value in counting read operation
(dispersion) operation amount that can perform before occurring the change that can detect that in estimates that interference is strong
Degree.TTC value is used as the threshold voltage (V in this read operation in the memory element of inquiryT) generation of drift
Reason.
Interference strength test should perform (for each device as a part for manufacturing process in factory
Or selected sample), then interference strength matrix will act as according to data management in each device of the present invention
A part for system.Interference strength matrix is previously in the fortune of the electric charge interference operation performed in SSD system
Row historical record (operation history) is used in combination, to determine when to perform prevention action to prevent data from damaging
Lose.The data dot values that interference strength matrix and operation history can also be used to distribute from memorizer reading is
The probability of the electric charge interference of result accumulation.Data dot values has disturbed enough in specific direction
Knowing of high probability allows to perform in real time error correction, as a part for the normal read operation of SSD.
Accompanying drawing explanation
Fig. 1 is the diagram of prior art nand flash memory multilayered memory cellular construction.
Fig. 2 A is the institute of the read operation of the prior art nand flash memory multilayered memory cellular construction of Fig. 1
Select the diagram of timing curve.
Fig. 2 B shows the timing curve of one group of prior art nand flash memory cell structure of Fig. 1
The diagram of the selected timing curve of the read operation of this group of possible range.
Fig. 3 is that the NAND with deterioration detection (EDD) in early days used in embodiment of the present invention dodges
Deposit the diagram of selected assembly in the page.
Fig. 4 is the selected merit of the deadline measuring unit of the nand flash memory embodiment according to the present invention
The diagram of energy design block.
Fig. 5 is the selected function design of the shift analysis device of the nand flash memory embodiment according to the present invention
The diagram of block.
Fig. 6 is the setting of maximum voltage detector used in the shift analysis device according to embodiment of the present invention
The diagram of meter.
Fig. 7 A and 7B diagram has the prior art multilayer for the parallel sense amplifier group quickly read
NOR flash memory.Fig. 7 A is conceptual diagram, and Fig. 7 B shows have current mirror and several parallel
The improvement project of sense amplifier (each having the reference voltage of himself, simultaneously switching).
Fig. 8 is the diagram of the selected assembly in the NOR flash memory system used in embodiments of the present invention.
Fig. 9 is the selected merit of the deadline measuring unit of the NOR flash memory embodiment according to the present invention
The diagram of energy design block.
Figure 10 is the design of the multiplexer (MUX) used in NOR flash memory embodiment of the present invention
Diagram.
Figure 11 be illustrate according to embodiment of the present invention for by force mistake determine one group of flash memory
The flow chart of the method for the interference strength of operation.
Figure 12 be illustrate according to embodiment of the present invention for by use shift analysis determine one group of sudden strain of a muscle
Deposit the flow chart of the method for the interference strength of operation.
The distribution of the readout of Figure 13 A diagram flash memory.
Figure 13 B diagram is according to the distribution of the readout of the flash memory illustrating mistake bar of embodiment of the present invention.
Figure 14 is to illustrate the block diagram according to the selected assembly in the SSD of embodiment of the present invention.
Detailed description of the invention
Figure 14 is to illustrate the block diagram according to the selected assembly in the SSD 130 of embodiment of the present invention.Its
It is only used as diagram to provide.It will be understood by those skilled in the art that, can be in the feelings of the spirit without departing from the present invention
Under condition, some functions described are re-allocated to main frame.SSD includes communication interface 131, and it processes SSD
With two communications between host apparatus (e.g., computer 120).SSD includes Data Management Unit 133,
Its management to and from the flowing of data of array control unit 139, array control unit 139 then controls to
Flowing from the data of flash array 141 (it can be NAND or NOR-type device).This implements
Data Management Unit 133 in mode stores non-volatile the depositing that be associated of firmware program by including having
The standard microprocessor (not shown) of reservoir.Firmware program is performed by microprocessor, to realize describing below
Data management process step.Data Management Unit 133 is used together interference with running operation history 137
Intensity matrix 135 (describing below), to determine when to perform prevention data management activity.In various enforcements
In mode, each of flash array 141 execution is significantly operated by Data Management Unit 133 by record
Maintain operation history 137.In some embodiments, provide interference strong to Data Management Unit 133
Degree matrix 135 is as read-only data, and this is owing to the sample device selected to other performs interference strength
Test.But, in some embodiments, Data Management Unit 133 creates by running self-test
Interference strength matrix 135.
The present invention includes the embodiment using nand flash memory array 141 and uses NOR flash memory array
The embodiment of 141.NAND and NOR sudden strain of a muscle that embodiments of the present invention include is described below
Deposit (it includes that the early stage according to related invention deteriorates detection (EDD) system).
There is the nand flash memory embodiment deteriorating detection in early days
Fig. 1 illustrates and can be applicable to single and multilayered memory cellular construction 20 prior art NAND
Flash memory.Note that there is any effective programming VTOther memory element of level and the NAND being just queried
Flash cell is placed in series.(noting, be not such situation for NOR flash memory).Will be with NAND
Structurized dividing elements is to have the cell array (a) of the transistor being shown as left-hand column and as the right hand
The two cell array of the cell array (b) of row.Cellular construction 20 includes verifying (BV) electricity by turn
Road 21a, 21b, it is connected to each of two bit lines BLai, BLbi.Two bit lines and BV circuit
Share public read-write (R/W) circuit similar with the open bit line framework of DRAM.R/W circuit is being read
Extract operation is used as flop difference sense amplifier 22, in programmed written operates, is used as data latches
Circuit.
By selected time point t1, t2 and t3, the selected timing curve of the read operation of the structure of Fig. 1 is shown
Go out in fig. 2.To put it more simply, the reading circuit of Perfect Matchings is assumed in all sequential charts and discussion, use
The parallel reading of all unit in the page.Not mating in these circuit can be by simply calibrating
Journey illustrates.Such as, the benchmark using the memory element with specific group of contents known reads can be
Memory array is not mated in order to Correction Sensitive amplifier in the reading after a while of unit.
Sense amplifier 22 (it is comparator) generally uses regenerative loop (regenerative loop)
Input line after transmission gate in Fig. 1 and bit line BLai and BLbi little is separated develop into fully developed after
Output-voltage levels.Circuit in Fig. 1 and the curve in Fig. 2 A suitably represent nand flash memory and read
Go out.Fig. 2 B be one group of prior art nand flash memory cell structure of Fig. 1, for 1.8v read
The diagram of the selected portion after the t3 of BLai " 1 ", it illustrates typical timing curve 26, and
The example of the possible range of the timing curve of the one group of unit defined by line 25,27.The BLbi of one group of unit
Signal will illustrate similar timing curve distribution.Embodiments of the present invention are by measuring or estimating this group list
The deadline (TTC) of unit detects the change of the drift in the performance of page unit.The rising of curve
The drift in part moment is by the difference of deadline (TTC) of becoming read operation.It should be noted that to dodge
Deposit the normal drift that reading circuit generally comprises to guarantee in timing performance and never produce the spy of readout error
Levy, i.e. circuit " is forced (sandbag) ".Therefore, the present invention is to disclose those skilled in the art not
The aspect of the flash memory recognized also uses this disclosure of this phenomenon in new opplication.
Nand flash memory framework causes according to content status different in unselected memory element for institute
Menu unit presents the resistance of different series.Therefore, inquire about nand flash memory cell content, and in order
It is compared from different reference levels by step, wherein inquires about VTVarying level.
Reading one page memory element in nand flash memory concurrently, it required by suitable lock in time
Signal starts read operation.Equilibrium is used for all sense amplifiers of each bar line of the page by clock signal,
But higher and more weak unit will differently drive sense amplifier line (after equalization), therefore, for
Higher and more weak unit, from trigger latch to sense amplifier the output complete voltage of formation time
Between (that is, TTC) would is that different.According to the present invention it is possible to measure in a suitable form and store
These differences in deadline (TTC), analyze further for system.
Owing to all memory element in nand flash memory matrix are identical on paper, and each
It is programmed into threshold voltage VT, it is at the V to program immediately preceding itTOn specific voltage level
(VREAD) inquiry time produce the current level that limits in advance, then:
I the drift in () TTC will be the V of the unit being just readTIn the agency (proxy) of drift；
(ii) when the life-span of flash memory pages starts, the drift value in TTC can save as reference value, and
It is compared to determine when memory element deteriorates beyond ensureing that data are protected with the drift being measured later when reading
Protect the limit of action；And
(iii) from each unit, read operation knows that the drift TTC can be in order to divide by Soft Inform ation
Each memory cell content determined of dispensing.
Fig. 3 shows that the early stage having according to embodiment of the present invention deteriorates detection (EDD) system
The selected function block of the nand flash memory page 60.Controller 30 includes time base 31, sequentially VTInquiry
Control 33 and decoder 35, they are designed according to prior art, will not describe in detail.The most true
Determine the V of memory elementT, decoder 35 exports the corresponding binary code of memory cell content.Sequentially VT
It is to be sequentially searched correct V in selected memory element that inquiry controls 33TNand flash memory in use
Abstract (abstraction) of circuit.Time base 31 produces necessary time signal for transmission gate, and
It is latched in sense amplifier, and also timing deadline (TTC) measuring unit 32.
Deadline (TTC) measuring unit 32 is measured and is driven by the memory element in memory cell structure 20
Dynamic bit line output reaches the time needed for its end value.Controller 30 and memory cell structure 20 are formed
There is drift and measure the unit being referred to as storage organization of (MSDM) unit 40.The page of memorizer will
Require to be connected in parallel to multiple MSDM (MSDM_1...MSDM_n) of shift analysis device 50.Business
With in flash memory, memory cell structure is actually implemented having the storage array of shared circuit, without deviating from
The spirit of this description.Thus the simplification that Fig. 3 is constructed to illustrate the design of the present invention describes, and it is only
The purpose of diagram and provide, and be not intended to the present invention.
In order reading processes, when being in from the input reference of mute (dummy) bit line (BLbi)
The V of the memory element (i.e., being just queried) under read operationTSpirit time above, in memory cell structure
Quick amplifier will only be in developing on specific direction exporting completely.Therefore, reconciliation will be determined in binary form
The content of the selected memory element of code.Additionally, in this moment, measured by deadline measuring unit 32
The time that is appropriately completed (TTC) gone out will be reported shift analysis device 50 by TTC reporter 34.TTC
Reporter 34 can include being adapted to the information of deadline is correctly sent to the slow of shift analysis device
Rush device and signal.
Fig. 4 shows the diagram of the embodiment of deadline measuring unit 32.This embodiment is similar to
The charge pump circuit used in the phase detector circuit of phaselocked loop (PLL) system.Illustrative at this
In realization, but it not with any limited form, finishing time information is stored in TTC measuring unit 32
Internal capacitor COUTIn electric charge in 73.Voltage on capacitor is proportional to allow from current source I1
Electric current via switch S1 flow into capacitor time.The switching of S1 is controlled by trigger 72, described tactile
Send out device 72 origin autodyne and assign to the output reset of single-ended converter 71.Differential-to-single-ended converter 71 uses
Two binary system output conduct inputs from memory cell structure.Determining the V of memory elementTAfterwards,
The correct deadline is reported to shift analysis device (DA).Based on the signal from time base, electric capacity
Device 73 is via switch S2 and current source I2 excretion.
Fig. 5 is the diagram of the selected function design block of the shift analysis device 50 according to embodiment of the present invention.
Shift analysis device 50 is analog signal processing block.In this embodiment, its function includes reading from the page
The group of the TTC measuring unit 32 of operation determines the minimum and maximum deadline.Each TTC measures single
Unit 32 output is through TTC reporter 34 and the analog voltage level that is transferred to shift analysis device 50
(TTCM_out).Min/Max detector 51 in shift analysis device determines from TTC reporter
The maximum voltage of its multiple inputs and minimum voltage.By the difference (delta) between total maximum and minimum value
It is defined as the measurement of the drift of the page by subtractor 52.Shift analysis device uses comparator 54 really
Whether the delta that devise a stratagem calculates is more than reference value 53, and correspondingly arranges caution signals.Reference value is pre-
The threshold value first determined or the initial value set up when the life-span of nand flash memory starts.In embodiments,
When the operation of nand flash memory chip starts within the storage system, after program command, issue and read life
Order is to set up reference value, for comparing V when read operation each timeTIn following drift.Therefore, logical
Cross and calculate the initial delta between total maximum and minimum value so that shift analysis device and to preserve this initial
Reference value, as reference value, can be set to a part for manufacturing process by delta.
Fig. 6 is to use in the Min/Max detector 51 shift analysis device according to embodiment of the present invention
The diagram of the design of maximum voltage detector 51A.In fig. 6 it is shown that it is true for maximum input voltage
The example of fixed cmos circuit.It is " big winner (winner-takes-all) " circuit.This circuit
The precision that maximum input voltage differs from is followed in output to the 1mV between each incoming level.Input number in circuit
Amount directly can be increased by the duplication of circuit, or two input circuits can be arranged to hierarchical tree.
In order to follow minimum input voltage, use the insertion circuit (inset circuit) from NMOS to PMOS
In suitable change.
Deteriorating detecting system in early days can be in order to the content assignment mistake read out from each memory element
Probability or correct confidence level.By utilizing the information measured about the deadline (TTC) to read
V about each unitTThe information of position can be in order to correct confidence level be distributed to from each list
The data that unit reads.This allows new and more effectively coding and error correction algorithm to be used in nand flash memory chip
On, in the ideal distribution of each cell data that described nand flash memory chip reads equipped with notice
VTThis ability of position.Required single reading.
There is the NOR flash memory embodiment deteriorating detection in early days
Prior art NOR Flash cell and each sense amplifier such as Fig. 7 A in rough schematic view with
Arrange to emphasize basic operation as 7B instruction.Recall only column decoder transistors and NOR flash memory list
Unit and sensing circuit are placed in series.Therefore, NOR Flash cell (single layer cell (SLC) or multilamellar list
Unit (MLC)) reading can complete concurrently as in analog-digital converter circuit, and look into single
Inquiry determines the V of programming in each unitT(it is different from nand flash memory situation, and wherein order is looked into
Inquiry is necessary).Comparator COMP1-3 generally use regeneration ring by input line (bit line MAT1-3,
REF1-3) little separation develops into fully developed output-voltage levels.Circuit and timing performance are suitably
Represent single layer cell (SLC) and multilevel-cell (MLC) reads the two.
Prior art multilayer (MLC) flash memory circuit of Fig. 7 A and 7B is modified to include suitable benchmark
Comparator (REF1-3), as indicated.Use one group of sense amplifier 97,98 (COMP1-3)
Parallel, operate simultaneously, this be due to as mentioned by as, only column decoder transistors and NOR flash memory
In the memory element series connection that is just being read, and suitable reference voltage can be defined, be used for determining reading behaviour
The threshold voltage of the memory element under Zuoing.
The early stage of the NOR flash memory according to the present invention deteriorates the principle of detecting system can be as follows by observing
Some illustrates:
1) read several memory element due to parallel in NOR flash memory, and this read operation is by identical
Suitably definition time signal (line of all sense amplifiers related in its equilibrium read operation, and
And trigger sensing) initiate, the most higher and more weak unit will differently separate sense amplifier line (all
After weighing apparatus), and from triggering time (this sensing the complete voltage development at the output of sense amplifier
It is referred to as " deadline " (TTC)) would is that different for higher and more weak unit.
2) it is identical on paper due to all memory cells in NOR flash memory matrix, and often
One is programmed into threshold voltage VT, it is at the V to program immediately preceding itTOn specific voltage level
Predetermined current level is produced during inquiry, then:
I the time drift in the TTC limited in () such as (1) will be the V of the unit being just readTIn
The agency of drift；
(ii) drift value that can preserve when service life of flash memory starts in TTC, and by its with read after a while
Drift in TTC is compared, and ensures data protection action determining when that memory element has deteriorated to exceed
Limit.The selected value of drift reference value can also replace the measured value of reality and be used；And
(iii) in read operation, knowing of the drift in the TTC of all unit may be used for dividing Soft Inform ation
Each memory cell content determined of dispensing.
Fig. 8 diagram has the NOR flash memory 80 of the early stage deterioration detecting system according to embodiment of the present invention
In selected assembly.The shift analysis device 50 of the NOR embodiment of the present invention is functionally similar to this
The shift analysis device of the NAND embodiment of invention, but be discussed further below, input would is that different.
Shift analysis device 50 receive from multiple (1 ... the n) input of TTC measuring unit 120, its be shown as produce
Raw MUX_OUT...MUXn_OUT signal.4 layers of NOR flash memory are assumed for this embodiment, but
It it not restrictive condition.Under input reference is in read operation, (MAT1-3) is in the V of memory elementTOn
Time, sense amplifier 98 only outputs it (OUT1-3) and develops into positive rail (rail) completely.Cause
This, three deadline (TTC1-3) unit 32A-C are by the finite value of development deadline, i.e. at it
The finite value of the voltage of output, is only used for VREADAt VTAbove those compare.Other TTC unit
Block output it saturated for complete path voltage.
(it exports the storage of binary format to prior art Thermometer-decoder (TD) 25 in this illustration
The content of unit) additionally provide the screening signal (screening for analog multiplexer (MUX) 23
Signal), for representing the voltage of the deadline of the memory cell content of shift analysis device 50 to be sent to
Suitable selection.If all unit (or subset of all unit) read in read operation is complete
The drift of the value in the one-tenth time (TTC) is more than predetermined value, then shift analysis device 50 is reported to the police arranging deterioration
Signal.
Figure 10 is the diagram of the design of the multiplexer (MUX) 23 of embodiment of the present invention.MUX
The input of 23 be output from each TTC unit 32A-C (TTC1_OUT33A,
TTC2_OUT33B、TTC3_OUT33C).MUX selects one of these inputs to continue to be delivered to drift
Move analyzer as MUX1_OUT signal.MUX 23 can conceptually be described as the mould of transmission gate
Matroid arranges.But several different realizations are possible, for adjusting electricity with suitable buffer and signal
Road (signal conditioning circuit) is by the electricity of the output from one of three TTS unit 32A-C
Voltage level is sent to the function of the input of shift analysis device 50.
In the embodiment of NOR flash memory reading circuit, by the signal of the memory element from inquiry also
Row ground with benchmark replicate voltage (REF1-3) compare, described benchmark replicate voltage (REF1-3) and
The different content charge level that the memory element of inquiry can keep is corresponding.According to design alternative, from this
Some outputs of comparator COMP1-3 in diagram will be in present worth ' 0 ', and some present surplus value ' 1 ',
Wherein ' 0 ' and ' 1 ' will occur as in graduation of thermometer, i.e. such as at OUT2 and OUT3
Place output ' 0 ', OUT1 at export ' 1 ', or OUT3 at output ' 0 ', OUT1 with
Exporting ' 1 ' at OUT2, it is two examples that possible export.
Then this graduation of thermometer (scale) output is converted to binary coding by Thermometer-decoder 25.
In embodiments, the unit that first expression of the OUT1-3 signal of output ' 1 ' is just being queried is kept
Threshold level (VTThe first reference level more than), and its position also will be encoded as from temperature
The signal S (s0, s1) of the MUX23 to be sent to of meter decoder 25.Signal S is by Thermometer-decoder
Determining, it is used as the Thermometer-decoder that memory cell content reads in embodiments.Retouch conceptual
In stating, but not limited significance Shangdi, and which TTC1-3 signal signal S (s0, s1) selects be
The deadline to be reported (TTC) of shift analysis device is delivered to by MUX.
TTC unit 32A-C is identical.Produce the TTC1 unit 32A's of output TTC1-OUT
Illustrative embodiments illustrates in fig .9.It is similar in phaselocked loop (PLL) circuit the electric charge used
Pump circuit, the moving for correction of the PHASE SEPARATION between VCO frequency to be determined and reference frequency
Make.(SAEQ) signal will be equalized from sense amplifier and be increased to Vout(OUT1-3 respectively) raises
Time is converted to capacitor CoutOn voltage level.Additionally, use standard timing signals Address
Transition Detection (ATD, address transition detection) and ENDREAD or other similar signal.
Buffer circuits (not shown) can be used between output and the MUX circuit of TTC block.
In this embodiment, shift analysis device 50 determines the minimum and maximum deadline, as from the page
In the output signal of multiple TTC measuring units 120 of read operation as instruction.Each TTC
The analog voltage level of MUX 23 is gone in 32A-C output, described MUX 23 then select its three defeated
One of enter to continue to be sent to shift analysis device 50.Min/Max detector 51 in shift analysis device is true
The maximum voltage of fixed its multiple inputs from multiple TTC measuring units 120 and minimum voltage.Will be total
Maximum and minimum value between difference (delta) be defined as the measuring of drift of the page by subtractor 52.
The output of subtractor 52 is the drift value used in embodiment of the present invention, and this will retouch below further
State.Shift analysis device uses comparator 54 to determine whether the delta calculated is more than reference value 53, and
Alarm signal is correspondingly set.Reference value is predetermined threshold value or sets up when the life-span of flash memory starts
Initial value.In one embodiment, when the operation of flash chip starts within the storage system, compiling
After journey order, issue reading order to set up for comparing V when each read operationTIn following drift
The reference value moved.Therefore, initial by make shift analysis device calculate between total maximum and minimum value
Delta also preserves this initial delta as reference value, and reference value can be set to one of manufacturing process
Point.
By noticing that shift analysis utensil is related to the letter of the deadline from all unit being read
Breath, can develop the support of the error correcting code mechanism requiring Soft Inform ation for embodiments of the present invention.According to
The position of its initiation unit in the drift of deadline result, can distribute to suitable correct probability
Final binary result.Required single reading.
Use the probability Estimation of the error correction of interference strength & operation history
In normal operating, NOR and nand flash memory cell experience may be added or removed from floating boom
The interference of electric charge.From ieee standard 1005-1998, the table 1 below drawn in page 97 gives not
With the operation of disturbed condition and condition and they are for the impact of the electric charge in the memory element of interference.
One group of operation in table 1 is it will be assumed that be the default list of the operation with the current potential producing interference.But,
The invention is not restricted to any specific operational group.
| It is called for short | Operator scheme | Electron transport type |
| Grid is wiped | Programming | Loss |
| Gate program | Programming | Increase |
| Drain electrode erasing | Programming | Increase |
| Programming interference | Programming | Loss |
| Puncture programming | Programming | Increase |
| Anti-tunneling program | Programming | Increase |
| Source electrode is wiped | Erasing | Loss |
| Ditch track erasure | Erasing | Loss |
| Grid reads erasing | Read | Loss |
| Raceway groove reads programming | Read | Increase |
| Soft programming | Read | Increase |
Table 1
By forcing mistake to measure interference strength
Implement the method for the present invention and measure one group of operation (those whole or in e.g., listed table 1
Part) average relative interference strength.Interference strength should be defined as a part for manufacturing process.Dry
Disturb intensity to be determined by self-test by device, as will be described below, but can also be
Testing results in representational sample device, then using interference strength matrix as of read only memory
Divide and generator is provided to.Assume that the flash chip used in specific device is from using identical chips framework
And device technique and the given manufacturer of technique, different operations is shown substantially similar flat
All relative to interference strength.It is possible that the average relative intensity of disturbance is from different manufacturers
Being fully difference in chip, to allow client to determine, the product of which flash chip manufacturer is for institute
Choosing application is the most competent part.
The embodiment of test and characterization method will be discussed by means of the flow chart in Figure 11.Flash memory core
Sheet should be wiped completely, is placed in state consistent, known the most before testing begins.In order to mesh is described
, Figure 11 shows the task of the average relative interference strength of characterization disturbance operation in flash chip
The example of flow chart.Method by from can electric charge disturbed one 1 operation complete list select operation
And start.
Although method can use any operation in list, but read operation has some advantages, this
Be due to, in addition to other reason, the quantity of the read operation for performing does not has inherent limitations.
The restriction of number of executions for certain operations is discussed further below.Additionally, be different from certain operations,
Reading can be performed in the case of not being sequentially performed other operation.Such as, programming is it is generally required to before
Erasing operation, this is completed by block.
Certain operations (such as erasing or read operation) may not have any data bit pattern being associated,
But such as programming operation can have the bit pattern of the corresponding group of application in the internal model ring of method.
Pattern can be standard memory bit pattern (e.g., AAh or 55h) or other suitable pattern any.
Can consider that memory element more or less may be interfered according to the electric charge occurred in consecutive storage unit
The selection of the proper data pattern of impact.In order to check this, system may need to program unit
To such as ' 1 ', its adjacent cells is programmed for ' 0 ' simultaneously, and checks the sensitivity for interference.
It follows that another content is programmed in selected unit, different content is programmed in adjacent cells simultaneously.
When carrying out interference strength self-test, multiple pattern can be applied, but last in final interference strength
In matrix, single value should be there is for each operation.Although can be with many significant modes (bag
Include average) use the group of MODE NUMBER, but selection is caused the most strongly disturbing pattern by conservative way
Numbering.Target is intended to the robust system with imminent problem of reporting to the police, in order to can take to remedy
Action.
Perform once selected operation and selected (first or next) pattern (if any),
To produce initial baseline (baseline) result 12.Read and preserve the memorizer produced from step 12
Initial content is for comparison 13 subsequently.If any, memorizer is then by using present mode
Perform relative high number institute's selection operation and by stress (stressed), 14.It is selected that counting has performed
The total degree 14 of operation.Again read off the content 15 of memorizer.Current Content is compared with initial content,
To check whether to have forced mistake 16.If Current Content is still identical with initial content, then logical
Cross and loop back step 14 and perform more multioperation.Finally, mistake will be caused, and method will proceed to step
17, the operation sum that its record performs before an error is detected.Due to each time operation after unlike
Relatively/test memory content, therefore resolution is limited by the operation amount performed between each reading/test.
The also direction 17 of misregistration (increase of electric charge or loss).Result at this point is used for institute's selection operation,
And be probably a pattern, have selected the most now any additional mode of institute's selection operation, and again
Perform internal model ring 18.When having been carried out during all patterns of selection operation, if deposited in lists
In more multioperation, the most again perform external rings 19.
Once already tested with all operations, the data of record are the interference strengths operated for each
Matrix 19a.If for single operation already tested with multiple patterns, then in matrix the value of record will be from
The single numbering selecting or calculating in MODE NUMBER group as discussed above.Relatively being given of record number is every
The relative interference strength of one operation.For a kind of possible purposes of this data matrix be as
The instrument made a distinction between mentioned flash memory fabrication business.
In the case of positive test sample and destructive test are to allow, the optional embodiment of method is
Determine along with the interference strength change in memorizer experience erasing-programming cycle is prepared.At this embodiment
In, repeatedly all to determine as erasing-programming in erasing programming cycle and the whole process of selected quantity
After the interference strength change of the function of issue amount, re-execute the method shown in Figure 11.Then will divide
Analysis interference strength change, to draw useful algorithm or one group of matrix, it can be implemented in generator
So that change when interference strength matrix tracks memorizer experiences the erasing-programming cycle over time.As
Example, it can be deduced that can be in order to adjust interference strength when erasing-programming amount of cycles increases over time
The equation of matrix.
When determining can enter in the case of shortening life-span of chip indistinctively or reaching end-of-life limit
Need to consider some factors during the operation amount gone.For any specific flash chip, manufacturer will refer to
The upper limit of some operation fixed.When design and fabrication technology develops over time, it may be desirable that absolute number quantitative change
Change.Such as, specific flash memory chip can be designated as bearing the hundreds of erasing-programming cycle.Therefore,
The particular bound of actual chips just to use must select the behaviour that can perform in interference strength is tested
Make quantity, unless destructive testing is to allow.For wanting to use after running interference strength test
Device, operation amount should be the least compared to specified limit.Alternative embodiment can be to a collection of
The selected sample of flash chip performs disturbed test, and is extended down to outward the behavior of other chip in this batch.Can
Can, test from generation chip (it all has the same design from manufacturer and manufacturing technology)
Sample may be sufficient to.When sample is in order to determine interference strength, it will thus provide interference strength matrix is made
For the read-only data in the program storage of generation data storage device.
Note, be always used together from its all product with phase the same generation element of manufacturer
In the case of group sample defines the matrix of relative interference strength, the process flow described in Figure 11 can be followed
Limit to flash chip probable life.It would is that destructive feature for the sample used.Except
Outside the erasing-programming cycle version of the process used in device self-test is more limited, it is possible to use this
Plant destructive process.
Interference strength is estimated in the change using drift
Memory element enhanced charge will increase the V in this memory elementTVoltage.On equidirectional gradually
Enter interference and will move VTBeyond threshold limit, and it is read as comprising and V by this unitTRecordable electricity
The data that in Ping, next level higher is corresponding.Conversely, because the electric charge of interference incident loss will reduce
VTProgressive interference on voltage, and equidirectional will finally make VTMove to VTRecordable level
Next level lower in scope.
In a word, can be at the relative intensity not forming interference in the case of flash chip adds additional circuit
Matrix.Interference strength relatively is measured with the quantity of interference incident, to change the V of object elementT
Voltage is beyond the V of its protocolTThe threshold value of value above and below.
It is apparent, however, that once the additional circuit of EDD based on TTC drift is available, then
Compared to being previously described in the application, can be with lesser amount of interference incident and therefore with low cost
The matrix of the relative intensity of interference is constructed with the shorter time.
Noting, EDD additional circuit not only provides about all group memory element of inquiry in reading at the page
The information of total drift, the V of each memory element in also providing for reading about the pageTRelative position
Information.Therefore, the matrix of the relative intensity of interference can construct based on the quantity of interference, gives with impact
Determine the unit V of memory elementTDetected displacement in position, or more accurately, give order relative to this
Given change in the TTC block of unit.
In the embodiment that will describe in this section, as retouched for NAND or NOR flash memory before
As stating, system includes the EDD system with drift distribution estimating.As in embodiment before,
Interference strength should be defined as a part for manufacturing process.Use in this embodiment from shift analysis
The drift value signal (illustrating in Figure 5) of device 50.Use V the most in this wayTReplacing of distribution
In generation, is measured.Drift value is the mould of the delta between the minimum and maximum deadline value representing locked memory pages
Intend signal.Move to the time before next page, the single page can be performed the method, or
Each step can be performed for all pages.In embodiments, test and characterization method will be by complete
Entirely wipe flash chip and start.Figure 12 shows the flow chart of the embodiment in order to describe method.
From can electric charge interference operation list select operation 11C.Select bit pattern and be written into storage
Device 12C.Perform read operation, and preserve initial drift value 13C that shift analysis device produces.Repeat
Institute's selection operation relatively great amount of number of times 14C.Current drift value is remeasured by performing read operation
15C.Then current drift value and initial drift value are compared 16C.If two values are equal (in public affairs
In difference), then method loops back step 14C to perform another batch operation and to remeasure drift value.One
The current drift value of denier is not equal to initial drift value, then the performed given change caused in drift value
Interference strength 17C that count recording is institute's selection operation of operation.If for this operation exist any other
Desired pattern, then method loops back step 12C with for next pattern retest 18C.Once
All mode already tested with institute's selection operation, then in the case of method exists more multioperation in lists
Loop back step 11C.
The matrix 20C of the relative interference strength then operated with this group of above surveying record.If for list
Individual operation is already tested with multiple patterns, then as it has been described above, single value will be recorded with matrix.Just testing
In the case of sample and permission destructive testing, as the method for Figure 11 as above, Tu12Zhong
Shown method can re-execute after the erasing programming cycle of selected quantity, to determine as erasing
The change of the interference strength of the function of programming cycle quantity.
The allocation probability of data management action
SSD system 130 according to embodiment of the present invention has data management system 133, and it uses dry
Disturb intensity matrix 135 and operation history 137 determines when perform prevention action and (e.g., refreshes or mobile
Data).As mentioned above, it is assumed that it is relative that the interference from the selected memory chip of given manufacturer operates
Intensity can be as all elements from same manufacturer, (it uses identical chip architecture and skill
Art and manufacturing process) the representative of relative intensity of interference operation.Therefore, according to this embodiment
System in:
I () maintains the operation operating (program-write, wipe, read) before performed on flash chip
History, i.e. operation history 137；
(ii) disturbance operation average relative interference strength and increase-loss direction at interference strength square
Battle array 135 in known；And
(iii) cumulative effect for the electric charge of all interference operations actually performed can use interference
Intensity and increase-loss direction and estimate.Increase by the electric charge of net output (net out) various operations
And loss.
Figure 13 A diagram is by the readout of the multilamellar flash chip in order to embodiments of the present invention to be described
(VT) distribution.In figure 13a, various data points have the correct probability that is associated, and are the most not yet subject to
Disturbing to initial program value, it can use the technology of the present invention to estimate.In this example, distribution 1-3
Shown in data point all in the original tolerance interval allowing target programmed value of MLC, therefore its
It is to be interpreted as being corrected by prior art systems.But, owing to electric charge increases or loss, data point
Can be moved to another from a distribution.The read operation of prior art flash chip can recover such as
Data at data point 121,122 are as being distributed in 2, but may be distributed 1 or 3 Central Plains
It is programmed these data points with beginning.
The relative interference strength operated with these by the execution history using interference operation, can be by probability
Distribute to include the correctness of the arbitrary data point value of 121,122.Therefore, by using according to the present invention
Method, to data dot values 121 distribution be probably be programmed into before distribution 1 in possible state in the lump
And by reaching the resultant interference state of the memory element of its end-state from interference operation increase electric charge
Probability.Similarly, by the impact of the operation of loss of charge may be caused, the initially number in distribution 3
Strong point can move to lower value and fall in distribution 2, such as data point 122.The increase of electric charge or damage
The direction lost and value are the interference strength of specific operation, increase-loss direction and the actual operation performed
The function of cumulative effect.
It should be noted that the electric charge on Destination Storage Unit is removed in erasing operation, but this does not require the behaviour that resets
The history made.Erasing operation is added to historical record, and by the interference incident in order to update this flash memory
Cumulative effect.Noting, for the erasing cycle, the relative intensity of interference may change.
In one embodiment, the history of interference operation can be fixed as in the sum of interference operation each
The percentage ratio of individual interference operation.This will cause those interference operations for the amount of charge in floating gate
The weighted sum of the relative intensity of the cleanest interference effect.This history of interference operation can by the page of chip or
Sector (sector) record, and can also adjust with the possibility of reflection chip when each interference operation
Different content.
Interference strength matrix and operation history can use in many ways, to make about prevention action
Determine to prevent data degradation.A kind of way uses conservative decision to force the refreshing of data in flash chip
Or it is mobile.Such as, testing from interference strength, data management system may such as have been observed that given (non-
Often sensitive) 1,000,000 read operations on unit produce position interference in the memory content read.Root
An embodiment according to assembly of the invention then can be at its unit after 1,000,000 read operations
Any one in ask or perform Refresh Data.Alternately, replacing forcing to refresh, probability can be
The unit just reading (after 1,000,000 read operations) is likely to be at the selected probability of wrong distribution.
Can transmit this information to should be assigned to the mistake of agency of this reading data confidence level really as it
Error detection and error correction unit.Then request under the control of error detector and error correction unit is refreshed.
In a word, as shown in Figure 13 B, history and the erasing cycle of interference may be used for producing reading data
The estimation of upper mistake bar.The TTC information of discrete cell estimates the V of this unit in its distributionTPosition.
By adding two information, error probability can be distributed to any number read out from flash memory by management system
According to.
Although illustrate and describing the present invention with reference to particular implementation, but the present invention being only by institute
Restriction in the scope specified in attached claim.
Claims (19)
1. a method for operating flash memory system, including:
The operation operation history of the selected electric charge interference operation that record had previously performed on flash memory system；And
By using operation history, the relative interference strength value and each of electric charge interference operation selected by each
The electric charge of individual selected electric charge interference operation increase-lose direction come calculating storaging unit electric charge net increase or
The estimation of loss；
The interference that can detect that wherein caused by the change in the electric charge content producing memory element needs
The quantity of selected interference operation determines described relative interference strength value.
2. the method for claim 1, farther includes: uses to comprise and experiences about memory element
The electric charge net increase of memory element of information of history of erasing-programming cycle or the estimation of loss, estimate
The probability of the error in data that meter reads out from memory element.
3. the method for claim 1, farther includes: when memory element electric charge net increase or
When being estimated to exceed predetermined threshold of loss, performs prevention action to prevent data degradation.
4. the method for claim 1, farther includes:
One group of memory element is initialized as selected state；
This group memory element is repeatedly carried out selected while periodically reading this group memory element
Electric charge interference operation, until detecting the state change of this group memory element；
It is secondary that the selected electric charge interference performed before changing based on the state this group memory element being detected operates
Number, determines the relative interference strength value of selected electric charge interference operation；And
Relative interference strength value and the electric charge of record selected electric charge interference operation increase-lose direction, Qi Zhong electricity
Lotus increases-loses direction and indicates the state change of this group memory element to be electric charge increase or lose.
5. method as claimed in claim 4, wherein, performs selected electric charge interference operation and farther includes
Binding operation uses selected data bit pattern.
6. method as claimed in claim 4, farther includes: in many group electric charge interference operations
Each repeats to initialize, perform, determine and record relative interference strength value and electric charge increases-lose direction
Step.
7. method as claimed in claim 6, farther includes to store the interference operation of this group electric charge with matrix
Relative interference strength value and electric charge increase-lose direction.
The most the method for claim 1, wherein the electric charge net increase of calculating storaging unit or loss
Estimation farther include:
Calculate the percentage ratio of each electric charge interference operation in operation history；And
The weighted sum of the relative interference strength value of calculated charge interference operation.
The most the method for claim 1, wherein relative by electric charge interference operation selected by each
Interference strength value and the electric charge of electric charge interference operation selected by each increase-lose direction and provide described
System, as the tentation data determined by test sample device.
10. a flash memory system, including:
One group of flash cell；
Interference strength matrix, its relative interference strength value comprising electric charge interference operation selected by each and electricity
Lotus increases-loses direction；
Operation history, it is the log of the selected electric charge interference operation that described system performs；And
Data Management Unit, it is used together interference strength matrix together with operation history, to calculate flash memory list
The electric charge net increase of unit or the estimation of loss；
The interference that can detect that wherein caused by the change in the electric charge content producing flash cell needs
The quantity of selected interference operation determines relative interference strength value.
11. flash memory systems as claimed in claim 10, wherein, the instruction of described relative interference strength value exists
The number of times of the selected electric charge interference operation performed before the state change of flash cell detected.
12. flash memory systems as claimed in claim 10, wherein, interference strength matrix is entered by described system
The self-test of row determines.
13. flash memory systems as claimed in claim 10, wherein, Data Management Unit includes for using
The error in data that the electric charge net increase of flash cell or the estimation of loss are estimated to read out from flash cell
The parts of probability.
14. flash memory systems as claimed in claim 10, wherein, Data Management Unit includes for when dodging
The electric charge net increase of memory cell or execution prevention action when being estimated to exceed predetermined threshold of loss are to prevent data
The parts of loss.
15. flash memory systems as claimed in claim 10, wherein, Data Management Unit includes for calculating
In operation history, the percentage ratio of each electric charge interference operation the interference relatively of calculated charge interference operation are strong
The parts of the weighted sum of angle value.
16. flash memory systems as claimed in claim 10, farther include for estimating this group flash cell
The distribution of read voltage threshold value in the parts of position of read voltage threshold value of flash cell.
17. flash memory systems as claimed in claim 16, wherein, the read voltage threshold of each flash cell
Value draws from the measuring unit being connected to corresponding flash cell, and described measuring unit produces the sudden strain of a muscle from read operation
That the deadline of memory cell draws, as the measurement measured of the voltage threshold of flash cell in read operation
Signal.
18. flash memory systems as claimed in claim 16, farther include for using operation history and doing
Disturb the intensity matrix parts to the data assignment error bar read out from flash cell.
19. flash memory systems as claimed in claim 18, farther include for using mistake bar and this group
In the read voltage threshold value distribution of flash cell, the position of the read voltage threshold value of flash cell is come to from flash cell
The parts of the data assignment error probability read out.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/930,017 | 2010-12-22 | ||
| US12/930,017 US8649215B2 (en) | 2010-12-22 | 2010-12-22 | Data management in flash memory using probability of charge disturbances |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102543212A CN102543212A (en) | 2012-07-04 |
| CN102543212B true CN102543212B (en) | 2016-12-14 |
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| US6094734A (en) * | 1997-08-22 | 2000-07-25 | Micron Technology, Inc. | Test arrangement for memory devices using a dynamic row for creating test data |
| CN1411001A (en) * | 2001-09-27 | 2003-04-16 | 夏普公司 | Bit line controlling decoder circuit, semiconductor storage device and data device and data reading method thereof |
| CN101472769A (en) * | 2006-06-19 | 2009-07-01 | Iee国际电子工程股份公司 | Capacitive occupant classification system operating method |
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| US6094734A (en) * | 1997-08-22 | 2000-07-25 | Micron Technology, Inc. | Test arrangement for memory devices using a dynamic row for creating test data |
| CN1411001A (en) * | 2001-09-27 | 2003-04-16 | 夏普公司 | Bit line controlling decoder circuit, semiconductor storage device and data device and data reading method thereof |
| CN101472769A (en) * | 2006-06-19 | 2009-07-01 | Iee国际电子工程股份公司 | Capacitive occupant classification system operating method |
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