CN102540218B - Correlator for global positioning satellite navigation signal - Google Patents
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Abstract
The invention discloses a correlator for a global positioning satellite navigation signal. In order to improve the application universality of the correlator, the correlator comprises: a code numerically-controlled oscillator provides a clock signal; a first frequency divider and a second frequency divider are used for carrying out frequency division on the clock signal to obtain a first frequency division signal and a second frequency division signal; a first sequence generator generates a first local code corresponding to an in-phase code according to the first frequency division signal; a second sequence generator generates a second local code corresponding to an orthogonal code according to the second frequency division signal; a first arithmometer receives a frequency-mixed in-phase component and a frequency-mixed orthogonal component and finishes the correlation operation with the first local code to obtain a first operation result; a selector selects a local code from the delayed first local code and the delayed second local code; a second arithmometer receives the frequency-mixed in-phase component and the frequency-mixed orthogonal component and finishes the correlation operation with the local code selected by the selector to obtain a second operation result; and an output port outputs the first operation result and the second operation result. The correlator can adapt to complicate and various signal structures.
Description
Technical field
The present invention relates to global positioning satellite navigation (GNSS) technology, relate in particular to a kind of correlator of GNSS signal.
Background technology
Current, satellite navigation application has developed into global new high-tech industry.Along with the development of GNSS, the situation that the various global NAVSTAR (GNSS) such as European galileo (Galileo) system, american global positioning system (GPS), Russian GLONASS (GLONASS) system, Chinese dipper system coexist probably there will be in future.
Multiple systems coexists more safer than only using triangular web, and ground receiving equipment is inevitable to be developed to GNSS equipment from current the most frequently used GPS equipment.The variation of GNSS signal system, also has higher requirement in design and the production of aspect to receiver, equipment etc. such as modularization, universalization, cost and the power consumptions of Base-Band Processing.
Correlator is in the technology about GPS and GNSS receiver, can be used to describe the baseband chip from the simplest gate circuit to complete embedded micro-processor, also be used to be described as receiving and extracting hardware or the software of the required whole related datas of a certain definite GNSS satellite-signal generation, close to the concept of passage.
GPS-L1C/A is a CDMA (CDMA) signal.The signal that different satellites send respectively has a specific pseudo-random sequence, and length is 1023 chips, and code check is 1.023 megahertzes (MHz).These chips are modulated in two-phase PSK (BPSK) mode, and only 0 degree and two kinds of phase places of 180 degree change, and correspond respectively to 1 in sequence and-1.1 and the process that multiplies each other of-1 and 50 bits per second (bps) navigation message data make the bandwidth of signal be increased to about 2MHz by 50 hertz (Hz), be called as direct sequence spread spectrum (DS-SS).
The Main Function of correlator in GNSS signal is processed carries out despreading at receiving end to spread-spectrum signal exactly, removes frequency expansion sequence, recovers the arrowband navigation message signals of 50bps.This needs local reproduction signal synchronizes or aligns with reception signal time, thereby 1 and 1 multiplies each other, and-1 and-1 multiplies each other, and is equivalent to telegraph signal and has been multiplied by 1.
Correlator has mainly participated in following two important and relatively independent signal processings:
(1) catch; Before determining and can receiving a certain signal, must be first carry out correlation integral test at a large amount of possible code phase and Doppler shift places, utilize the result of relevant accumulation to carry out peak value searching.
(2) follow the tracks of; Once acquisition success, receiver must continue despreading input signal to obtain navigation message and to carry out pseudorange and carrier phase measurement.
For this purpose, one group of totalizer, a part is leading and another part lags behind input signal code phase, under delay-locked loop (DLL) is controlled, keep local code as far as possible closely with receive signal and synchronize.
In brief, correlator is used to detectable signal and is kept.Correlation integral/accumulation equation between input signal r (t) and local reproduction signal s (t) is as shown in expression formula (1):
Wherein, R (τ) represents output signal.
Above-mentioned expression formula has comprised important physical significance:
First,, if carrier wave and spreading code are correctly peeled off, relevant output is the autocorrelation function of signal.If track loop can keep the absolute synchronization to input signal, local signal be input as zero and differ, so just can obtain the maximal value of R (τ), that is to say the peak value place that remains on related function.
In acquisition procedure, code phase difference τ changes within the specific limits, thus the maximal value of searching out.Upper limit of integral T is calculating R (τ) whole observing time of length before.This time is longer, and the signal to noise ratio (S/N ratio) after integration is just higher, smoothed/average because signal is accumulated noise by coherent.
Fig. 1 is the structural representation that carries out the many tap correlator of serial (SequentialMulti-Tap) of fast Acquisition in prior art.The input of decision logic is the envelope of all tap correlations, and test statistics is serial tap output signal Y[n], Y[n+1], Y[n+2] ..., Y[n+R] max function.Once test statistics exceedes the thresholding definite according to certain decision rule, i.e. decision signal acquisition success, transfers track loop to the processing of this signal.Each search launches at R delay unit place simultaneously, if do not find signal (being that test statistics does not transfinite), code phase moves R delay unit and continues search.By selecting search strategy (as serrate search), reduce the impact of yard Doppler effect on mean acquisition time.
The multiple accumulator structure that is similar to SMT is also successfully applied to Radio frequency interference (RFI) and detects and suppress.Radio frequency interference (RFI) is very serious threat for GNSS aviation users, and a large amount of interference mitigation technologies are designed and develop to reduce GNSS receiver to the susceptibility disturbing.Most of this type of technology is space irrelevance, the spectral selectivity with useful signal based on interference, as adaptive antenna and trapper etc., or amplitude detection.The means that the appearance of multiple accumulator structure provides relevant rear Radio frequency interference (RFI) to detect.Multiple accumulator makes to analyze the details of relevant peaks, and extracting interference effect becomes possibility in the feature of track loop.The micropulse correlator (PAC) of NovAtel company is the Typical Representative of this respect successful Application, and this correlator can effectively suppress multipath and disturb the impact on pseudo range measurement.
Summary of the invention
Technical matters to be solved by this invention is the correlator that a kind of global positioning satellite navigation signal need to be provided, to improve the versatility of correlator application.
In order to solve the problems of the technologies described above, the invention provides a kind of correlator of global positioning satellite navigation signal, comprising:
Yardage controlled oscillator, for providing clock signal;
The first frequency divider, is connected with described yardage controlled oscillator, for described clock signal is carried out to frequency division, obtains the first fractional frequency signal;
The second frequency divider, is connected with described yardage controlled oscillator, for described clock signal is carried out to frequency division, obtains the second fractional frequency signal;
First ray generator, is connected with described the first frequency divider, for generating according to described the first fractional frequency signal the first local code adapting with homophase code;
The second sequencer, is connected with described the second frequency divider, for generating according to described the second fractional frequency signal the second local code adapting with orthogonal code;
First arithmetic device, is connected with described yardage controlled oscillator and First ray generator, for receiving in-phase component and the quadrature component after mixing, and completes related operation with described the first local code, obtains the first operation result;
Selector switch, is connected with described the second sequencer and first arithmetic device, for selecting a kind of local code from described the first local code and described the second local code that postpone through described first arithmetic device;
Second arithmetic device, is connected with described digital controlled oscillator and selector switch, for receiving in-phase component and the quadrature component after mixing, and completes related operation with the local code that described selector switch is selected, and obtains the second operation result;
Output port, is connected with described first arithmetic device and second arithmetic device, for exporting described the first operation result and the second operation result.
Preferably, described yardage controlled oscillator is used for exporting spill over as described clock signal.
Preferably, described first arithmetic device and second arithmetic device, respectively comprise n totalizer and n pseudo-random sequence shift register;
In described first arithmetic device:
After n pseudo-random sequence shift register concatenation, one end is connected on described First ray generator, and the other end is connected on described selector switch; Each pseudo-random sequence shift register is preserved respectively described the first local code;
N totalizer connects n pseudo-random sequence shift register correspondingly, all receive in-phase component and quadrature component after mixing, and with each self-corresponding pseudo-random sequence shift register in described the first local code of preserving complete related operation, obtain described the first operation result;
In described second arithmetic device:
After n pseudo-random sequence shift register concatenation, be connected on described selector switch; Each pseudo-random sequence shift register is preserved respectively the local code that described selector switch is selected;
N totalizer connects n pseudo-random sequence shift register correspondingly, all receive in-phase component and quadrature component after mixing, and with each self-corresponding pseudo-random sequence shift register in the local code selected of the described selector switch preserved complete related operation, obtain described the second operation result.
Preferably, described first arithmetic device is for receiving bpsk signal after mixing, or the I code passage of QPSK signal after mixing.
Preferably, when described second arithmetic device selects the second local code and first arithmetic device to receive the bpsk signal after mixing for described selector switch, receive the bpsk signal after mixing.
Preferably, when described second arithmetic device selects the second local code and first arithmetic device to receive the I code passage of the QPSK signal after mixing for described selector switch, receive the Q code passage of the QPSK signal after mixing.
Preferably, when described second arithmetic device is selected described first local code of described first arithmetic device delay for described selector switch, the BPSK after reception mixing or the I code passage of QPSK signal.
Compared with prior art, the GNSS signal correction device that the present invention proposes, mainly be configured and work under serial or parallel mode by multiple multiple totalizers, follow the tracks of a certain passage/component of bpsk signal or quarternary phase-shift keying (QPSK) (QPSK) signal, or follow the tracks of homophase and orthogonal two passages of QPSK signal simultaneously, there is good versatility, can adapt to complicated and various signal structure and the requirement of algorithm.Binary channels combined tracking mode can be applicable to the tracking of the auxiliary Y code of C/A code and GPS-L5 signal etc.
Other features and advantages of the present invention will be set forth in the following description, and, partly from instructions, become apparent, or understand by implementing the present invention.Object of the present invention and other advantages can be realized and be obtained by specifically noted structure in instructions, claims and accompanying drawing.
Brief description of the drawings
Accompanying drawing is used to provide the further understanding to technical solution of the present invention, and forms a part for instructions, for explaining technical scheme of the present invention, does not form the restriction to technical solution of the present invention together with embodiments of the present invention.In the accompanying drawings:
Fig. 1 is the structural representation that carries out the many tap correlator of serial (SMT) of fast Acquisition in prior art;
Fig. 2 is the composition schematic diagram of the GNSS correlator of the embodiment of the present invention one;
Fig. 3 is the structural representation of middle first arithmetic device embodiment illustrated in fig. 2 and second arithmetic device;
Fig. 4 is the synchronization mechanism schematic diagram of middle clock signal embodiment illustrated in fig. 2.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical matters whereby, and the implementation procedure of reaching technique effect can fully understand and implement according to this.
First,, if do not conflicted, the mutually combining of each feature in the embodiment of the present invention and embodiment, all within protection scope of the present invention.
Along with the development of GNSS system and the appearance of multiple NAVSTAR, multimode compatible technique becomes the definite development trend of satellite navigation receiver.In the receiving terminal of single ground, realize the integration of multiple radio frequency standard, relate to reception and processing to different modulating pattern, carrier frequency and bandwidth signal, this just requires the diversified trend that baseband portion can adaptation signal structure.Correlator is the nucleus module of catching and following the tracks of, and intermediate-freuqncy signal is mapped to base band.Modern GNSS receiver is in order to make full use of multiple constellations and frequency; conventionally meeting huge correlator of integrated quantity in baseband chip; therefore correlator design requirement is not only compact but also have good versatility, can adapt to complicated and various signal structure and the requirement of algorithm.
The in real time accurate global position system that GPS has Global coverage ability as first, has become the actual international standard in GNSS field.The defect in use coming out for GPS-L1C/A and Y coded signal, the U.S. comes into effect GPS updating program, so that system is upgraded.Galileo system has adopted the signal of New System in a large number, all civilian frequencies have all comprised pilot tone (pilot) signal that there is no navigation message modulation, for user among the people provides the binary offset carrier that anti-interference is better (BOC) signal.Although GLONASS system adopts frequency division multiple access technology, is still digital phase moudlation signal, it is caught and tracking mode and gps system and Galileo system indistinction.
Following table is the brief summary to GPS and Galileo signal characteristic:
The brief summary of table 1GNSS signal characteristic
Embodiment mono-, GNSS correlator
Fig. 2 is the structural representation of the present embodiment.As shown in Figure 2, the correlator of the present embodiment mainly comprises yardage controlled oscillator (NCO) 210, the first frequency divider 220, the second frequency divider 230, First ray generator 240, the second sequencer 250, first arithmetic device 260, second arithmetic device 280, selector switch 270 and output port 290, wherein:
Code NCO 210, be connected with the first frequency divider 220, the second frequency divider 230, first arithmetic device 260 and second arithmetic device 280, in order to accurate clock signal to be provided, ensure achieve a butt joint collect mail number code catch and follow the tracks of;
The first frequency divider 220, is connected with code NCO210 and First ray generator 240, carries out frequency division for the clock signal that code NCO 210 is provided, and obtains the first fractional frequency signal;
The second frequency divider 230, is connected with code NCO210 and the second sequencer 250, carries out frequency division for the clock signal that code NCO 210 is provided, and obtains the second fractional frequency signal;
First ray generator 240, is connected with the first frequency divider 220 and first arithmetic device 260, for generate the first local code adapting with homophase (I) code according to the first fractional frequency signal;
The second sequencer 250, is connected with the second frequency divider 230 and selector switch 270, for generate the second local code adapting with orthogonal (Q) code according to the second fractional frequency signal;
First arithmetic device 260, be connected with code NCO210, First ray generator 240, selector switch 270 and output port 290, for receiving homophase (I) component (the In-phase arm after mixing, digital signal) and orthogonal (Q) component (Quadra-phase arm, digital signal), and complete related operation with the first local code that First ray generator 240 generates, obtain the first operation result;
Second arithmetic device 280, be connected with code NCO210, selector switch 270 and output port 290, for receiving homophase (I) component (digital signal) and orthogonal (Q) component (digital signal) after mixing, and complete related operation with the selected local code of selector switch 270, obtain the second operation result;
After being configured, the present embodiment can work under serial and parallel mode.The first local code outputs to after first arithmetic device 260, under serial mode, sends to second arithmetic device 280 through selector switch 270.Under parallel mode, the first local code outputs to first arithmetic device 260, the second local codes and sends to second arithmetic device 280 through selector switch 270.
Fig. 3 is the concrete structure schematic diagram of above-mentioned first arithmetic device 260 and second arithmetic device 280.As shown in Figure 3, above-mentioned first arithmetic device 260 and second arithmetic device 280 can be to be respectively mainly made up of n totalizer and n pseudo-random sequence shift register.After n in first arithmetic device 260 pseudo-random sequence shift register concatenation, one end (the first register PN as shown in the figure
1) be connected on First ray generator 240 other end (n register PN as shown in the figure
n) be connected on the first input end of selector switch 270.After n in second arithmetic device 280 pseudo-random sequence shift register concatenation, one end (n+1 register PN as shown in the figure
n+1) be connected on the output terminal of selector switch 270 (the second input end of selector switch 270 accesses the second local code).Each shift register in each arithmetical unit, (shift register in first arithmetic device 260 is preserved the first local code that First ray maker 240 generates to the local code that saving sequence maker generates respectively, and the shift register in second arithmetic device 280 is preserved through the selected local code of selector switch 270 (the second local code that the first local code that first arithmetic device 260 forwards or the second sequence generator 250 generate).Each totalizer in each arithmetical unit (first arithmetic device 260 and second arithmetic device 280), be connected to uniquely separately on a corresponding shift register, be that each totalizer in first arithmetic device 260 is connected respectively to the each shift register in first arithmetic device 260 correspondingly, the each totalizer in second arithmetic device 280 is connected respectively to the each shift register in second arithmetic device 280 correspondingly.Each totalizer in each arithmetical unit, all access after homophase (I) component (digital signal) and orthogonal (Q) component (digital signal) after mixing, complete related operation with the local code in corresponding shift register, and operation result is separately outputed to output port 290.
The totalizer of each group in arithmetical unit, corresponding different delay-correlated.Under serial mode, the different delayed time of the corresponding same road of the totalizer signal in two arithmetical unit is relevant, and under parallel mode, the corresponding delay-correlated of totalizer in two arithmetical unit is separate.
Technical scheme of the present invention can be followed the tracks of a certain passage/component of bpsk signal or QPSK signal.Bpsk signal only has a code passage, and QPSK signal has two code passages (each yard of intermediate-freuqncy signal corresponding to passage all comprised homophase and orthogonal two carrier components).Technical solution of the present invention, under parallel mode, can be turn-offed 280 of second arithmetic devices and follow the tracks of with first arithmetic device 260 passage of BPSK or QPSK signal; Can under serial mode, use two arithmetical unit (first arithmetic device 260 and second arithmetic device 280) to do finer tracking to a code passage of BPSK or QPSK signal; Also can under parallel mode, follow the tracks of two passages (each arithmetical unit is followed the tracks of a passage) of QPSK signal with two arithmetical unit.
When having two bpsk signals by a frequency, can process this two bpsk signals with two arithmetical unit.Such as GPS-L2C signal, two pseudo-random codes of L2CM and L2CL are modulated on same carrier wave with time division multiplexing mode, can parallel mode follow the tracks of L2CM and L2CL or combined tracking simultaneously.
Under parallel mode, the I code passage of the first frequency divider 220, First ray generator 240 and first arithmetic device 260 treatments B psk signals or QPSK signal, the Q code passage of the second frequency divider 230, the second sequencer 250 and second arithmetic device 280 treatments B psk signals or QPSK signal; Or turn-off the second frequency divider 230, the second sequencer 250 and second arithmetic device 280, only retain the first frequency divider 220, First ray generator 240 and first arithmetic device 260 and process the I code passage of QPSK signal.Under serial mode, the first frequency divider 220, First ray generator 240, first arithmetic device 260 and second arithmetic device 280 are connected the I code passage of processing bpsk signal or QPSK signal by selector switch 270.
The spill over exported of code NCO 210 provides local First ray generator 240 and the second sequencer 250, with totalizer in first arithmetic device 260 and second arithmetic device 280 and the clock signal of shift register synchronous operation.This clock signal is after the frequency division of the first frequency divider 220 and the second frequency divider 230 is processed, drive respectively First ray generator 240 and the second sequencer 250, the minimum spacing (N/mono-chip) that has determined accordingly narrow correlator, the synchronization mechanism of clock signal as shown in Figure 4.
The controlling mechanism of Fig. 4 based on code NCO.Low-converter data synchronizing signal (Data enable fromdown convert) exports the each totalizer (acc) in a yard NCO (Code NCO) 210 and two arithmetical unit to.The spill over (overflow) of code NCO output drives Dump counter, has determined when each totalizer exports cumulative/correlated results.The spill over of code NCO output also drives the each shift register in two arithmetical unit to carry out shifting function.The spill over of code NCO output also drives Pm counter, determines when pseudo-random code (PRN) maker produces new chip.
As can be seen from Table 1, Current GPS signal and Galileo signal have all comprised homophase and orthogonal two code components, carry out concurrently the working method of related operation so above-described embodiment has defined homophase code component and orthogonal code component.As shown in Figures 2 and 3,2n totalizer is divided into two groups, can select and a different set of local code input for second group.Two digital frequency dividers make two sequence generators can produce the local code of different code checks, two groups of totalizers (totalizer in totalizer and second arithmetic device in first arithmetic device) can form (narrow) correlator of different spacing, process the mutually orthogonal input signal of two-way.This characteristic adaptation is in the feature of GPS-L1 frequency, and the code check of in-phase branch C/A code and quadrature branch P (Y) differs ten times.Conventionally adopt identical correlator spacing (if intactly receive two branch roads of QPSK signal, selector switch 270 can be exported the second local code) for the equal signal of two branch road code checks (as GPS-L5 and Galileo).
It should be noted that, in each arithmetical unit, the quantity of totalizer should be moderate, the very few tracking that may give some signal (as binary offset carrier (BOC) signal) brings difficulty, the ability of future feature expansion and performance boost also can be restricted, and crosses and can waste at most hardware resource and unnecessarily increase power consumption.Galileo has adopted compound BOC (Composite BOC) signal at E1 frequency, and BOC signal can appear on more satellite navigation system, more frequency because of its outstanding interference free performance from now on.But also there is an inherent shortcoming in BOC signal, more than one of its relevant peaks, what track loop locked may not be main peak, thereby may introduce larger pseudo range measurement deviation, causes positioning error to transfinite.Judge whether locking correctly needs multiple totalizers more completely to describe correlation curve, the Bump-Jump method being widely adopted needs 5 totalizers, if only need to follow the tracks of a road signal (can be both a bpsk signal, also can be a passage/branch road of QPSK signal), correlator can turn-off any one arithmetical unit and corresponding frequency divider and sequencer, to reduce power consumption.
GPS-L2C signal is modulated on same carrier channel and produces with time division multiplexing mode by two pseudo-random sequence L2CM and L2CL at present.Above-mentioned correlator embodiment of the present invention, in cumulative, can follow the tracks of two codes of L2CM and L2CL simultaneously.Above-mentioned correlator embodiment of the present invention is in cumulative, can be according to the effective time of two pseudo-random sequences, control respectively that in complex correlator, ((reality) correlator is only processed passage/PRN code of a bpsk signal or QPSK signal, complex correlator is equivalent to two (reality) correlators, so can process two PRN codes of QPSK signal) whether totalizer work, and carrys out in timeslice separately, to carry out respectively accumulating operation.
When correlator works in serial mode, 2n totalizer in two arithmetical unit contributes to the characteristic of signal or interference draw meticulously and extract.Taking anti-multipath interference as example, the technology of main flow is all to adopt the correlator of multiple specific distance to simulate the shape of relevant peaks by the whole bag of tricks, accordingly code measurement result is revised.Under equal noise level, the performance of matching is directly proportional to counting of matching of participation.Totalizer number is more, just can under lower carrier-to-noise ratio condition, reject the impact that multipath disturbs.And, the satellite that the angle of pitch is lower, its signal carrier-to-noise ratio is lower, and multipath disturbs also more serious.In the resolving of position, speed and time (PVT), add low elevation angle satellite to contribute to improve geometric dilution of precision (DOP is also referred to as precision degree of strength) value, improve positioning precision, but prerequisite is effectively to suppress multipath to disturb, control survey error.
Correlator under work in series mode also can be for signal capture, especially recapturing after signal transient loss.Along with the maturation of micro electro mechanical system (MEMS) technology, the cost of inertial measuring unit had had remarkable decline in recent years, and the range of application of whipping lead/GPS combination technique is extended to the low-end markets such as road vehicle, train, short-range guided missile, unmanned vehicle and personal navigation gradually by high-end ship, aircraft and long-range missile.For static or through lead/gps system of whipping of close adjustment, receiver user-intersatellite radially relative velocity is known.Can determine rough code phase by positioning calculation result and known satellite position, the quick reacquisition after can realizing signal and lose in short-term according to determined rough code phase.Serial mode work can provide than the correlator of many one times of parallel mode, has improved the speed of reacquisition.
The code cycle of a part of frequency is 1 millisecond as shown in Table 1, and the code cycle of all the other frequencies is not 1 millisecond.As shown in table 1, the code of GNSS signal has 1ms, 4ms, 20ms etc. in a cycle, and the cumulative time of correlator is configured according to the length in the code cycle of the signal that will follow the tracks of, to adapt to the length in code cycle of unlike signal.
The GNSS signal correction device that technical solution of the present invention provides, can be according to signal environment and processing policy flexible configuration, support configurable serial mode or parallel mode work, (chip that adjacent totalizer is corresponding may be identical for configurable correlator spacing, also may be different, if there be at most N the chip that adjacent totalizer is corresponding identical, correlator spacing is N/mono-).Under concurrent working mode, the parameter such as relevant spacing of two branch roads can be set respectively.Support QPSK combined tracking, C/A assists P code tracking, supports BOC to follow the tracks of, and supports L2C signal trace.The starting and ending time of totalizer (being integrator) is configurable, to adapt to the code cycle of different satellite system signals.Support to turn-off I or Q branch road totalizer to reduce power consumption.In addition, configurable code generator, can be for generation of the spreading code of different satellite systems.
Technical scheme of the present invention provides the correlator technical scheme under a kind of diversified GNSS signal structure background, in application, support multiple processing policy, and even such as the quick reacquisition of the multiple correlator cascades of serial mode after realizing signal and losing in short-term, under serial mode, use multiple totalizers to support multipaths restraint algorithm (as the PAC technology of NovAtel company), multiple totalizers support the Jump-Bump of BOC to follow the tracks of (must at least 5 totalizers), and parallel mode can be supported combined tracking of QPSK signal and time division multiplex GPS-L2C signal etc.
Those skilled in the art should be understood that, above-mentioned of the present invention each module or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on the network that multiple calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in memory storage and be carried out by calculation element, or they are made into respectively to each integrated circuit modules, or the multiple modules in them or step are made into single integrated circuit module realize.Like this, the present invention is not restricted to any specific hardware and software combination.
Although the disclosed embodiment of the present invention as above, the embodiment that described content just adopts for the ease of understanding the present invention, not in order to limit the present invention.Technician in any the technical field of the invention; do not departing under the prerequisite of the disclosed spirit and scope of the present invention; can do any amendment and variation what implement in form and in details; but scope of patent protection of the present invention, still must be as the criterion with the scope that appending claims was defined.
Claims (6)
1. a correlator for global positioning satellite navigation signal, is characterized in that, comprising:
Yardage controlled oscillator, for providing clock signal;
The first frequency divider, is connected with described yardage controlled oscillator, for described clock signal is carried out to frequency division, obtains the first fractional frequency signal;
The second frequency divider, is connected with described yardage controlled oscillator, for described clock signal is carried out to frequency division, obtains the second fractional frequency signal;
First ray generator, is connected with described the first frequency divider, for generating according to described the first fractional frequency signal the first local code adapting with homophase code;
The second sequencer, is connected with described the second frequency divider, for generating according to described the second fractional frequency signal the second local code adapting with orthogonal code;
First arithmetic device, is connected with described yardage controlled oscillator and First ray generator, for receiving in-phase component and the quadrature component after mixing, and completes related operation with described the first local code, obtains the first operation result;
Selector switch, is connected with described the second sequencer and first arithmetic device, for selecting a kind of local code from described the first local code and described the second local code that postpone through described first arithmetic device;
Second arithmetic device, is connected with described digital controlled oscillator and selector switch, for receiving in-phase component and the quadrature component after mixing, and completes related operation with the local code that described selector switch is selected, and obtains the second operation result;
Output port, is connected with described first arithmetic device and second arithmetic device, for exporting described the first operation result and the second operation result;
Wherein, described first arithmetic device and second arithmetic device, respectively comprise n totalizer and n pseudo-random sequence shift register;
After n in described first arithmetic device pseudo-random sequence shift register concatenation, one end is connected on described First ray generator, and the other end is connected on described selector switch; Each pseudo-random sequence shift register is preserved respectively described the first local code;
N in a described first arithmetic device totalizer connects n pseudo-random sequence shift register in described first arithmetic device correspondingly, all receive in-phase component and quadrature component after mixing, and with each self-corresponding pseudo-random sequence shift register in described the first local code of preserving complete related operation, obtain described the first operation result;
After n in described second arithmetic device pseudo-random sequence shift register concatenation, be connected on described selector switch; Each pseudo-random sequence shift register is preserved respectively the local code that described selector switch is selected;
N in a described second arithmetic device totalizer connects n pseudo-random sequence shift register in described second arithmetic device correspondingly, all receive in-phase component and quadrature component after mixing, and with each self-corresponding pseudo-random sequence shift register in the local code selected of the described selector switch preserved complete related operation, obtain described the second operation result.
2. correlator according to claim 1, is characterized in that:
Described yardage controlled oscillator is used for exporting spill over as described clock signal.
3. correlator according to claim 1, is characterized in that:
Described first arithmetic device is for receiving bpsk signal after mixing, or the I code passage of QPSK signal after mixing.
4. correlator according to claim 3, is characterized in that:
When described second arithmetic device selects the second local code and first arithmetic device to receive the bpsk signal after mixing for described selector switch, receive the bpsk signal after mixing.
5. correlator according to claim 3, is characterized in that:
When described second arithmetic device selects the second local code and first arithmetic device to receive the I code passage of the QPSK signal after mixing for described selector switch, receive the Q code passage of the QPSK signal after mixing.
6. correlator according to claim 1, is characterized in that:
When described second arithmetic device is selected described first local code of described first arithmetic device delay for described selector switch, the BPSK after reception mixing or the I code passage of QPSK signal.
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| CN103543441B (en) * | 2013-10-21 | 2015-08-26 | 南京理工大学 | Based on the digital correlator of FPGA nanosecond programmable time delay circuit |
| CN103983989B (en) * | 2014-05-14 | 2016-05-18 | 付寅飞 | A kind of digital non-integer track loop for satellite positioning navigation receiving system |
| US9100107B1 (en) * | 2014-10-22 | 2015-08-04 | Honeywell International Inc. | Systems and methods for global navigation satellite system signal tracking |
| CN104898133B (en) * | 2015-06-04 | 2018-12-07 | 中国人民解放军国防科学技术大学 | Anti-multipath method of reseptance applied to bpsk signal |
| CN108226967B (en) * | 2016-12-15 | 2021-08-20 | 展讯通信（上海）有限公司 | GNSS signal tracking method and device |
| CN107202996B (en) * | 2017-05-31 | 2020-08-25 | 成都盟升电子技术股份有限公司 | Satellite navigation anti-deception jamming design method based on multipoint correlation method |
| CN109307876B (en) * | 2018-11-08 | 2021-09-07 | 北京理工大学 | Autonomous integrity monitoring method suitable for GNSS vector tracking |
| CN109541559B (en) * | 2018-11-12 | 2020-06-19 | 北京航空航天大学 | PSK (phase Shift keying) technology-based real-time calibration method for broadband analog complex correlator |
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