CN102522988A - Symmetrical current source array switching sequence generation method and device and application thereof - Google Patents
Symmetrical current source array switching sequence generation method and device and application thereof Download PDFInfo
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- CN102522988A CN102522988A CN2011104562926A CN201110456292A CN102522988A CN 102522988 A CN102522988 A CN 102522988A CN 2011104562926 A CN2011104562926 A CN 2011104562926A CN 201110456292 A CN201110456292 A CN 201110456292A CN 102522988 A CN102522988 A CN 102522988A
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Abstract
The invention discloses a symmetrical current source array switching sequence generation method and a device and application thereof, which relate to the technical field of current type DACs (digital to analog convertors). The symmetrical current source array switching sequence generation method includes: S1, initializing the number M of current sources distributed with switching sequences in selected regions in a to-be-driven symmetrical current source array, the error sum of the M current sources and the INL(integral non-linearity)_d to be zero and computing error of each current source in secondary error distribution; S2, updating the M and the INL_d and arranging the current sources without being distributed with switching sequence numbers to be the VECTOR; S3, selecting multiple current sources from the vector to group a partial sequence Ap={ak1, ak2,..., akp}; and S4, distributing switching sequences for the current sources in the Ap according to the current INL_d. By the symmetrical current source array switching sequence generation method and the device and the application thereof, current error accumulation can be smaller than that of the current various switching sequences, and accordingly the precision of the current type DACs is improved correspondingly.
Description
Technical field
(Digital to Analog Converter, DAC) (be called for short current mode DAC) technical field relate in particular to a kind of generation method, device and application thereof of on off sequence of symmetric form current source array to the present invention relates to current steering digital-to-analog converter.
Background technology
Along with the continuous development of the signal processing technology and the communication technology, the interfacing between digital signal and the analog signal becomes the bottleneck of restriction digital-to-analogue hybrid system.In order to satisfy the data transaction requirement of high-speed, high precision, (Analog to Digital Converter ADC) need reach high as far as possible speed and precision for DAC and analog to digital converter.In the high-speed DAC, current mode DAC becomes numerous engineers' first-selected structure in modern times, because it can directly drive resistive load, and has fast speeds.
Common current mode DAC structure is as shown in Figure 1, mainly comprises following components: supplied with digital signal decoding module (Decoder), switch module (Switches), current source array (Current Sources).Wherein, the supplied with digital signal decoding module is used for the digital signal of input is deciphered and handled, make the signal of output can be directly as the control signal of switch module.Switch module is directed to positive output end IOUTP or negative output terminal IOUTN with the electric current of current source array output under the effect of control signal; Any output in these two outputs can also can be used the output of the difference of these two outputs as digital to analog converter as the output of digital to analog converter.
In realization, current source array is formed a two-dimensional array usually, places on the chip piece.In the array, the size of current of each current source is usually designed to identical, and the digital signal of input converts control signal behind the thermometer coding to control the current direction of each current source: or to positive output end, or to negative output terminal.Common current source array can be divided into two kinds of symmetric array and asymmetric arrays.In the symmetric array, a center symmetric points O is arranged, each current source is split into the little current source that forms centrosymmetric several same size about central point O.Be illustrated in figure 2 as the current source array that a current source is split into the symmetry of two symmetrical little current sources.Each grid is represented a current source among the figure.
When digital to analog converter was worked, along with supplied with digital signal is increasing, increasing current source was directed into positive output end, and is also increasing thereby the output current when making the output of positive output end and difference is followed the variation of input.In the ideal case, the output current strictness is proportional to the digital signal of input.But in realizing circuit, because the existence of various non-ideal factors, all there is certain deviation in the current value of each current source in the current source array with its design load.This deviation is divided into two kinds, and a kind of is random deviation, and promptly the size of the value of deviation is at random; Another kind often is called system deviation, or claims the system matches error.The current source of current mode DAC generally is made up of metal-oxide-semiconductor; These metal-oxide-semiconductors are designed to have identical size and shape; But because the process deviation in chip manufacturing proces; Cause these on all four in theory metal-oxide-semiconductors to be actually devious, this deviation just is called device mismatch, and the deviation that device mismatch caused is the system matches error.This system deviation is main with deviation and secondary deviation in chip.Along with the increase of output current, this deviation is constantly accumulated, thereby influences the precision of digital to analog converter.
Integral nonlinearity (being INL) is a kind of index of describing the transformed error of digital to analog converter, and what it was described is the realization output valve of digital to analog converter and the deviation between the idea output.INL is more little, and the precision of digital to analog converter is also just high more.Therefore, the precision of digital to analog converter is described with INL usually.
Current have a lot of methods to reduce INL.First kind of thinking is the matching precision between the current source in increasing current source array, promptly reduces the size of current of each current source and the deviation between the ideal current size.The realization of this thinking depends on more advanced chip manufacturing process, higher overdrive voltage, bigger transistor area usually.Under given chip manufacturing process; The increase of overdrive voltage can reduce the digital to analog converter amplitude of output voltage, and bigger transistor area can cause the area of whole current source array excessive and possibly cause the current value matching precision between the current source of apart from each other in the chip poorer.Therefore, the effect of first kind of thinking is very limited, promptly relies on it to realize that high-precision digital to analog converter is difficult under the present case.Second kind of thinking is to use alignment technique and dynamic element matching technique.This technology can make digital to analog converter reach the precision of 16 bits, but has increased the complexity and the design difficulty of digital to analog converter.The third thinking is to use suitable on off sequence (Switching sequence).What on off sequence was described is when the input of digital to analog converter constantly increases, the order of gating successively in the current source array.Because the current error in the current source array has the excessive accumulation that just also has negative, suitable on off sequence both can avoid positive error, the excessive accumulation of the error that also can avoid bearing.Use the third thinking can make the precision of digital to analog converter reach 14 bits at present, and implementation is more simple with respect to second kind of thinking.
Disclosed at present on off sequence mainly contains Row-Column, Q
2Disclosed on off sequence or the like in Random Walk, GET, SPBR and the U.S. Pat 20050012650.These on off sequences can reduce the accumulation of current error to a certain extent, but effect is limited, and the precision of corresponding current mode DAC is not high.
Summary of the invention
The technical problem that (one) will solve
The technical problem that the present invention will solve is: the accumulation that a kind of current error is provided is much smaller than current disclosed various on off sequences, can improve generation method, device and the application thereof of on off sequence of the symmetrical current source array of corresponding current mode DAC precision.
(2) technical scheme
For addressing the above problem, the invention provides the generation method of the on off sequence of symmetrical current source array, the method comprising the steps of:
S1. in the selection area in the initialization symmetrical current source array to be driven the current source of dispense switch sequence number count M and said M the sum of the deviations INL_d of the current source of dispense switch sequence number be 0, and calculate the error that the second order error branch plants each current source;
S2. upgrade said M and INL_d, with the current source of unallocated switch sequence number by error from big to small successively ordering be vectorial VECTOR, i.e. { a
1, a
2, a
3..., a
N-M, N is the current source sum in the said selection area;
S3. from said vectorial VECTOR, select a plurality of current sources to form a partial sequence Ap={a
K1, a
K2..., a
Kp, said sequence A p is satisfied impose a condition;
S4. according to current INL_d, be the current source dispense switch sequence number among the selected said sequence A p of step S3.
Preferably, include only a current source in every group of symmetrical current source in the said selection area.
Preferably, in step S3, said impose a condition into:
Wherein, E (i) is the error amount of each current source, and wherein i, ki are sequence number, i=1; 2...N-M, ki=k1, k2...; Kp, B are the higher value in the theory lower bound of integral nonlinearity of INL_d and said vectorial VECTOR, i.e. B=max{E (1)/2;-E (N-M)/2, abs (INL_d) }, Δ is the preset permission difference between the theory lower bound of the theory lower bound of the integral nonlinearity of the on off sequence that generates and the integral nonlinearity of whole possible on off sequences.
Preferably, step S4 further comprises:
S4.1 is with current source a
K1, a
K2..., a
KpGive on off sequence M+1 respectively, M+2 ..., M+p;
S4.2 is if exist the current source of unallocated on off sequence number, execution in step S4.3 then, otherwise flow process finishes;
If S4.3 is INL_d >=0; Then from said vectorial VECTOR, select the not minimum current source of the current error value in Ap, and give its on off sequence M+p+1, continue execution in step S4.4; Otherwise; From said vectorial VECTOR, select the not maximum current source of the current error value in Ap, and give its on off sequence M+p+1, continue execution in step S4.4;
S4.4 is if exist the current source of unallocated on off sequence number, execution in step S4.5 then, otherwise flow process finishes;
If S4.5 is INL_d >=0; Then from said vectorial VECTOR, select the not maximum current source of the current error value in Ap, and give its on off sequence M+p+2, continue execution in step S4.6; Otherwise; From said vectorial VECTOR, select the not minimum current source of the current error value in Ap, and give its on off sequence M+p+2, continue execution in step S4.6;
S4.6 then returns execution in step S2 if there is the current source of unappropriated on off sequence number, otherwise flow process finishes.
The present invention also provides a kind of on off sequence generating apparatus, and this device uses said method to generate on off sequence.
The present invention also provides a kind of current mode digital-to-analog converter, comprises switch module, and said switch module is the described on off sequence generating apparatus of claim 5.
Preferably, this device also comprises: the symmetrical current source array that links to each other with said switch module, the current source of said symmetrical current source array is made up of PMOS transistor or nmos pass transistor.
(3) beneficial effect
Method of the present invention, device and application thereof; Can be according to the domain shape of selected current source array; Set out suitable on off sequence; Reduce the system matches error of size of current in the current source array, can so that the accumulation of current error much smaller than current various on off sequences, thereby improve the precision of corresponding current mode DAC.
Description of drawings
Fig. 1 is a typical current type DAC structural representation;
Fig. 2 is the generation result of the on off sequence of square symmetrical current source array;
Fig. 3 is the generation result of the on off sequence of circular symmetry current source array;
Fig. 4 is the generation method flow diagram according to the on off sequence of the symmetrical current source array of one embodiment of the present invention;
Fig. 5 is the schematic flow sheet according to an instance of the generation method of the on off sequence of the symmetrical current source array of one embodiment of the present invention;
On off sequence and existing the performance comparison under quadratic distribution systematic error with on off sequence of Fig. 6 (a)-Fig. 6 (f) for generating according to method of the present invention.
Embodiment
Generation method, device and the application thereof of the on off sequence of the symmetric form current source array that the present invention proposes specify as follows in conjunction with accompanying drawing and embodiment.
For further illustrating principle of the present invention, what need explanation is: all there is certain error in each current source in the current source array.When a given lateral coordinates x and along slope coordinate y, error can be designated as ε (x, y)=a
11X+a
12Y+a
21x
2+ a
22y
2+ a
23Xy+..., wherein error component with once and quadratic term be main, and a
21≈ a
22, and a
23The xy item can be ignored basically, so ε (x, y) ≈ a
11X+a
12Y+a
2(x
2+ y
2).After error profile was confirmed, the theory lower bound through the INL after the on off sequence optimization was Max (abs (ε (x, y))/2.
In the current source array of symmetry, each current source is split into the same less current source of several design current values, and these several current sources form centrosymmetric arrangement mode.In the current source array of symmetry, if the CURRENT DISTRIBUTION error of only considering once, owing to just be one positive one negative, so current source error accumulation once is zero about the error of centrosymmetric any two current sources.So only need to consider how to eliminate the current source error of quadratic term in the current source array of symmetry, i.e. second order error.On the other hand, in symmetric array, when the central point of second order error changed, the INL of the accumulation that it causes can't change.This is to have introduced first-order error because the central point of second order error changes to be equivalent to, and symmetric array can be eliminated all first-order errors.So, when generating the on off sequence of current source array, only need guarantee as far as possible little the getting final product of INL that under certain concrete second order error, accumulates to the current source array of symmetry.
As shown in Figure 4, comprise step according to the generation method of the on off sequence of the symmetrical current source array of one embodiment of the present invention:
S1. in the selection area in the initialization symmetrical current source array to be driven the current source of dispense switch sequence number count M and M the sum of the deviations INL_d of the current source of dispense switch sequence number be 0; And given certain average is that 0 second order error distributes, and calculates the error of each current source;
Consider symmetry, the current source array of symmetry can be divided into several symmetrical zones; The on off sequence that generates whole current source array is equivalent to the wherein on off sequence in a zone of generation.In step S1, coordinate system is set up in a zone only need choosing in the current source array of symmetry, this zone is comprised and includes only a current source in every group of symmetrical current source.
S2. upgrade M and INL_d, with the current source of unallocated on off sequence number by error from big to small successively ordering be vectorial VECTOR, i.e. { a
1, a
2, a
3..., a
N-M, N is the current source sum in this selection area;
S3. from vectorial VECTOR, select a plurality of current sources to form a partial sequence Ap={a
K1, a
K2..., a
Kp, sequence A p is satisfied impose a condition;
S4. according to current INL_d, be the current source dispense switch sequence number among the selected sequence A p of step S3.
In step S3, impose a condition into:
Wherein, E (i) is the error amount of each current source, and wherein i, ki are sequence number, i=1; 2...N-M, ki=k1, k2...; Kp, B are the higher value in the theory lower bound of INL of INL_d and said vectorial VECTOR, i.e. B=max{E (1)/2;-E (N-M)/2, abs (INL_d) }, the permission difference of setting between the theory lower bound of Δ for the theory lower bound of the INL of the on off sequence that generates and the INL of whole possible on off sequences.
In the method for this execution mode, step S4 further comprises:
S4.1 is with current source a
K1, a
K2..., a
KpGive on off sequence M+1 respectively, M+2 ..., M+p;
S4.2 is if there is the current source of unappropriated on off sequence number, execution in step S4.3 then, otherwise flow process finishes;
If S4.3 is INL_d >=0; Then from vectorial VECTOR, select the not current source of the current error value in Ap minimum (being that negative sense is maximum); Give on off sequence M+p+1; Otherwise, from vectorial VECTOR, select the not current source of the current error value in Ap maximum (being that forward is maximum), give on off sequence M+p+1;
S4.4 is if there is the current source of unappropriated on off sequence number, execution in step S4.5 then, otherwise flow process finishes;
If S4.5 is INL_d >=0; Then from vectorial VECTOR, select the not current source of the current error value in Ap maximum (being that forward is maximum); Give on off sequence M+p+2; Otherwise, from vectorial VECTOR, select the not current source of the current error value in Ap minimum (being that negative sense is maximum), give on off sequence M+p+2;
S4.6 then returns execution in step S2 if the current source of unappropriated on off sequence number is arranged, otherwise flow process finishes.
Fig. 5 provides a sample that above-mentioned flow process is described. Current source 1,2,3,6,7}, 4,8}, { 5,9} composes the on off sequence value among step S3, S4.3, the S4.5.What need explanation a bit is, because the sequence A p in the above-mentioned flow process is not unique, therefore can utilize this flow process to obtain the similar many on off sequences of performance.The sample of the complete symmetrical current source array that said method of the present invention provides is like accompanying drawing 2, shown in 3.
With existing on off sequence (Row-Column, Q
2Random Walk, GET, SPBR) to compare, the on off sequence that method of the present invention generates can reduce the accumulation of current value systematic error in the current source array.Like table 1 with shown in Fig. 6 (a)-Fig. 6 (f), method of the present invention can be reduced to the systematic error of the quadratic distribution in the array of symmetry theoretic minimum value, be existing best on off sequence (SPBR) accumulation error 23%.
The performance of symmetrical switch sequence that table 1 the present invention proposes and existing disclosed symmetrical switch sequence relatively
In addition, the present invention also provides a kind of on off sequence generating apparatus, and this device uses said method to generate on off sequence.
The present invention further provides a kind of current mode DAC, the symmetrical current source array that comprises switch module and link to each other with switch module, and this switch module is above-mentioned on off sequence generating apparatus.And this current mode DAC can draw electric current (Source) type DAC for what be made up of current source the PMOS transistor; Also can be for constitute filling electric current (Sink) the type DAC of current source by nmos pass transistor; The kind of PMOS and nmos type current source is well known to those skilled in the art, at this not as limitation of the present invention.
Above execution mode only is used to explain the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (7)
1. the generation method of the on off sequence of a symmetrical current source array is characterized in that the method comprising the steps of:
S1. in the selection area in the initialization symmetrical current source array to be driven the current source of dispense switch sequence number count M and said M the sum of the deviations INL_d of the current source of dispense switch sequence number be 0, and calculate the error that the second order error branch plants each current source;
S2. upgrade said M and INL_d, with the current source of unallocated switch sequence number by error from big to small successively ordering be vectorial VECTOR, i.e. { a
1, a
2, a
3..., a
N-M, N is the current source sum in the said selection area;
S3. from said vectorial VECTOR, select a plurality of current sources to form a partial sequence Ap={a
K1, a
K2..., a
Kp, said sequence A p is satisfied impose a condition;
S4. according to current INL_d, be the current source dispense switch sequence number among the selected said sequence A p of step S3.
2. the method for claim 1 is characterized in that, includes only a current source in every group of symmetrical current source in the said selection area.
3. the method for claim 1 is characterized in that, in step S3, said impose a condition into:
Wherein, E (i) is the error amount of each current source, and wherein i, ki are sequence number, i=1; 2...N-M, ki=k1, k2...; Kp, B are the higher value in the theory lower bound of integral nonlinearity of INL_d and said vectorial VECTOR, i.e. B=max{E (1)/2;-E (N-M)/2, abs (INL_d) }, Δ is the preset permission difference between the theory lower bound of the theory lower bound of the integral nonlinearity of the on off sequence that generates and the integral nonlinearity of whole possible on off sequences.
4. method as claimed in claim 3 is characterized in that step S4 further comprises:
S4.1 is with current source a
K1, a
K2..., a
KpGive on off sequence M+1 respectively, M+2 ..., M+p;
S4.2 is if exist the current source of unallocated on off sequence number, execution in step S4.3 then, otherwise flow process finishes;
If S4.3 is INL_d >=0; Then from said vectorial VECTOR, select the not minimum current source of the current error value in Ap, and give its on off sequence M+p+1, continue execution in step S4.4; Otherwise; From said vectorial VECTOR, select the not maximum current source of the current error value in Ap, and give its on off sequence M+p+1, continue execution in step S4.4;
S4.4 is if exist the current source of unallocated on off sequence number, execution in step S4.5 then, otherwise flow process finishes;
If S4.5 is INL_d >=0; Then from said vectorial VECTOR, select the not maximum current source of the current error value in Ap, and give its on off sequence M+p+2, continue execution in step S4.6; Otherwise; From said vectorial VECTOR, select the not minimum current source of the current error value in Ap, and give its on off sequence M+p+2, continue execution in step S4.6;
S4.6 then returns execution in step S2 if there is the current source of unappropriated on off sequence number, otherwise flow process finishes.
5. an on off sequence generating apparatus is characterized in that, this device uses each described method of claim 1-4 to generate on off sequence.
6. a current mode digital-to-analog converter comprises switch module, it is characterized in that, said switch module is the described on off sequence generating apparatus of claim 5.
7. current mode digital-to-analog converter as claimed in claim 6 is characterized in that, this device also comprises: the symmetrical current source array that links to each other with said switch module, the current source of said symmetrical current source array is made up of PMOS transistor or nmos pass transistor.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI577138B (en) * | 2015-12-04 | 2017-04-01 | 上海兆芯集成電路有限公司 | Current source devices |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1351422A (en) * | 2000-10-26 | 2002-05-29 | 富士通株式会社 | Segment circuit |
| WO2003100982A1 (en) * | 2002-05-27 | 2003-12-04 | Nokia Corporation | Method for calibrating a digital-to-analog converter and a digital-to-analog converter |
| US20050012650A1 (en) * | 2003-04-07 | 2005-01-20 | Francesco Cretti | Method of generating a switching sequence for an unary array of conducting branches and a relative thermometrically decoded digital-to-analog converter |
| WO2005104376A1 (en) * | 2004-04-20 | 2005-11-03 | Koninklijke Philips Electronics N.V. | Method to improve error reduction in a digital-to-analog converter and digital-to-analog converter in which this method is applied |
| CN101494459A (en) * | 2009-02-24 | 2009-07-29 | 苏州通创微芯有限公司 | High matching current source layout for current rudder D/A converter |
| CN101800531A (en) * | 2010-03-09 | 2010-08-11 | 清华大学 | Switching device and current mode digital-to-analog converter with same |
-
2011
- 2011-12-30 CN CN201110456292.6A patent/CN102522988B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1351422A (en) * | 2000-10-26 | 2002-05-29 | 富士通株式会社 | Segment circuit |
| WO2003100982A1 (en) * | 2002-05-27 | 2003-12-04 | Nokia Corporation | Method for calibrating a digital-to-analog converter and a digital-to-analog converter |
| US20050012650A1 (en) * | 2003-04-07 | 2005-01-20 | Francesco Cretti | Method of generating a switching sequence for an unary array of conducting branches and a relative thermometrically decoded digital-to-analog converter |
| WO2005104376A1 (en) * | 2004-04-20 | 2005-11-03 | Koninklijke Philips Electronics N.V. | Method to improve error reduction in a digital-to-analog converter and digital-to-analog converter in which this method is applied |
| CN101494459A (en) * | 2009-02-24 | 2009-07-29 | 苏州通创微芯有限公司 | High matching current source layout for current rudder D/A converter |
| CN101800531A (en) * | 2010-03-09 | 2010-08-11 | 清华大学 | Switching device and current mode digital-to-analog converter with same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI577138B (en) * | 2015-12-04 | 2017-04-01 | 上海兆芯集成電路有限公司 | Current source devices |
| US9712183B2 (en) | 2015-12-04 | 2017-07-18 | Via Alliance Semiconductor Co., Ltd. | Axially and centrally symmetric current source array |
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