CN102521098B - Processing method and processing device for monitoring dead halt of CPU (Central Processing Unit) - Google Patents
Processing method and processing device for monitoring dead halt of CPU (Central Processing Unit) Download PDFInfo
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Abstract
The invention discloses a processing method and a processing device for monitoring the dead halt of a CPU (Central Processing Unit). The method comprises the following steps of: presetting a first timer; carrying out periodic zero clearing on the first timer when the CPU is in normal operation, wherein a time value t3 of a periodic time is smaller than a timing time value t1 of the first timer; when the first timer is in time-out, determining the CPU to be in dead halt when a system operates a task program; and recording the address information of the task program, and calling a task program exception manipulation function to acquire the related data of the task program at the time-out moment of the first timer. According to the processing method and the processing device for monitoring the dead halt of the CPU, the CPU is adopted to carry out periodic zero clearing on the timer, the timer cannot generate time out when the CPU is in normal operation, the CPU is determined to be in dead halt through the time-out of the timer, and the related program exception manipulation function is called to acquire the related data of a currently-running program, so that maintainers can analyze the reasons for the dead halt of the CPU according to the related data, and the efficiency and the speed for restoring the CPU are greatly accelerated.
Description
Technical field
The present invention relates to embedded system technology field, especially relate to a kind of disposal route and device of CPU deadlock monitoring.
Background technology
Embedded system usually there will be fault, and in numerous faults of embedded system, cpu fault is a problem that is difficult to location always.In order to realize the effective monitoring to CPU, in prior art, generally obtain relevant information by following processing, to analyze the reason that causes cpu fault: record obtains the task (if special processing can further record the message of last processing) of scheduling for the last time; When producing, CPU resets, recording reset reason; When because software is initiatively carried out reset operation, recording reset traceback information; Work as watchdog reset, record watchdog reset action message; Recording reset is to occur in interruption or in task.
Above-mentioned obtained relevant information, is to obtain in the situation that CPU does not crash, once CPU crashes, cannot obtain.Therefore aforesaid way cannot get the related data that causes CPU to crash.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of disposal route of CPU deadlock monitoring, the related data of current working procedure while obtaining CPU deadlock, the reason crashing to analyze CPU.
The present invention proposes a kind of disposal route of CPU deadlock monitoring, comprises step:
Default first timer, default second timer;
Other to first timer, periodically zero clearing of second timer at the normal motion time of CPU; The magnitude relationship of the timing value t1 of the time value t3 in first timer cycle and first timer is t3 < t1, and the pass between timing value t2 and the t1 of described second timer is t1 < t2; The time value t4 in the cycle of second timer is less than t2;
Overtime when first timer, judge that CPU crashes in the time of system operation task program, and to periodically zero clearing of second timer, the time value in this cycle is t4;
Record described task program address information, calling task program exception is processed function, to obtain the related data of task program described in overtime moment of first timer;
Overtime when second timer, judge that CPU crashes in the time of system outage program;
Call interrupt routine abnormality processing function, to obtain the related data of interrupt routine described in overtime moment of second timer.
Preferably, the disposal route of described CPU deadlock monitoring, also comprises:
Obtaining after the related data of described task program, the related data of this task program is being saved in the high memory of CPU; Or,
Obtaining after the related data of described interrupt routine, the related data of this interrupt routine is saved in the high memory of CPU.
Preferably, the related data of described task program comprises the following data of task program: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer;
The related data of described interrupt routine comprises the following data of interrupt routine: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer.
Preferably, the disposal route of described CPU deadlock monitoring also comprised before default first timer and second timer:
Configure hardware WatchDog Timer to be to obtain the related data of described interrupt routine, and this interrupt routine related data is saved in the high memory of CPU.
The another treating apparatus that proposes a kind of CPU deadlock monitoring of the present invention, comprising:
Presetting module, for default first timer, second timer;
The first dump block, for other to first timer, periodically zero clearing of second timer at the normal motion time of CPU, the magnitude relationship of the timing value t1 of the time value t3 in the cycle of first timer and first timer is t3 < t1, and the pass between timing value t2 and the t1 of described second timer is t1 < t2; The time value t4 in the cycle of second timer is less than t2;
The second dump block, for overtime at first timer, after judging that CPU crashes in the time of system operation task program, to periodically zero clearing of second timer, the time value in this cycle is t4;
The first determination module, for overtime when first timer, judges that CPU crashes in the time of system operation task program;
The first acquisition module, for recording described task program address information, calling task program exception is processed function, to obtain the related data of task program described in overtime moment of first timer;
The second determination module, for overtime when second timer, judges that CPU crashes in the time of system outage program;
The second acquisition module, for calling interrupt routine abnormality processing function, to obtain the related data of interrupt routine described in overtime moment of second timer.
Preferably, the treating apparatus of described CPU deadlock monitoring, also comprises:
Preserve module, for obtaining after the related data of described task program, the related data of this task program is saved in the high memory of CPU; Or, obtaining after the related data of described interrupt routine, the related data of this interrupt routine is saved in the high memory of CPU.
Preferably, the related data of described task program comprises the following data of task program: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer;
The related data of described interrupt routine comprises the following data of interrupt routine: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer.
Preferably, the treating apparatus of described CPU deadlock monitoring, also comprises:
Configuration module,, and is saved to the related data of this interrupt routine in the high memory of CPU to obtain the related data of described interrupt routine for configure hardware WatchDog Timer;
Reseting module, for when hardware watchdog timer expiry, carries out hardware watchdog timer reset operation.
The disposal route of CPU deadlock monitoring provided by the present invention, adopt CPU to periodically zero clearing of timer, make it cannot be overtime in the time that CPU normally moves, judge that by timer expiry CPU crashes, and call relative program abnormality processing function and obtain the related data of current working procedure, so that maintainer causes CPU deadlock reason according to this related data analysis, accelerate widely to repair CPU efficiency and speed.
Brief description of the drawings
Fig. 1 is the process flow diagram of disposal route one embodiment of CPU deadlock monitoring of the present invention;
Fig. 2 is the structural representation for the treatment of apparatus one embodiment of CPU deadlock monitoring of the present invention;
Fig. 3 is the structural representation of another embodiment for the treatment of apparatus of CPU deadlock monitoring of the present invention;
Fig. 4 is the structural representation of another embodiment for the treatment of apparatus of CPU deadlock monitoring of the present invention;
Fig. 5 is the structural representation of another embodiment for the treatment of apparatus of CPU deadlock monitoring of the present invention;
Fig. 6 is the structural representation of another embodiment for the treatment of apparatus of CPU deadlock monitoring of the present invention.
Realization, functional characteristics and the advantage of the object of the invention, in connection with embodiment, are described further with reference to accompanying drawing.
Embodiment
Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Referring to Fig. 1, disposal route one embodiment of CPU deadlock monitoring of the present invention is proposed, comprising:
Step S101, default first timer;
Step S102, in the time that CPU normally moves to periodically zero clearing of first timer; The magnitude relationship of the timing value t1 of the time value t3 in this cycle and first timer is t3 < t1;
Step S103, overtime when first timer, judges that CPU crashes in the time of system operation task program;
Step S104, record described task program address information, calling task program exception is processed function, to obtain the related data of task program described in overtime moment of first timer.
In said method embodiment, in the time that CPU normally moves, first timer is carried out to periodicity zero clearing.Because the time value t3 in this cycle is less than the timing value t1 of first timer, when therefore CPU normally moves, by its periodically zero clearing, can there is not overtime phenomenon in first timer.Hence one can see that, if first timer is overtime, shows that CPU is current cannot normally move, and CPU crashes.
The size of the timing value t1 of described first timer is to cause during according to operation task program the crash length of time of CPU to arrange.
Further, above-mentioned CPU crashes in the disposal route embodiment monitoring, and also comprises following processing: default second timer; In the time that CPU normally moves to periodically zero clearing of second timer; Pass between timing value t2 and the t1 of described second timer is t1 < t2; Overtime when second timer, judge that CPU crashes in the time of system outage program; Call interrupt routine abnormality processing function, to obtain the related data of interrupt routine described in overtime moment of second timer.
Further, described CPU crashes in the disposal route embodiment monitoring, described overtime when first timer, judge that CPU also comprises following processing after crashing in the time of system operation task program: second timer is carried out to periodicity zero clearing, and the time value t4 in this cycle is less than t2.
In like manner, the present embodiment, due in the time that CPU normally moves, carries out periodicity zero clearing to second timer, and the time value t3 in this cycle is less than t2, and when therefore CPU normally moves, by CPU, to its periodically zero clearing, overtime phenomenon can not occur first timer.Because the timing value t1 of first timer is less than the timing value t2 of second timer, therefore, in the time that CPU cannot normally move, first timer is first overtime, is now judged to be CPU and crashes in the time of system operation task program.Not overtime for second timer, by this second timer is carried out to periodicity zero clearing, the time value t4 in this cycle is less than the timing value t2 of second timer.
The size of the timing value t2 of described second timer is to cause during according to outage program the crash length of time of CPU to arrange.
In this method embodiment, after first timer is overtime, to periodically zero clearing failure of second timer, and cannot calling task program exception process function, second timer, by overtime, be now judged to be CPU and crash in the time of system outage program.
Further, above-mentioned CPU crashes in the disposal route embodiment monitoring, and also comprises following processing: obtaining after the related data of described task program, the related data of this task program is being saved in the high memory of CPU; Or, obtaining after the related data of described interrupt routine, the related data of this interrupt routine is saved in the high memory of CPU.
In this method embodiment, the related data of the related data of the task program obtaining or interrupt routine is saved in the high memory of CPU, can ensure not lose in the rear related data of task program of hardware watchdog reset or the related data of interrupt routine, can be by the related data writing in files system of the related data of task program or interrupt routine after hardware watchdog resets, for analyzing further, the final real factor that causes CPU to crash that obtains, so that maintainer repairs CPU fast.
Further, described CPU crashes in the disposal route embodiment monitoring, and the data that described task program is relevant comprise the following data of task program: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer.The related data of described interrupt routine comprises the following data of interrupt routine: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer.
Further, in said method embodiment, after calling task program exception is processed function or called interrupt routine abnormality processing function, also comprise following processing: call Hook Function, register related data used to obtain user, and this related data is saved in the high memory of CPU.After hardware watchdog resets, this related data is written in file system together with task program related data, or be written in file system with together with the related data of interrupt routine, for analyzing further, the final real factor that causes CPU to crash that obtains, so that maintainer repairs CPU fast.
Further, above-mentioned CPU crashes in the disposal route embodiment monitoring, before default first timer and second timer, also comprise following processing: the timing value t5 of configure hardware WatchDog Timer, with ensure CPU crash after within the t5 time, can realize the related data of obtaining described task program, and the related data of this task program is saved in the high memory of CPU; And can realize the related data of obtaining described interrupt routine within the t5 time, and the related data of this interrupt routine is saved in the high memory of CPU.Described method also comprises following processing: when hardware watchdog timer expiry, carry out hardware watchdog reset operation.
In this method embodiment, the timing value t5 of configure hardware WatchDog Timer, is for after crashing at CPU, before carrying out hardware watchdog reset operation, gets the related data that causes CPU to crash.Due to after hardware watchdog reset, can only ensure that CPU middle and high end data in EMS memory is not lost simultaneously.Therefore need to before resetting, hardware watchdog need the related data of obtaining to be saved in the high memory of CPU.
The disposal route embodiment of CPU deadlock monitoring of the present invention, adopt CPU to first timer and periodically zero clearing of second timer, make it cannot be overtime in the time that CPU normally moves, thereby judge that by timer expiry CPU crashes, and call relative program abnormality processing function and obtain the related data of current working procedure, so that maintainer causes CPU deadlock reason according to this related data analysis, accelerate widely to repair CPU efficiency and speed.
In addition, in above-described embodiment, there is a MSR register CPU inside, has several zone bits in register, by configuring these zone bits, can enable or forbid abnormal generation.If user calls some system interface function and closed abnormality mark position, after will causing second timer overtime, Critical cannot be produced abnormal.Therefore in order to prevent that user from calling some system interface function and having closed the CE zone bit in the MSR register of controlling second timer abnormal function, need to revise system interface function, Critical abnormality mark is removed from CPU interrupt inhibit control list.
Referring to Fig. 2, treating apparatus 100 1 embodiment of CPU deadlock monitoring of the present invention are proposed, it comprises: presetting module 110, the first dump block 120, the first determination module 130 and the first acquisition module 140.Wherein, presetting module 110, for default first timer; Described the first dump block 120, in the time that CPU normally moves to periodically zero clearing of first timer, the magnitude relationship of the timing value t1 of the time value t3 in this cycle and first timer is t3 < t1.The first determination module 130, for overtime when first timer, judges that CPU crashes in the time of system operation task program, and second timer is carried out to periodicity zero clearing, and the time value t4 in this cycle is less than t2.The first acquisition module 140, for recording described task program address information, calling task program exception is processed function, to obtain the related data of task program described in overtime moment of first timer.
In said apparatus embodiment, in the time that CPU normally moves, first timer is carried out to periodicity zero clearing.Because the time value t3 in this cycle is less than the timing value t1 of first timer, when therefore CPU normally moves, by its periodically zero clearing, can there is not overtime phenomenon in first timer.Hence one can see that, if first timer is overtime, shows that CPU is current cannot normally move, and CPU crashes.
The size of the timing value t1 of described first timer is to cause during according to operation task program the crash length of time of CPU to arrange.
Further, referring to Fig. 3, above-mentioned CPU crashes in treating apparatus 100 embodiment that monitor, and described presetting module 110, also for arranging second timer.Described the first dump block 120, also in the time that CPU normally moves to periodically zero clearing of second timer; Pass between timing value t2 and the t1 of described second timer is t1 < t2.Described treating apparatus 100 also comprises: the second determination module 150 and the second acquisition module 160.Wherein, described the second determination module 150, for overtime when second timer, judges that CPU crashes in the time of system outage program.Described the second acquisition module 160, for calling interrupt routine abnormality processing function, to obtain the related data of interrupt routine described in overtime moment of second timer.
Further, referring to Fig. 4, the treating apparatus 100 of described CPU deadlock monitoring, also comprise: the second dump block 170, the second dump block 170, for overtime at first timer, after judging that CPU crashes in the time of system operation task program, second timer is carried out to periodicity zero clearing, and the time value t4 in this cycle is less than t2.In like manner, the present embodiment, due in the time that CPU normally moves, carries out periodicity zero clearing to second timer, and the time value t3 in this cycle is less than t2, and when therefore CPU normally moves, by CPU, to its periodically zero clearing, overtime phenomenon can not occur first timer.Because the timing value t1 of first timer is less than the timing value t2 of second timer, therefore, in the time that CPU cannot normally move, first timer is first overtime, is now judged to be CPU and crashes in the time of system operation task program.Not overtime for second timer, by this second timer is carried out to periodicity zero clearing, the time value t4 in this cycle is less than the timing value t2 of second timer.
The size of the timing value t2 of described second timer is to cause during according to outage program the crash length of time of CPU to arrange.
In this method embodiment, after first timer is overtime, to periodically zero clearing failure of second timer, and cannot calling task program exception process function, second timer, by overtime, be now judged to be CPU and crash in the time of system outage program.
Further, referring to Fig. 5, above-mentioned CPU crashes in treating apparatus 100 embodiment that monitor, and also comprises: preserve module 180.This preservation module 180, for obtaining after the related data of described task program, is saved to the related data of this task program in the high memory of CPU; Or, obtaining after the related data of described interrupt routine, the related data of this interrupt routine is saved in the high memory of CPU.
In this device embodiment, the related data of the related data of the task program obtaining or interrupt routine is saved in the high memory of CPU, can ensure not lose in the rear related data of task program of hardware watchdog reset or the related data of interrupt routine, can be by the related data writing in files system of the related data of task program or interrupt routine after hardware watchdog resets, for analyzing further, the final real factor that causes CPU to crash that obtains, so that maintainer repairs CPU fast.
Further, above-mentioned CPU crashes in treating apparatus 100 embodiment that monitor, and the related data of described task program comprises the following data of task program: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer.The related data of described interrupt routine comprises the following data of interrupt routine: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer.
Further, in said apparatus embodiment, after calling task program exception is processed function or called interrupt routine abnormality processing function, also comprise following processing: call Hook Function, register related data used to obtain user, and this related data is saved in the high memory of CPU.After hardware watchdog resets, together with the related data of this related data and task program, be written in file system, or be written in file system together with interrupt routine related data, for analyzing further, the final real factor that causes CPU to crash that obtains, so that maintainer repairs CPU fast.
Further, referring to Fig. 6, above-mentioned CPU crashes in treating apparatus 100 embodiment that monitor, and also comprises: configuration module 190 and reseting module 101.Wherein, described configuration module 190, for the timing value t5 of configure hardware WatchDog Timer, with ensure CPU crash after within the t5 time, can realize the related data of obtaining described task program, and the related data of this task program is saved in the high memory of CPU; And can realize the related data of obtaining described interrupt routine within the t5 time, and the related data of this interrupt routine is saved in the high memory of CPU.Described reseting module 101, for when hardware watchdog timer expiry, carries out hardware watchdog reset operation.
In this device embodiment, the timing value t5 of configure hardware WatchDog Timer, is for after crashing at CPU, before carrying out hardware watchdog reset operation, gets the related data that causes CPU to crash.Due to after hardware watchdog reset, can only ensure that CPU middle and high end data in EMS memory is not lost simultaneously.Therefore need to before resetting, hardware watchdog need the related data of obtaining to be saved in the high memory of CPU.
Treating apparatus 100 embodiment of CPU deadlock monitoring of the present invention, adopt CPU to first timer and periodically zero clearing of second timer, make it cannot be overtime in the time that CPU normally moves, thereby judge that by timer expiry CPU crashes, and call relative program abnormality processing function and obtain the related data of current working procedure, so that maintainer causes CPU deadlock reason according to this related data analysis, accelerate widely to repair CPU efficiency and speed.
In addition, in above-described embodiment, there is a MSR register CPU inside, has several zone bits in register, by configuring these zone bits, can enable or forbid abnormal generation.If user calls some system interface function and closed abnormality mark position, after will causing second timer overtime, Critical cannot be produced abnormal.Therefore in order to prevent that user from calling some system interface function and having closed the CE zone bit in the MSR register of controlling second timer abnormal function, need to revise system interface function, Critical abnormality mark is removed from CPU interrupt inhibit control list.
Should be understood that; these are only the preferred embodiments of the present invention; can not therefore limit the scope of the claims of the present invention; every equivalent structure or conversion of equivalent flow process that utilizes instructions of the present invention and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (8)
1. a disposal route for CPU deadlock monitoring, is characterized in that, comprises step:
Default first timer, default second timer;
Other to first timer, periodically zero clearing of second timer at the normal motion time of CPU; The magnitude relationship of the timing value t1 of the time value t3 in first timer cycle and first timer is t3 < t1, and the pass between timing value t2 and the t1 of described second timer is t1 < t2; The time value t4 in the cycle of second timer is less than t2;
Overtime when first timer, judge that CPU crashes in the time of system operation task program, and to periodically zero clearing of second timer, the time value in this cycle is t4;
Record described task program address information, calling task program exception is processed function, to obtain the related data of task program described in overtime moment of first timer;
Overtime when second timer, judge that CPU crashes in the time of system outage program;
Call interrupt routine abnormality processing function, to obtain the related data of interrupt routine described in overtime moment of second timer.
2. the disposal route of CPU deadlock monitoring according to claim 1, is characterized in that, also comprises:
Obtaining after the related data of described task program, the related data of this task program is being saved in the high memory of CPU; Or,
Obtaining after the related data of described interrupt routine, the related data of this interrupt routine is saved in the high memory of CPU.
3. according to the disposal route of the CPU deadlock monitoring described in claim 1 to 2 any one, it is characterized in that,
The related data of described task program comprises the following data of task program: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer;
The related data of described interrupt routine comprises the following data of interrupt routine: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer.
4. the disposal route of CPU deadlock monitoring according to claim 2, is characterized in that, before default first timer and second timer, also comprises:
Configure hardware WatchDog Timer to be to obtain described interrupt routine related data, and this interrupt routine related data is saved in the high memory of CPU.
5. a treating apparatus for CPU deadlock monitoring, is characterized in that, comprising:
Presetting module, for default first timer, second timer;
The first dump block, for other to first timer, periodically zero clearing of second timer at the normal motion time of CPU, the magnitude relationship of the timing value t1 of the time value t3 in the cycle of first timer and first timer is t3 < t1, and the pass between timing value t2 and the t1 of described second timer is t1 < t2; The time value t4 in the cycle of second timer is less than t2;
The second dump block, for overtime at first timer, after judging that CPU crashes in the time of system operation task program, to periodically zero clearing of second timer, the time value in this cycle is t4;
The first determination module, for overtime when first timer, judges that CPU crashes in the time of system operation task program;
The first acquisition module, for recording described task program address information, calling task program exception is processed function, to obtain the related data of task program described in overtime moment of first timer;
The second determination module, for overtime when second timer, judges that CPU crashes in the time of system outage program;
The second acquisition module, for calling interrupt routine abnormality processing function, to obtain the related data of interrupt routine described in overtime moment of second timer.
6. the treating apparatus of CPU deadlock monitoring according to claim 5, is characterized in that, also comprises:
Preserve module, for obtaining after the related data of described task program, the related data of this task program is saved in the high memory of CPU; Or, obtaining after the related data of described interrupt routine, the related data of this interrupt routine is saved in the high memory of CPU.
7. according to the treating apparatus of the CPU deadlock monitoring described in claim 5 to 6 any one, it is characterized in that,
The related data of described task program comprises the following data of task program: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer;
The related data of described interrupt routine comprises the following data of interrupt routine: data, function and call stack retrieve data thereof near data, PC pointer near CPU context data, stack pointer.
8. the treating apparatus of CPU deadlock monitoring according to claim 6, is characterized in that, also comprises:
Configuration module,, and is saved to this interrupt routine related data in the high memory of CPU to obtain described interrupt routine related data for configure hardware WatchDog Timer.
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902423A (en) * | 2012-12-26 | 2014-07-02 | 联芯科技有限公司 | Method and system for debugging crash of central processor |
| CN104834643B (en) * | 2014-02-11 | 2019-06-14 | 腾讯科技（深圳）有限公司 | A kind of quick common gateway interface file analysis method and apparatus |
| CN104794016A (en) * | 2015-04-23 | 2015-07-22 | 惠州Tcl移动通信有限公司 | Mobile terminal crash testing and processing method and system |
| CN105718326B (en) * | 2016-01-27 | 2018-12-11 | 惠州市德赛西威汽车电子股份有限公司 | The restorability test method of embedded system |
| CN105760305A (en) * | 2016-03-09 | 2016-07-13 | 上海博达数据通信有限公司 | Real-time system monitoring method under linux |
| CN106021069A (en) * | 2016-06-01 | 2016-10-12 | 北京金山安全软件有限公司 | CPU occupation detection method, device and equipment |
| CN107423151A (en) * | 2017-03-28 | 2017-12-01 | 上海斐讯数据通信技术有限公司 | The method and apparatus that a kind of Wireless Access Point System recovers |
| CN109032822B (en) * | 2017-06-09 | 2024-01-09 | 中兴通讯股份有限公司 | Method and device for storing crash information |
| CN107894930A (en) * | 2017-10-19 | 2018-04-10 | 湖南国科微电子股份有限公司 | The method and apparatus of deadlock status data passive recovery processing |
| CN111124730B (en) * | 2019-12-20 | 2024-01-23 | 浪潮商用机器有限公司 | Error positioning method and device of server and computer storage medium |
| CN113742113A (en) * | 2020-05-29 | 2021-12-03 | 上海微电子装备（集团）股份有限公司 | Embedded system health management method, equipment and storage medium |
| CN111984969A (en) * | 2020-08-20 | 2020-11-24 | 北京金山云网络技术有限公司 | Fault alarm method and device of virtual machine and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1400529A (en) * | 2001-07-30 | 2003-03-05 | 华为技术有限公司 | Fault location method of real-time embedding system |
| CN101089823A (en) * | 2006-06-12 | 2007-12-19 | 深圳市研祥智能科技股份有限公司 | Computer watchdog device and its working method |
| CN100395722C (en) * | 2003-12-24 | 2008-06-18 | 华为技术有限公司 | Method for preserving abnormal state information of control system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006338605A (en) * | 2005-06-06 | 2006-12-14 | Denso Corp | Program failure monitoring method and program failure monitoring device |
-
2011
- 2011-11-23 CN CN201110375754.1A patent/CN102521098B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1400529A (en) * | 2001-07-30 | 2003-03-05 | 华为技术有限公司 | Fault location method of real-time embedding system |
| CN100395722C (en) * | 2003-12-24 | 2008-06-18 | 华为技术有限公司 | Method for preserving abnormal state information of control system |
| CN101089823A (en) * | 2006-06-12 | 2007-12-19 | 深圳市研祥智能科技股份有限公司 | Computer watchdog device and its working method |
Non-Patent Citations (2)
| Title |
|---|
| 单片机应用系统的软件抗干扰技术;张翔;《广西工学院报》;20010630;第12卷(第2期);参见第52页 * |
| 张翔.单片机应用系统的软件抗干扰技术.《广西工学院报》.2001,第12卷(第2期),参见第52页. * |
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