CN102520913A - Parallel branch prediction device of packet-based updating historical information - Google Patents
Parallel branch prediction device of packet-based updating historical information Download PDFInfo
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Abstract
The invention discloses a parallel branch prediction device of packet-based updating historical information, which comprises a group branch historical shift register, a branch result memory, an instruction pre-coding unit, a branch instruction labeling unit and a branch acknowledgement message cache unit, wherein the group branch historical shift register is used for caching group branch jump information of latest-executed j group branch instructions; the branch result memory is used for storing a branch jump result acknowledged by the backward-stage production line and outputting branch prediction information; the instruction pre-coding unit is used for selecting one bit of branch prediction information as a branch prediction result of branch instructions from I bits of branch prediction information at the output end of the branch result memory if the branch instructions are obtained through pre-coding; the branch instruction labeling unit is used for grouping and labeling the pre-coded branch instructions; and the branch acknowledgement message cache unit is used for monitoring an acknowledgement condition of the backward-stage production line to the branch instructions and updating the group branch historical shift register by using the group branch jump information of one group of branch instructions when the group of branch instructions is acknowledged by the backward-stage production line. The parallel branch prediction device is used for processing a plurality of branch instructions in parallel and precisely predicting the branch result under a high clock frequency.
Description
Technical field
The present invention relates to a kind of branch prediction device, thereby relate in particular to a kind of based on divide into groups upgrading the branch prediction device that historical information can many branch instructions of parallel processing.
Background technology
In the design of microprocessor, along with the requirement of high-end applications to processor performance improves constantly, the frequency of processor is also increasingly high accordingly.Increase pipeline series and be promote processor frequencies main and also be one of effective and efficient manner.But dark streamline has also brought many challenges to design, is exactly one of them to the processing of branch instruction.Level production line just can obtain because the correct result of branch instruction is only in the back; If pause streamline; Produce the continued executive routine up to branch outcome; Will produce many streamline bubbles, and the probability that branch instruction occurs in program is very high, this has just brought fatal infringement to performance of processors.Branch prediction can address this problem to a great extent, and branch prediction is just predicted the result of branch instruction in the streamline prime through various forecasting mechanisms; And make processor speculate carry out the program after the branch instruction according to prediction result; Level production line is checked predicting the outcome of branch instruction in the back, if the branch prediction mistake occurs, then need empty processor pipeline; Address instruction fetch from correct restarts executive routine.Therefore, high-precision branch prediction mechanism becomes and improves the processor performance key.
Present branch prediction techniques mainly is based on the secondary branch prediction of branch history information; With the instruction is that granularity is divided branch history information; The redirect result of some branch instructions before the branch instruction that is processed is as the historical information of this branch instruction, and the program counter information in conjunction with this branch instruction itself draws the branch information index; Remove index branching pattern table, from the branching pattern table, obtain branch prediction results.This mode has the better prediction accuracy through practice examining when the phase is only handled the wall scroll branch instruction weekly.But improve constantly along with what processor performance was required, the appearance of superscalar processor becomes inevitable, and increasing processor can obtain many instructions simultaneously, and to many instruction parallel decodings, emission and execution.Therefore processor need solve many branch instructions of each period treatment and obtain the problem of branch prediction results; If according to traditional branch prediction method; The redirect result of last branch instruction is as the historical information of a back branch instruction; Then only after obtaining the branch prediction information result of last branch instruction, just can obtain the historical information of a back instruction, and then obtain the branch prediction results of a back instruction.The process of such serial can produce very big time-delay, and this can't realize in current high-frequency processor.
Summary of the invention
Under high clock frequency, can't handle the deficiency of many branch instructions simultaneously in order to overcome existing branch prediction device, the present invention provide a kind of under high clock frequency many branch instructions of parallel processing and to branch outcome carry out accurately predicting based on the branch prediction device that divide into groups to upgrade historical information.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of based on the parallel branch prediction unit that divides into groups to upgrade historical information, said parallel branch prediction unit comprises:
Group of branches history, bit wide are the j position, in order to the group of branches jump information of the nearest j group of branches of buffer memory instruction, and read index and write index for the branch outcome storer provides;
The branch outcome storer is connected in group of branches history output terminal, in order to the branch redirect result of storage through level production line affirmation later, and the output branch prediction information, the IO port bit wide of storer is the i position, the degree of depth of storer is 2
jIndividual list item;
Instruct preparatory decoding unit; Be connected in the output terminal of branch outcome storer, at most can be to the parallel decoding in advance of m bar instruction, wherein; M≤i; To every instruction,, from the i position branch prediction information of branch outcome storer output terminal, choose 1 branch prediction results as this branch instruction if decoding draws it for branch instruction in advance;
The branch instruction indexing unit is connected in the output terminal of the preparatory decoding unit of instruction, the branch instruction after the preparatory decoding is divided into groups, and every group of article one and the last item branch instruction are marked;
Branch's confirmation buffer unit; Be connected in the input end of group of branches history; In order to monitor the affirmation situation of back level production line to branch instruction; When the back level production line had been confirmed group of branches instruction, with the group of branches jump information update group branch history shift register of this group of branches instruction, the group of branches jump information specifically obtained with exclusive disjunction through carrying out the logic step-by-step to the correct branch outcome of each bar branch instruction in this group.
Further; Said branch confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; If the branch prediction mistake does not take place in the back level production line when confirming branch instruction; Then the group of branches history reads i position branch prediction information as the index of reading of branch outcome storer at every turn from the branch outcome storer.
Further again; Branch's confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; If the branch prediction mistake does not take place in the back level production line when confirming branch instruction; Then the group of branches history is as the index of writing of branch outcome storer, and the n position in the usefulness programmable counter of this branch instruction is chosen 1 as selecting signal from the i position of branch outcome memory input simultaneously; The correct branch outcome of this branch instruction is write the branch outcome storer, and wherein the relation of n and i is: i=2
n
Preferably, said parallel branch prediction unit is an elementary cell with the instruction of once looking ahead, many instructions of parallel processing; The instruction of wherein once looking ahead is minimum to contain 1 instruction, contains the instruction of m bar at most, wherein; M≤i, the instruction definition of once looking ahead are an instruction bag.
Further again, in the preparatory decoding unit of said instruction, to the parallel decoding in advance of each bar instruction in the instruction bag; If decoding draws branch instruction in advance; Then with the n position in the programmable counter of this branch instruction as selecting signal, select branch prediction results, wherein the relation of n and i is: i=2
n
Further; In the said branch instruction indexing unit; If decoding draws in the instruction bag and contains branch instruction in advance, then: the branch instruction indexing unit is stamped the group labeling head to article one branch instruction in the instruction bag, has the branch instruction of organizing labeling head and is defined as a group branch instruction; If have at least predicting the outcome of a branch instruction to be redirect in the instruction bag; Then the branch instruction indexing unit predicts the outcome to article one in the instruction bag and stamps group tail tag note for the branch instruction of redirect; If all predicting the outcome of branch instruction are not redirect in the instruction bag; Then the branch instruction indexing unit is stamped group tail tag note to the last item branch instruction wherein, and the branch instruction that has group tail tag note is defined as group tail branch instruction.
Preferably; In the said branch instruction indexing unit; All instructions before the group tail branch instruction in the instruction bag and group tail branch instruction as one group of instruction, are instructed branch prediction results and the cue mark information that is comprised together with this group, mail to down level production line together; Instruction during the branch instruction indexing unit will instruct and wrap after the group tail branch instruction abandons.
In the said branch confirmation buffer unit, monitoring back level production line is to the affirmation situation of branch instruction, if the branch instruction that the back level production line is confirmed is a group branch instruction, then this kind situation is defined as a group branch and confirms; If the branch instruction of back level production line affirmation is redirect for the correct branch outcome of group tail branch instruction or this instruction, then this kind situation is defined as the affirmation of group tail branch; Observation process comprises:
If an only generation group branch confirmed when the back level production line was confirmed branch instruction, then the correct branch outcome of this branch instruction is got up as the branch history information buffer memory;
If only generation group tail branch confirmed when the back level production line was confirmed branch instruction; Then the correct branch outcome of this branch instruction is done the same exclusive disjunction of logic with the branch history information that is buffered; Obtain the group of branches jump information of group of branches instruction; And this group of branches jump information write the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one;
Both not generation group branch's affirmations when if the back level production line is confirmed branch instruction; Also not generation group tail branch confirms; Then the correct branch outcome of this branch instruction is done the same exclusive disjunction of logic with the branch history information that is buffered; Obtain new branch history information, and with this branch history information buffer memory, the branch history information that is buffered before covering;
If branch's affirmation of generation group simultaneously and group tail branch confirmed when the back level production line was confirmed branch instruction; The group of branches jump information of then directly the correct branch outcome of this branch instruction being instructed as a group of branches; Be written to the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one.
Among the present invention, above-mentioned j, i, m, n are natural number, and wherein: the value of j can be for any greater than zero natural number; The value of i is 2 integer power, promptly can be 2,4,8,16 or the like, by that analogy; The value of m can be any natural number less than i; The value of n is that the relation of natural number and i is: i=2
nIf promptly the value of i is 4, then the value of n is 2, if the value of i is 8, then the value of n is 3, by that analogy.
Technical conceive of the present invention is: one group of instruction with the processor parallel processing is that granularity is divided branch history information; And then be that a base unit upgrades historical information and safeguards with one group of instruction; Therefore when processor is handled many branch instructions simultaneously; Can many branch instructions be regarded as one group of instruction; The historical information of all branch instructions is consistent in the instruction on the same group; So just the traditional serial processing procedure is changed into parallel processing procedure, the time delay of many branch instructions being carried out prediction processing is the same with the time delay that a branch instruction is carried out prediction processing, and this has just guaranteed that processor can make accurate predicted operation to branch instruction under high-frequency.
Beneficial effect of the present invention mainly shows: 1) guaranteeing to have promoted the branch instruction predictions precision under the high-frequency prerequisite, parallel many branch instructions are being handled and branch prediction, rather than serial ground begins to predict that next bar instructs after predict an instruction; 2) save hardware resource, through branch instruction is divided into groups, every group of instruction occupies a branch history information, rather than every instruction occupies a branch history information, saved the shift register resource that writes down branch history information.
Description of drawings
Fig. 1 is the general frame figure of first embodiment of the invention.
Fig. 2 is the synoptic diagram of the composition organizational form of instruction bag in the first embodiment of the invention.
Fig. 3 is the structural drawing of the preparatory decoding unit of instruction in the first embodiment of the invention.
Fig. 4 is the structural drawing that the branch instruction indexing unit is realized a marker set branch instruction in the first embodiment of the invention.
Fig. 5 is the structural drawing that the branch instruction indexing unit is realized marker set tail branch instruction in the first embodiment of the invention.
Fig. 6 is the structural drawing of branch's confirmation buffer unit in the first embodiment of the invention.
Fig. 7 is 4 synoptic diagram that instruction is wrapped that first embodiment of the invention is handled when operation.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further statement.
Please refer to shown in Figure 1ly, be the structure chart of first embodiment of the invention.This device provides branch prediction results for branch instruction in processor; This device is an elementary cell with the instruction of once looking ahead, many instructions of parallel processing, and the instruction of wherein once looking ahead is minimum to contain 1 instruction; Contain the instruction of m bar at most, the instruction definition of once looking ahead is an instruction bag.
As shown in fig. 1, this device comprises the group of branches history, and the branch outcome storer instructs preparatory decoding unit, branch instruction indexing unit, branch's confirmation buffer unit.
Wherein, The bit wide of group of branches history is the j position; Wherein storing the group of branches jump information of the j group of branches instruction of carrying out recently; The group of branches jump information of each branch instruction occupies 1, and the group of branches history is exported its value, reading index and writing index as the branch outcome storer.
The branch outcome storer is connected in the output terminal of group of branches history, the redirect result of branch of warp level production line affirmation later in the stored programme, if the redirect result of branch 1 then representes redirect, if 0, then represent not redirect.Branch outcome storer output branch prediction information, the IO port bit wide of branch outcome storer is the i position, so the branch prediction information output of i position will be arranged at every turn; The degree of depth of branch outcome storer is 2
jIndividual list item comes index with the j hyte branch jump information of group of branches history output.
Instruct preparatory decoding unit to be connected in the output terminal of branch outcome storer; At most can be to the parallel decoding in advance of m bar instruction; Decoding draws branch instruction wherein in advance, and from the branch prediction information of branch outcome storer output terminal, chooses the branch prediction results of branch instruction, because the total i position of the output terminal of branch's storer branch prediction information; So instruct the preparatory decoding unit simultaneously treated instruction strip number to be m; Here m≤i, so just can guarantee every branch instruction from the diverse location of branch outcome storer output terminal to its branch prediction results, thereby avoid the phase mutual interference between the different branch instructions.To every branch instruction; Instruct preparatory decoding unit with the n position in the programmable counter of this branch instruction as selecting signal; From the i position branch prediction information of branch outcome storer output terminal, choose 1 branch prediction results as this branch instruction, wherein the relation of n and i is: i=2
n
The branch instruction indexing unit is connected in the output terminal of the preparatory decoding unit of instruction; All instructions to preparatory decode results in the instruction bag is a branch instruction are divided into groups; And every group of article one branch instruction stamped the group labeling head, every group of the last item branch instruction stamped group tail tag note.If draw in the instruction bag through preparatory decoding and to contain branch instruction, then: the branch instruction indexing unit is stamped the group labeling head to article one branch instruction in the instruction bag, has the branch instruction of organize labeling head and is defined as and organizes a branch instruction; If have at least predicting the outcome of a branch instruction to be redirect in the instruction bag; Then the branch instruction indexing unit predicts the outcome to article one in the instruction bag and stamps group tail tag note for the branch instruction of redirect; If all predicting the outcome of branch instruction are not redirect in the instruction bag; Then the branch instruction indexing unit is stamped group tail tag note to the last item branch instruction wherein, and the branch instruction that has group tail tag note is defined as group tail branch instruction.All instructions during the branch instruction indexing unit will instruct and wrap before the group tail branch instruction and group tail branch instruction are as one group of instruction, and branch prediction results and cue mark information together with this group instruction is comprised mail to down level production line together; Instruction during the branch instruction indexing unit will instruct and wrap after the group tail branch instruction abandons.
Branch's confirmation buffer unit is connected in the input end of group of branches history; Monitoring back level production line is to the affirmation situation of branch instruction; When the back level production line has been confirmed group of branches instruction; Branch's confirmation buffer unit is with the group of branches jump information update group branch history shift register of this group of branches instruction, and the group of branches jump information specifically obtains with exclusive disjunction through carrying out the logic step-by-step to the correct branch outcome of each bar branch instruction in this group.Branch confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction, if the branch instruction that the back level production line is confirmed is a group branch instruction, then this kind situation is defined as a group branch and confirms; If the branch instruction of back level production line affirmation is redirect for the correct branch outcome of group tail branch instruction or this instruction, then this kind situation is defined as the affirmation of group tail branch.Branch's confirmation buffer unit is confirmed according to a group branch and group tail branch confirms that the situation occurred of both of these case carries out concrete operations: an only generation group branch confirms when confirming branch instruction as if the back level production line, then the correct branch outcome of this branch instruction is got up as the branch history information buffer memory; If only generation group tail branch confirmed when the back level production line was confirmed branch instruction; Then the correct branch outcome of this branch instruction is done the same exclusive disjunction of logic with the branch history information that is buffered; Obtain the group of branches jump information of group of branches instruction; And this group of branches jump information write the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one; Both not generation group branch's affirmations when if the back level production line is confirmed branch instruction; Also not generation group tail branch confirms; Then the correct branch outcome of this branch instruction is done the same exclusive disjunction of logic with the branch history information that is buffered; Obtain new branch history information, and with this branch history information buffer memory, the branch history information that is buffered before covering; If branch's affirmation of generation group simultaneously and group tail branch confirmed when the back level production line was confirmed branch instruction; The group of branches jump information of then directly the correct branch outcome of this branch instruction being instructed as a group of branches; Be written to the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one.
Branch's confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; If the branch prediction mistake does not take place in the back level production line when confirming branch instruction; Then the group of branches history reads i position branch prediction information as the index of reading of branch outcome storer at every turn from the branch outcome storer; If the branch prediction mistake takes place in the back level production line when confirming branch instruction; Then with the write index of group of branches history as the branch outcome storer; N in the usefulness programmable counter of this branch instruction is as selecting signal simultaneously; The position is chosen 1 from the i position of branch outcome memory input, the correct branch outcome of this branch instruction is write the branch outcome storer, and wherein the relation of n and i is: i=2
n
Please refer to shown in Figure 2ly, be the organizational form of the handled instruction bag of first embodiment of the invention.The base unit that the instruction bag is handled for the present invention, i.e. the present invention once can be to all the instruction parallel processings in the instruction bag.An instruction package definition is the instruction that processor is once looked ahead, and the instruction number that processor once can be looked ahead among the present invention is minimum to be 1 instruction, is the instruction of m bar, wherein m≤i at most.So as shown in Figure 2, the possible organizational form of instruction bag is: only comprise 1 instruction, promptly instruct 1; Comprise 2 instructions, promptly instruct 1, instruction 2; Increase progressively successively, comprise the instruction of m bar at most, promptly instruct 1, instruction 2 is up to instruction m.
Please, be the concrete implementation of the preparatory decoding unit of instruction in the first embodiment of the invention with reference to shown in Figure 3.Instruct preparatory decoding unit to be connected in the output terminal of branch outcome storer.Because an instruction bag has the instruction of m bar at most, thus instruct preparatory decoding unit to comprise the m sub-cells, subelement 1, subelement 2 is up to subelement m, and is as shown in Figure 3.Each subelement is responsible for an instruction is deciphered in advance, and whether decipher in advance and draw this instruction is branch instruction, is specially the instruction 1 in the subelement correspondence instruction bag, subelement 2 corresponding instructions 2 of instructing in wrapping, by that analogy.Each sub-cells concurrent working is to the parallel decoding in advance of all instructions in the instruction bag.Each subelement is all with the i position branch prediction information of the branch outcome storer output terminal input signal as self.Fig. 3 is the structure of clear subelement 1 specifically; The order code of instruction 1 was as input during decoding logic in the subelement 1 will be instructed and wrapped; To instructing 1 to decipher in advance, if decoding obtains instructing 1 to be branch instruction in advance, decoding logic is drawn high branch's useful signal; Otherwise this signal is dragged down, and decoding logic inputs to this signal at one end of branch filter and door; Instruct n position in 1 the programmable counter as the selection signal of information of forecasting selector switch (i=2 wherein simultaneously
n), from the i position branch prediction information of branch outcome storer output terminal, choose 1 branch prediction information, this information inputs to the other end of branch filter and door, wherein i=2
nIf instruction 1 be a branch instruction, then branch filter is a high level with the input end that door is connected branch's useful signal, thus branch filter and output be exactly the value that the other end is imported, promptly instruct 1 branch prediction results; If instruct 1 not to be branch instruction, then branch filter is a low level with the input end that door is connected branch's useful signal, so the output perseverance of branch filter and door is 0, it is invalid promptly should to export the result.Subelement 2 is the same with subelement 1 up to the structure of subelement m; Unique difference is that each sub-cells is deciphered its corresponding instruction in advance; And with the n position in the programmable counter of corresponding instruction as selecting signal, from the i position branch prediction information of branch outcome storer output terminal, choose 1 branch prediction information.The branch's useful signal and the branch prediction results of each subelement output command adapted thereto supply the branch instruction indexing unit to use.
Please refer to shown in Figure 4ly, be the concrete realization logic of a branch instruction indexing unit marker set branch instruction in the first embodiment of the invention.The branch instruction indexing unit is connected in the output terminal of the preparatory decoding unit of instruction, and branch's useful signal that each bar of exporting according to the preparatory decoding unit of instruction instructs comes a marker set branch instruction.An instruction bag can comprise the instruction of m bar at most, and this m bar instruction all might become a group branch instruction, representes with m root signal respectively, and is as shown in Figure 4.Instruction 1 is exactly branch's useful signal self of instruction 1 for the realization logic of a group branch instruction; Instruction 2 for the conditions of a group branch instruction be instruction 1 for branch instruction, instruct 2 to be branch instruction simultaneously, realize that specifically logic is with carrying out logic and operation with branch's useful signal of instruction 2 after branch's useful signal negate of instruction 1; By that analogy; Instruction m is instruction 1 for the condition of a group branch instruction; Instruction 2 all is not a branch instruction up to instruction (m-1); Instruct the m to be branch instruction simultaneously, specifically realize logic be with instruction 1 to branch's useful signal of instruction (m-1) separately after the negate with instruct branch's useful signal of m to carry out logic and operation.
Please, be the concrete realization logic of branch instruction indexing unit marker set tail branch instruction in the first embodiment of the invention with reference to shown in Figure 5.The branch instruction indexing unit is connected in the output terminal of the preparatory decoding unit of instruction, and the branch prediction results of branch's useful signal that each bar of exporting according to the preparatory decoding unit of instruction instructs and the instruction of each bar is come marker set tail branch instruction.An instruction bag can comprise the instruction of m bar at most, and this m bar instruction all might become group tail branch instruction, representes with m root signal respectively, and is as shown in Figure 5.The mark of group tail branch instruction can be divided into two kinds of situation; A kind of situation is that to have branch prediction results in the instruction bag be the branch instruction of redirect; Another kind of situation is that not have branch prediction results in the instruction bag be the branch instruction of redirect; Shown in Fig. 4 (A); Coming whether to have at least one branch prediction results in presentation directives's bag through a signal is the branch instruction of redirect, if this signal is the branch instruction of redirect for not having branch prediction results in the high then presentation directives bag, this signal carries out logic and operation through the branch's useful signal with each bar instruction with corresponding branch prediction results; Again the m that an obtains intermediate result separately after the negate, is carried out logic and operation once more and obtained.Fig. 4 (B) has explained and will instruct 1 to be labeled as the logic of organizing the tail branch instruction; Be divided into two kinds of situation, first kind of situation is that instruction 1 is a branch instruction that branch prediction results is redirect, and second kind of situation is not predict the outcome in the instruction bag to be the branch instruction of redirect; And instruct 1 to be branch instruction; Instruction 2 be a branch instruction all to instruction m, realizes that specifically logic is: will instruct branch's useful signal of 1 and instruct 1 branch prediction results to carry out logic and operation, and obtain intermediate result 1; Instruction 2 is not predicted the outcome to the signal of the branch instruction of redirect and instructs branch's useful signal of 1 to carry out logic and operation after the negate with in the presentation directives bag separately to branch's useful signal of instruction m, obtain intermediate result 2; Intermediate result 1 and intermediate result 2 are carried out the logical OR computing.Fig. 4 (C) has explained and has instructed 2 to be labeled as the logic of organizing the tail branch instruction; Be divided into two kinds of situation, first kind of situation is that instruction 2 is the branch instruction of redirect for article one branch prediction results in the instruction bag, and second kind of situation is not predict the outcome in the instruction bag to be the branch instruction of redirect; And instruct 2 to be branch instruction; Instruction 3 is not a branch instruction all to instruction m, realizes that specifically logic is: will instruct 1 branch's useful signal and branch prediction results to carry out logic and operation, and obtain intermediate result 1; The branch's useful signal and the branch prediction results of instruction 2 are carried out logic and operation; Obtain intermediate result 2,, obtain intermediate result 3 carrying out logic and operation with intermediate result 2 after intermediate result 1 negate; Instruction 3 is not predicted the outcome to the signal of the branch instruction of redirect and instructs branch's useful signal of 2 to carry out logic and operation after the negate with in the presentation directives bag separately to branch's useful signal of instruction m, obtain intermediate result 4; Intermediate result 3 and intermediate result 4 are carried out the logical OR computing.By that analogy, each bar instruction considers according to above-mentioned two kinds of situation all that for group tail branch instruction Fig. 4 (D) has explained that instruction m is labeled as the logic of group tail branch instruction; Be divided into two kinds of situation; First kind of situation is that instruction m is the branch instruction of redirect for article one branch prediction results in the instruction bag, and second kind of situation is not predict the outcome in the instruction bag to be the branch instruction of redirect, and instruction m is a branch instruction; The concrete logic that realizes is: will instruct the 1 branch's useful signal to instruction (m-1) to carry out logic and operation with corresponding branch prediction results; Obtain (m-1) individual intermediate result,, branch's useful signal and the branch prediction results of instruction m are carried out logic and operation this (m-1) individual intermediate result negate separately; Carry out logic and operation with the intermediate result that obtains with through (m-1) individual intermediate result of inversion operation, obtain intermediate result 1; The signal that does not predict the outcome during branch's useful signal and the presentation directives of instruction m wrapped to the branch instruction of redirect carries out logic and operation, obtains intermediate result 2; Intermediate result 1 and intermediate result 2 are carried out the logical OR computing.
Please refer to shown in Figure 6ly, be the concrete implementation of branch's confirmation buffer unit in the first embodiment of the invention.Branch's confirmation buffer unit specifically comprises: branch history information working storage, logic be with the exclusive disjunction door, the branch history information selector switch.Branch history information working storage output branch history information, this branch history information input logic is with an end of exclusive disjunction door; The correct branch outcome input logic of warp level production line affirmation later is with the other end of exclusive disjunction door; Logic is input to an end of branch history selector switch with the output result of exclusive disjunction door; Be directly inputted to the other end of branch history selector switch through the correct branch outcome of level production line affirmation later; The branch history selector switch chooses one the tunnel from the two paths of signals of input end; Upgrade the branch history working storage; And in the back when level production line has confirmed that a group of branches is instructed, with the signal of branch history selector output end as the group of branches jump information, update group branch history shift register.Branch's confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; If an only generation group branch confirmed when the back level production line was confirmed branch instruction; Then branch history selector switch gating through after the correct branch outcome confirmed of level production line; And with this signal as branch history information, be cached in the branch history information working storage; If only generation group tail branch confirmed when the back level production line was confirmed branch instruction; Then branch history selector switch gate logic is with the output signal of exclusive disjunction door; And with the group of branches jump information of signal as group of branches instruction; Write the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one; Both not generation group branch's affirmations when if the back level production line is confirmed branch instruction; Also not generation group tail branch confirms; Then branch history selector switch gate logic is with the output signal of exclusive disjunction door; And with this signal as branch history information, be cached in the branch history information working storage branch history information that is buffered before covering; If branch's affirmation of generation group simultaneously and group tail branch confirmed when the back level production line was confirmed branch instruction; Then branch history selector switch gating through after the correct branch outcome confirmed of level production line; And with the group of branches jump information of this signal as group of branches instruction; Write the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one.
Please with reference to shown in Figure 7, for 4 instructions that first embodiment of the invention is handled when moving are wrapped.Explanation for ease supposes that here each instruction bag all contains 4 instructions: instruction 1, instruction 2, instruction 3 and instruction 4.
Shown in Fig. 7 (A), the instruction 1 in the instruction bag 1 is a branch instruction, and its branch prediction results is not redirect; Instruction 3 is a branch instruction, and its branch prediction results is not redirect; Instruction 2 is not a branch instruction with instruction 4.Instruct preparatory decoding unit will instruct 1 with instruction 3 programmable counter in the n position as selecting signal, from the i position branch prediction information of branch outcome storer output terminal, choose 1 branch prediction results respectively as the respective branches instruction.The branch instruction indexing unit comes marker set head and group tail branch instruction based on the branch's useful signal and the branch prediction results of the preparatory decoding unit output of instruction; To instruct 1 to be labeled as a group branch instruction, will instruct 3 to be labeled as group tail branch instruction, and will instruct 1; Instruction 2; Instruction 3 is as one group of instruction, and branch prediction results and cue mark information together with this group instruction is comprised mail to down level production line together; Instruction during the branch instruction indexing unit will instruct and wrap simultaneously after the instruction 3 abandons.Branch's confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; When the back level production line is confirmed instruction 1; Generation group branch confirms, so branch's confirmation buffer unit will instruct 1 correct branch outcome as the branch history information buffer memory; When after be that streamline is when confirming instruction 3; Generation group tail branch confirms; Therefore branch's confirmation buffer unit will instruct 3 correct branch outcome and the branch history information that is buffered to do the same exclusive disjunction of logic; Obtain the group of branches jump information of group of branches instruction, and this group of branches jump information is write the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one.
Shown in Fig. 7 (B), instruction 1 is a branch instruction in the instruction bag 2, and its branch prediction results is not redirect; Instruction 2 is a branch instruction, and its branch prediction results is not redirect; Instruction 3 is a branch instruction, and its branch prediction results is redirect.Instruct preparatory decoding unit will instruct 1, the n position in the programmable counter of instruction 2 and instruction 3 is chosen 1 branch prediction results as the respective branches instruction respectively as selecting signal from the i position branch prediction information of branch outcome storer output terminal.The branch instruction indexing unit comes marker set head and group tail branch instruction based on the branch's useful signal and the branch prediction results of the preparatory decoding unit output of instruction; To instruct 1 to be labeled as a group branch instruction, will instruct 3 to be labeled as group tail branch instruction, and will instruct 1; Instruction 2; Instruction 3 is as one group of instruction, and branch prediction results and cue mark information together with this group instruction is comprised mail to down level production line together; Instruction during the branch instruction indexing unit will instruct and wrap simultaneously after the instruction 3 abandons.Branch's confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; When the back level production line is confirmed instruction 1; Generation group branch confirms, so branch's confirmation buffer unit will instruct 1 correct branch outcome as the branch history information buffer memory; When the back level production line is confirmed instruction 2; Both a not generation group branch confirmed; Also not generation group tail branch confirms, so the branch information buffer unit will instruct 2 correct branch outcome and the branch history information that is buffered to do the same exclusive disjunction of logic, obtains new branch history information; And with this branch history information buffer memory, the branch history information that is buffered before covering; When the back level production line is confirmed instruction 3; Generation group tail branch confirms; Therefore branch's confirmation buffer unit will instruct 3 correct branch outcome and the branch history information that is buffered to do the same exclusive disjunction of logic; Obtain the group of branches jump information of group of branches instruction, and this group of branches jump information is write the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one.
Shown in Fig. 7 (C), instruction 3 is a branch instruction in the instruction bag 3, and its branch prediction results is not redirect; Instruction 1, instruction 2 all is not a branch instruction with instruction 4.Instruct preparatory decoding unit will instruct n position in 3 the programmable counter, from the i position branch prediction information of branch outcome storer output terminal, choose 1 as its branch prediction results as selecting signal.The branch instruction indexing unit comes marker set head and group tail branch instruction based on the branch's useful signal and the branch prediction results of the preparatory decoding unit output of instruction; To instruct 3 to be labeled as a group branch instruction, will instruct 3 to be labeled as group tail branch instruction simultaneously, and will instruct 1; Instruction 2; Instruction 3 is as one group of instruction, and branch prediction results and cue mark information together with this group instruction is comprised mail to down level production line together; Instruction during the branch instruction indexing unit will instruct and wrap simultaneously after the instruction 3 abandons.Branch's confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; When the back level production line is confirmed instruction 3; The branch of generation group simultaneously confirms and group tail branch confirms; Therefore branch's confirmation buffer unit directly will instruct the group of branches jump information that 3 correct branch outcome is instructed as a group of branches, be written to the most significant digit or the lowest order of group of branches history, and the group of branches history correspondingly moves to left or moves to right one.
Shown in Fig. 7 (D), instruction 2 is a branch instruction in the instruction bag 3, and its branch prediction results is redirect; Instruction 3 is a branch instruction, and its branch prediction results is not redirect; Instruction 1 is not a branch instruction with instruction 4.Instruct preparatory decoding unit will instruct 2 with instruction 3 programmable counter in the n position as selecting signal, from the i position branch prediction information of branch outcome storer output terminal, choose 1 branch prediction results as the respective branches instruction.The branch instruction indexing unit comes marker set head and group tail branch instruction based on the branch's useful signal and the branch prediction results of the preparatory decoding unit output of instruction; To instruct 2 to be labeled as a group branch instruction; To instruct 2 to be labeled as group tail branch instruction simultaneously; And will instruct 1 with instruction 2 as one group of instruction, instruct branch prediction results and the cue mark information that is comprised together with this group, mail to down level production line together; Instruction during the branch instruction indexing unit will instruct and wrap simultaneously after the instruction 2 abandons.Branch's confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; When the back level production line is confirmed instruction 2; The branch of generation group simultaneously confirms and group tail branch confirms; Therefore branch's confirmation buffer unit directly will instruct the group of branches jump information that 2 correct branch outcome is instructed as a group of branches, be written to the most significant digit or the lowest order of group of branches history, and the group of branches history correspondingly moves to left or moves to right one.
Claims (8)
1. one kind based on the parallel branch prediction unit that divide into groups to upgrade historical information, it is characterized in that said parallel branch prediction unit comprises:
Group of branches history, bit wide are the j position, the group of branches jump information of the j group of branches instruction of carrying out recently in order to buffer memory, and read index and write index for the branch outcome storer provides;
The branch outcome storer is connected in group of branches history output terminal, in order to the branch redirect result of storage through level production line affirmation later, and the output branch prediction information, the IO port bit wide of storer is the i position, the degree of depth of storer is 2
jIndividual list item;
Instruct preparatory decoding unit; Be connected in the output terminal of branch outcome storer, at most can be to the parallel decoding in advance of m bar instruction, wherein; M≤i; To every instruction,, then from the i position branch prediction information of branch outcome storer output terminal, choose 1 branch prediction results as this branch instruction if decoding draws it for branch instruction in advance;
The branch instruction indexing unit is connected in the output terminal of the preparatory decoding unit of instruction, the branch instruction after the preparatory decoding is divided into groups, and every group of article one and the last item branch instruction are marked;
Branch's confirmation buffer unit; Be connected in the input end of group of branches history; In order to monitor the affirmation situation of back level production line to branch instruction; When the back level production line had been confirmed group of branches instruction, with the group of branches jump information update group branch history shift register of this group of branches instruction, the group of branches jump information specifically obtained with exclusive disjunction through carrying out the logic step-by-step to the correct branch outcome of each bar branch instruction in this group.
2. as claimed in claim 1 based on the parallel branch prediction unit that divides into groups to upgrade historical information; It is characterized in that; Said branch confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction; If the back level production line when confirming branch instruction the branch prediction mistake does not take place, then the group of branches history reads i position branch prediction information as the index of reading of branch outcome storer at every turn from the branch outcome storer.
3. as claimed in claim 1 based on the parallel branch prediction unit that divides into groups to upgrade historical information; It is characterized in that; Said branch confirmation buffer unit monitoring back level production line is to the affirmation situation of branch instruction, if the back level production line when confirming branch instruction the branch prediction mistake takes place, then the group of branches history is as the index of writing of branch outcome storer; N position in the usefulness programmable counter of this branch instruction is as selecting signal simultaneously; From the i position of branch outcome memory input, choose 1, the correct branch outcome of this branch instruction is write the branch outcome storer, wherein the relation of n and i is: i=2
n
4. like claim 1 or 2 or 3 described parallel branch prediction units, it is characterized in that said parallel branch prediction unit is an elementary cell with the instruction of once looking ahead based on the renewal historical information of dividing into groups; Many instructions of parallel processing; The instruction of wherein once looking ahead is minimum to contain 1 instruction, contains the instruction of m bar at most, wherein; M≤i, the instruction definition of once looking ahead are an instruction bag.
5. like claim 1 or 2 or 3 described parallel branch prediction units based on the renewal historical information of dividing into groups; It is characterized in that, in the preparatory decoding unit of said instruction, the parallel decoding in advance of each bar instruction in the instruction bag; If decoding draws branch instruction in advance; Then with the n position in the programmable counter of this branch instruction as selecting signal, select branch prediction results, wherein the relation of n and i is: i=2
n
6. like claim 1 or 2 or 3 described parallel branch prediction units based on the renewal historical information of dividing into groups; It is characterized in that; In the said branch instruction indexing unit; If decoding draws in the instruction bag and contains branch instruction in advance, then: the branch instruction indexing unit is stamped the group labeling head to article one branch instruction in the instruction bag, has the branch instruction of organizing labeling head and is defined as a group branch instruction; If have at least predicting the outcome of a branch instruction to be redirect in the instruction bag; Then the branch instruction indexing unit predicts the outcome to article one in the instruction bag and stamps group tail tag note for the branch instruction of redirect; If all predicting the outcome of branch instruction are not redirect in the instruction bag; Then the branch instruction indexing unit is stamped group tail tag note to the last item branch instruction wherein, and the branch instruction that has group tail tag note is defined as group tail branch instruction.
7. as claimed in claim 6 based on the parallel branch prediction unit that divides into groups to upgrade historical information; It is characterized in that; In the said branch instruction indexing unit; All instructions before the group tail branch instruction in the instruction bag and group tail branch instruction as one group of instruction, are instructed branch prediction results and the cue mark information that is comprised together with this group, mail to down level production line together; Instruction during the branch instruction indexing unit will instruct and wrap after the group tail branch instruction abandons.
8. like claim 1 or 2 or 3 described parallel branch prediction units based on the renewal historical information of dividing into groups; It is characterized in that; In the said branch confirmation buffer unit, if the branch instruction that the back level production line is confirmed is a group branch instruction, then this kind situation is defined as a group branch and confirms; If the branch instruction of back level production line affirmation is redirect for the correct branch outcome of group tail branch instruction or this instruction, then this kind situation is defined as the affirmation of group tail branch; Observation process comprises:
If an only generation group branch confirmed when the back level production line was confirmed branch instruction, then the correct branch outcome of this branch instruction is got up as the branch history information buffer memory;
If only generation group tail branch confirmed when the back level production line was confirmed branch instruction; Then the correct branch outcome of this branch instruction is done the same exclusive disjunction of logic with the branch history information that is buffered; Obtain the group of branches jump information of group of branches instruction; And this group of branches jump information write the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one;
Both not generation group branch's affirmations when if the back level production line is confirmed branch instruction; Also not generation group tail branch confirms; Then the correct branch outcome of this branch instruction is done the same exclusive disjunction of logic with the branch history information that is buffered; Obtain new branch history information, and with this branch history information buffer memory, the branch history information that is buffered before covering;
If branch's affirmation of generation group simultaneously and group tail branch confirmed when the back level production line was confirmed branch instruction; The group of branches jump information of then directly the correct branch outcome of this branch instruction being instructed as a group of branches; Be written to the most significant digit or the lowest order of group of branches history, the group of branches history correspondingly moves to left or moves to right one.
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Effective date of registration: 20160229 Address after: 310012 A403 room, Hangzhou Neusoft building, 99 Huaxing Road, Xihu District, Zhejiang, Hangzhou, China Patentee after: Zhongtian Microsystems Co., Ltd., Hangzhou Address before: 310027 Hangzhou, Zhejiang Province, Xihu District, Zhejiang Road, No. 38, No. Patentee before: Zhejiang University |