CN102508776A - Automatic construction method for evaluation stimulus of multi-thread cross double-precision short-vector structure - Google Patents

Abstract

The invention discloses a method for automatically constructing evaluation incentives of a multi-threaded cross double-precision short vector structure, comprising the steps of: inputting the vector operation type and vector length to be evaluated; automatically creating an assembly language file with empty content used as evaluation incentives ; Write the following content into the assembly language file: multi-thread running initialization code segment, evaluation incentive control structure, multi-thread vector operation program segment, evaluation incentive synchronization structure, data segment and data segment initialization statement; constitute a complete multi-thread crossover Evaluation stimulus for double-precision short-vector structures. The invention can realize automatic batch construction of evaluation incentives, can shorten construction time, save costs, improve evaluation incentive development efficiency, and greatly facilitate processor verification and performance evaluation.

Description

Evaluation-inspired automatic construction of multithreaded interleaved double-precision short-vector structures

technical field

The invention relates to the field of processors and the field of evaluation, in particular to a method for automatically constructing evaluation incentives for multi-thread interleaving double-precision short vector structure processors.

Background technique

With the increasing integration of processor chips, it is an important development trend to implement double-precision short vector components in processor cores to support data-intensive scientific and engineering calculations. Extending the double-precision short vector unit in the multi-thread processor core can greatly improve the double-precision floating-point computing capability of the processor. The double-precision short vector component needs to implement a short vector register with a longer word length (currently Intel's AVX already supports a 256-bit short vector with a total of 4 double-precision data), and needs to implement a corresponding vector operation instruction set that supports double-precision calculations.

As shown in FIG. 1 , it is a schematic structural diagram of a multi-threaded processor core with extended double-precision short vector components. The processor core is implemented based on OpenSparc T2, and the vector processing unit (VPU) is extended in the processor core to support short vector operations of 4-way double-precision data, and multiple threads can be used concurrently. The processor core supports 8 hardware threads in the way of round-robin multi-threading, and each group of 4 hardware threads is a group; each clock cycle, the processor selects the current instruction of a thread from each group of 4 threads to execute, and the instruction can be It is a vector instruction or a scalar instruction. When an instruction of a certain thread causes the pipeline to be blocked due to reasons such as cache failure, the microprocessor with a multi-threaded cross-vector structure will fetch and execute instructions from other threads, thereby hiding the delay and ensuring that the pipeline is full. . As shown in Figure 1, the functions of each functional unit of the processor core are briefly described as follows:

1) Trapping logic unit (TLU), used to update machine state, handle exceptions and interrupts. For processor-extended VPU, TLU has also been extended accordingly to support VPU status update and exception handling.

2) The instruction fetch unit (IFU), which fetches an instruction from each group of threads every clock cycle, and sends it to the corresponding execution unit (EXU0/1, FGU, LSU, VPU) for execution according to the type of the instruction.

3) Integer execution unit (EXU0/1), responsible for executing integer operation instructions. The processor contains two integer execution units (labeled number 0 and number 1), with each of the four threads sharing an integer execution unit.

4) Floating-point and graphics unit (FGU), responsible for executing scalar floating-point operation instructions and instructions that support image processing.

5) Fetch/store unit (LSU), responsible for the execution of all memory access instructions.

6) The memory management unit (MMU), responsible for cooperating with the LSU unit to complete address conversion and memory management during storage access.

7) Vector operation unit (VPU), responsible for executing short vector instructions to realize 4-way double-precision data operations.

8) The communication unit (Gasket), which is responsible for the communication between the processor core and the second-level cache or other processor cores.

In order to realize the multi-thread interleaved double-precision short vector processor, the VPU unit is implemented on the basis of the original processor core. In order to cooperate with the functions of the VPU unit, TLU, IFU, LSU, and MMU have all been extended to support double-precision short vector operations. Corresponding to the improvement of the processor core structure, the processor of the multi-threaded cross double-precision short vector structure realizes a short vector operation instruction set, including vector access instructions, vector calculation instructions, vector comparison instructions, vector shift instructions, state operations instructions etc.

The above-mentioned processor core with a vector processing unit (VPU) supports up to 8 hardware threads, and multi-threaded concurrent use of VPU components constitutes a multi-threaded interleaved double-precision short vector architecture. The instruction stream of each thread using the vector unit contains several types of instructions. On this processor, the process of instruction execution is as follows:

IFU obtains two instructions from two threads from the current instructions of eight hardware threads every clock cycle, and it decides which functional unit to send the instruction to for execution according to the type of the instruction. If both are integer operation instructions, it can be At the same time, they are sent to two integer execution units respectively; if both are memory access instructions, vector floating-point operation instructions, and scalar floating-point operation instructions, one of them is issued first, and the other is sent in the next clock cycle. When multiple threads using the VPU unit are executed in the processor at the same time, vector access instructions and vector calculation instructions from different threads are executed on the LSU and VPU at the same time.

This multi-thread interleaved double-precision short vector structure can hide the delay of long-latency instructions and improve the overall performance of the processor.

Compared with the traditional SIMD extension for streaming media computing, the double-precision short vector unit uses different registers, different data paths, and completely different instruction sets; therefore, it is necessary to Write lots of review incentives. The benchmark stimulus used in processor verification and performance evaluation is an assembly language program for the processor architecture. In the processor verification process, the test stimulus is loaded into the test platform of the processor to run, and the correctness of the processor design can be verified; and the processor can be evaluated according to the execution time of the test stimulus and the calculation amount contained in the stimulus program performance. In the process of processor verification and performance evaluation, it is necessary to write a large number of assembly language programs as evaluation incentives. Usually, these programs are manually written by R&D and test personnel, which requires a lot of work and takes a long time. Because different processor instruction set architectures and short vector extension methods are different, it is impossible to inherit and reuse the existing evaluation incentives for multi-threaded short vector processing functional units.

Contents of the invention

The technical problem to be solved by the present invention is: aiming at the problems existing in the prior art, the present invention provides an automatic construction of evaluation incentives for a multi-threaded interleaved double-precision short vector structure that is easy to use, can reduce the workload of personnel, and can shorten the time-consuming method.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

A method for automatically constructing evaluation incentives for a multi-thread cross double-precision short vector structure, characterized in that it comprises the following steps:

(1) Enter the vector operation type and vector length to be evaluated;

(2) Automatically create an assembly language file with empty content used as an evaluation incentive;

(3) Write the following content to the assembly language file:

(3.1) Multi-threaded running initialization code segment;

(3.2) The evaluation incentive control structure, including: the code segment to start the multi-thread execution mode, which is used to set the multi-thread enable register to make the processor enter the multi-thread working state; the code segment for thread selection and jump, which is used to read each Thread private thread number register and jump to each thread according to the thread number;

(3.3) Multi-threaded vector operation program segment, including: the main thread vector operation code segment, which is used for the allocation of computing tasks for each thread, the calculation of the first address of the operand and the vector length, reading the source operand vector and the destination operand vector and looping Perform short vector operations; operate code segments from thread vectors to read source operand vectors and destination operand vectors and perform short vector operations;

(3.4) Evaluation incentive synchronization structure, including: the main thread synchronization code segment, which is used to judge and wait for all threads to complete the vector operation; the slave thread synchronization code segment, which is used to indicate to the main thread whether the thread has completed the vector operation;

(3.5) A data segment and a data segment initialization statement, the data segment is a multi-thread shared data segment, and the multi-thread shared data segment contains a source operand vector and a destination operand vector shared by multiple threads;

(4) The assembly language file obtained in step (3) is used as the evaluation stimulus for the automatically generated multi-thread interleaved double-precision short vector structure.

As a further improvement of the present invention:

In the step (3.3), the creation steps of the multi-threaded vector operation program segment are as follows:

(3.3.1) According to the input vector operation type and vector length, after assigning the calculation tasks of each thread (including the main thread and all slave threads), determine the starting position and length of the vector operated by each thread;

(3.3.2) Each thread calculates the source operand address and loop count register according to the thread number and vector length, and sets the base address register and loop count register;

(3.3.3) Each thread calculates the destination operand address according to the thread number, and sets the destination operand base address register;

(3.3.4) According to their respective calculation tasks, each thread inserts assembly instructions for vector reading, operation, or result writing back into the assembly language program text segment to form the main thread vector operation code segment and the slave thread vector operation code segment.

In the step (3.5), the shared data segment is constructed by the following steps:

(3.5.1) Use the random number generator of double-precision floating-point data to generate a double-precision vector used as a source operand, and the length of the vector is specified by the user; convert the double-precision data in the vector to hexadecimal as the source operand vector;

(3.5.2) Reserve the destination operand storage space according to the input vector length as the destination operand vector.

The data segment also includes a lock variable and a thread count variable used by the evaluation incentive synchronization structure. The evaluation incentive synchronization structure controls only one thread to update the thread count variable at the same time through the lock variable, and uses the thread count variable to distinguish and It is guaranteed that multiple threads must all complete their respective operations before the main thread continues to perform subsequent operations.

After the step (3.4) is completed, write the main thread calculation result comparison code segment for verifying the correctness of the main thread vector operation result, and the slave thread vector operation result comparison code segment for verifying the correctness of the slave thread vector operation result into the assembly language file. The code segment for thread calculation result comparison and the code segment for error reporting when the calculation result comparison is wrong; in the step (3.5), the data segment also includes the code segment for the main thread calculation result comparison and the slave thread calculation result comparison The correct vector of computed results read by the code segment.

Compared with the prior art, the present invention has the advantages of:

1. The evaluation and incentive automatic construction method of the multi-thread interleaving double-precision short vector structure of the present invention adopts the idea of component-based programming, uses the basic assembly language code segment as the basic component of the assembly language program, and automatically constructs multi-thread interleaving The evaluation incentive of the double-precision short vector structure is conducive to the rapid development of evaluation incentives for this type of architecture, which can reduce the workload of personnel.

2. The present invention can be realized by programming, input the vector operation type and vector length to be evaluated or verified, and the output evaluation incentive is an assembly language program that uses short vector instructions to complete computing tasks with multiple threads. Run the program multiple times and input different operation types and vector lengths to automatically construct evaluation incentives in batches, which can shorten the construction time, save costs, improve the efficiency of evaluation incentive development, and greatly facilitate processor verification and performance evaluation.

Description of drawings

FIG. 1 is a schematic diagram of a processor core structure of a multi-thread interleaved double-precision short vector structure.

Fig. 2 is a schematic diagram of the overall flow of a specific embodiment of the present invention.

Fig. 3 is a schematic flow chart of evaluation incentives constructed in a specific embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 2, the evaluation incentive automatic construction method of the multi-thread interleaved double-precision short vector structure of the present invention is used to evaluate and verify the multi-thread interleaved double-precision short vector structure system as shown in Figure 1, and the steps are as follows:

1. Enter the vector operation type and vector length to be evaluated.

2. Automatically create an assembly language source program file foo.s whose content is empty.

3. Write the following assembly language program text in the foo.s file:

3.1 The assembly language code segment used for multi-thread operation initialization; the present invention adopts the conventional initialization code segment, and the required initialization process of all constructed assembly language programs is the same.

3.2 Evaluation incentive control structure, including:

3.2.1 The code segment to start the multi-thread execution mode, which is used to set the multi-thread enable register to make the processor enter the multi-thread working state;

3.2.2 The code segment for thread selection and jump is used to read the private thread number register of each thread and jump to each thread according to the thread number; the thread with thread number 0 is the main thread, and other threads are slave threads.

3.3 Multi-thread vector operation program segment, which includes:

3.3.1 The main thread vector operation code segment is used for the allocation of calculation tasks of each thread, the calculation of the first address of the operand and the vector length, reading the source operand vector and the destination operand vector, and performing short vector operation in a loop. Its construction process is as follows:

a. The main thread calculates the first address and vector length of the operand according to its own thread number and calculation task allocation;

b. The main thread calculates the source operand address and the loop count register according to the thread number and the length of the vector, and sets the base address register and the loop count register;

c. The main thread calculates the destination operand address according to the thread number, and sets the destination operand base address register;

d. According to their respective calculation tasks, the main thread inserts assembly instructions for vector reading, operation, or result writing back into the assembly language program text segment to form the main thread vector operation code segment and the slave thread vector operation code.

3.3.2 From the thread vector operation code segment, it is used to read the source operand vector and the destination operand vector and perform short vector operation; its construction process is as follows: 

a. The slave thread calculates the first address and vector length of the operand according to its own thread number and calculation task assignment;

b. The slave thread calculates the source operand address and the loop count register according to the thread number and the length of the vector, and sets the base address register and the loop count register;

c. The slave thread calculates the destination operand address according to the thread number, and sets the destination operand base address register;

d. According to their respective calculation tasks, the slave thread inserts assembly instructions for vector reading, operation, or result writing back into the assembly language program text segment to form the main thread vector operation code segment and the slave thread vector operation code.

3.4 Evaluation incentive verification structure. It includes:

3.4.1 The main thread calculation result comparison code segment is used to verify the correctness of the main thread vector operation results;

3.4.2 Slave thread calculation result comparison code segment, used to verify the correctness of the slave thread vector operation results;

3.4.3 The code segment used to report an error when the calculation result is wrong.

For the test stimulus used as verification, it is necessary to insert a result comparison code segment for verifying the correctness of the operation result of the vector operation after the main thread and the slave thread execute the code segment of the vector operation operation. During actual operation, the result comparison code segment reads the numerical results just calculated by each thread and compares them with the corresponding pre-calculated correct calculation results, and executes the error code if the values are different.

3.5 Evaluation incentive synchronization structure, which includes:

3.5.1 The main thread synchronization code segment is used to judge and wait for all threads to complete the vector operation; if all threads have completed the operation, the main thread will report and exit; otherwise, the main thread will repeat the above process in a loop and wait for all threads to complete the vector operation.

3.5.2 The slave thread synchronization code segment is used to identify to the main thread whether the thread has completed the vector operation. After the slave thread completes the double-precision short vector operation, increase the thread count variable by 1 and enter the busy waiting state.

3.6 Data segment and data segment initialization statement. The data segment includes: a source operand vector and a destination operand vector, a lock variable, a thread count variable and correct calculation results for verification; wherein, the source operand vector and the destination operand vector are multi-thread shared data segments. The construction steps of the data segment and the data segment initialization statement are as follows:

3.6.1 Build a shared data segment:

a. Source operand vector. The random number generation program using double-precision floating-point data generates a double-precision vector used as a source operand, and the length of the vector is specified by the user; converts the double-precision data in the vector to hexadecimal, as the source operand vector, and specifies the data The alignment of the segment is align 32.

b. Destination operand vector. Reserve the storage space for the destination operand according to the length of the input vector. As the destination operand vector, the alignment of the data segment is align 32.

c. The correct calculation result vector. For the test stimulus used for verification, it is necessary to create a correct result data segment, which stores the pre-calculated correct result; this data segment is read by the result comparison code segment of the verification stimulus (created by step 3.4) Pick.

d. Create a lock variable. The lock variable is used to control that only one thread updates the thread count variable at a time. In this embodiment, a 64-bit integer lock variable is created in the shared data area, and the initial value is set to 0, and the alignment mode is align 8. When the value of the lock variable is 0, it means unlocked, and when the value of the lock variable is 1, it means locked. When the program is running, each thread loops to read the lock variable and judge the lock status with the compare and exchange instruction. If the value of the lock variable is 0, it means that no thread uses the shared data; the thread that acquires the lock variable first changes the lock variable to 1 , and then perform vector operations on the read-write shared data. After the vector operation is completed, use the compare and exchange instruction to restore the lock variable to 0.

e. Create a thread count variable. The thread count variable is used to judge and ensure that multiple threads must complete their respective operations before the main thread continues to perform subsequent operations. In this embodiment, a 64-bit integer thread count variable is created in the shared data area, and the initial value is set to 0, and the alignment mode is align 8. When the program is running, after the thread that acquires the lock variable completes the vector operation, it adds 1 to the thread count variable; when the main thread judges that the thread counter is equal to the total number of threads, it judges that all threads have completed the vector operation, then reports and exits.

4. Use the assembly language file obtained in step 3 as an evaluation stimulus for the automatically generated multi-thread interleaved double-precision short vector structure.

In the above steps, there is no limit to the order in which the vector operation program segment, verification structure, and synchronization structure of the evaluation incentive are written into the foo. After writing the structures, write them into the corresponding structures of the slave threads one by one. As shown in Figure 3, the execution flow of the evaluation incentives automatically generated in this embodiment is as follows:

(1) Multi-thread execution environment initialization.

(2) Read the corresponding thread number register of the hardware thread, and jump to the code entry of the main thread or the slave thread according to different thread numbers; if the thread number is 0, skip to step (3) and go to the main thread entry; Otherwise, skip to step (5) and switch to the corresponding slave thread entry.

(3) The main thread completes the double-precision short vector operation according to the thread number and the calculation task allocation; then executes the code to acquire the lock variable, if the lock variable is acquired, the thread counter is incremented by 1, and then the lock variable is released.

(4) Read the thread counter and judge whether the thread counter is equal to the total number of threads. If they are equal, it means that all threads have completed the vector operation, then the program terminates, returns to the system state and exits; if the two are not equal, execute this program in a loop steps until the two are equal.

(5) The corresponding slave thread completes the double-precision short vector operation according to the thread number and calculation task allocation; then executes the code to acquire the lock variable, if the lock variable is acquired, the thread counter is incremented by 1, and then the lock variable is released to enter the busy Waiting for status.

The above descriptions are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (5)

1. a kind of evaluation encourages the automatic construction method of multi-thread crossing double-precision short vector structure, it is characterized in that comprising the following steps: (1) Enter the vector operation type and vector length to be evaluated; (2) Automatically create an assembly language file with empty content used as an evaluation incentive; (3) Write the following content to the assembly language file: (3.1) Multi-threaded running initialization code segment; (3.2) The evaluation incentive control structure, including: the code segment to start the multi-thread execution mode, which is used to set the multi-thread enable register to make the processor enter the multi-thread working state; the code segment for thread selection and jump, which is used to read each Thread private thread number register and jump to each thread according to the thread number; (3.3) Multi-threaded vector operation program segment, including: the main thread vector operation code segment, which is used for the allocation of computing tasks for each thread, the calculation of the first address of the operand and the vector length, reading the source operand vector and the destination operand vector and looping Perform short vector operations; operate code segments from thread vectors to read source operand vectors and destination operand vectors and perform short vector operations; (3.4) Evaluation incentive synchronization structure, including: the main thread synchronization code segment, which is used to judge and wait for all threads to complete the vector operation; the slave thread synchronization code segment, which is used to indicate that the thread has completed the vector operation; (3.5) A data segment and a data segment initialization statement, the data segment is a multi-thread shared data segment, and the multi-thread shared data segment contains a source operand vector and a destination operand vector shared by multiple threads; (4) The assembly language file obtained in step (3) is used as the evaluation stimulus for the automatically generated multi-thread interleaved double-precision short vector structure. 2. The evaluation-inspired automatic construction method of multi-threaded interleaved double-precision short vector structure according to claim 1, characterized in that, in the step (3.3), the creation steps of the multi-threaded vector operation program segment are as follows: (3.3.1) According to the input vector operation type and vector length, after assigning the calculation tasks of each thread, determine the starting position and length of the vector operated by each thread; (3.3.2) Each thread calculates the source operand address and loop count register according to the thread number and vector length, and sets the base address register and loop count register; (3.3.3) Each thread calculates the destination operand address according to the thread number, and sets the destination operand base address register; (3.3.4) According to their respective calculation tasks, each thread inserts assembly instructions for vector reading, operation, or result writing back into the assembly language program text segment to form the main thread vector operation code segment and the slave thread vector operation code segment. 3. The evaluation-inspired automatic construction method of multi-threaded interleaved double-precision short vector structure according to claim 2, characterized in that, in the step (3.5), the shared data segment is constructed by the following steps: (3.5.1) Use the random number generator of double-precision floating-point data to generate a double-precision vector used as a source operand, and the length of the vector is specified by the user; convert the double-precision data in the vector to hexadecimal as the source operand vector; (3.5.2) Reserve the destination operand storage space according to the input vector length as the destination operand vector. 4. the evaluation incentive automatic construction method of multi-thread interleaving double-precision short vector structure according to claim 3, is characterized in that, described data section also comprises lock variable and the thread count variable that are used for described evaluation excitation synchronous structure, The evaluation incentive synchronization structure controls only one thread at a time to update the thread count variable through the lock variable, and judges and ensures that multiple threads must complete their respective operations before the main thread continues to perform subsequent operations through the thread count variable. 5. The evaluation-inspired automatic construction method of the multi-threaded interleaved double-precision short vector structure according to claim 1 or 2 or 3 or 4, characterized in that, after the step (3.4) is completed, the assembly language file Write the main thread calculation result comparison code segment for verifying the correctness of the main thread vector operation result, the slave thread calculation result comparison code segment for verifying the correctness of the slave thread vector operation result, and the error report for the calculation result comparison Code segment; in the step (3.5), the data segment also includes the correct calculation result vector read from the main thread calculation result comparison code segment and the slave thread calculation result comparison code segment.

Images