CN102508717B - Memory scheduling method and memory scheduling device for multi-core processor - Google Patents

Memory scheduling method and memory scheduling device for multi-core processor Download PDF

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CN102508717B
CN102508717B CN 201110366852 CN201110366852A CN102508717B CN 102508717 B CN102508717 B CN 102508717B CN 201110366852 CN201110366852 CN 201110366852 CN 201110366852 A CN201110366852 A CN 201110366852A CN 102508717 B CN102508717 B CN 102508717B
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memory block
memory
processor core
elasticity
surplus
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CN102508717A (en
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笪禹
陈剑
董继炳
刘博强
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Datang Mobile Communications Equipment Co Ltd
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Datang Mobile Communications Equipment Co Ltd
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Abstract

The invention discloses a memory scheduling method and a memory scheduling device for a multi-core processor. The memory scheduling method comprises the following steps of: distributing initialized memory blocks for each processor core according to memory configuration information, wherein the memory configuration information comprises information of a plurality of initialized memory blocks and a plurality of elastic memory blocks which is obtained by dividing a physical memory; for each processor core, monitoring residual quantity of the memory of the processor core; when the residual quantity of the memory is determined to be lower than a first set threshold, distributing the undistributed elastic memory blocks to the processor cores; and monitoring service conditions of the distributed elastic memory blocks and releasing the distributed elastic memory blocks when a first setting condition is met. According to the memory scheduling method and the memory scheduling device disclosed by the invention, the distribution dynamic of the memory is better; the requirement for newly-added memory caused by application change can be met; and the integral utilization rate of the memory is effectively improved.

Description

A kind of scheduling memory method and device that is applied to polycaryon processor
Technical field
The present invention relates to the multinuclear treatment technology, relate in particular to a kind of scheduling memory method and device that is applied to polycaryon processor.
Background technology
A kind of important model of polycaryon processor is exactly asymmetric heterogeneous system; each processor core operation one cover operating system; all physical resources of each operating system management self; internal memory is extremely important as the distribution of one of most important physical resource in heterogeneous system; present Memory Allocation mainly adopts the static allocation mode; as shown in Figure 1; by physical memory is divided according to the number of processor core; the operating system of distributing to then on the different processor nuclear manages; usually the number of dividing the memory block that obtains equates that with the number of processor core each processor core distributes a memory block.
Owing to adopt static allocation mode storage allocation, needing the designer that the required memory quantity that runs application on each processor core is had estimates more accurately, thereby the internal memory waste of avoiding storage allocation too much to cause, and the very few application function extendability that causes of storage allocation reduces.
But, adopt static allocation mode storage allocation, have following shortcoming:
1) can not accomplish strict distribution according to need, more be to rely on designer's experience to be carried out, and the validity of distribution exists not enough;
2) the static allocation mode is often planned at current demand, in case after application and business model changed, original planning just can not satisfy the demands, needs planning again to adjust, and is bigger to the stiffness of system influence.
Summary of the invention
The invention provides a kind of scheduling memory method and device that is applied to polycaryon processor, in order to effectively to utilize physical memory and to satisfy the processing demands of different IPs.
The invention provides a kind of scheduling memory method that is applied to polycaryon processor, comprising:
Distribute the initialization memory block according to memory configurations information for each processor core, described memory configurations information comprises divides a plurality of initialization memory block information and a plurality of elasticity memory block information that obtains with physical memory;
At each processor core, monitor the internal memory surplus of described processor core, when determining that described internal memory surplus is lower than first setting threshold, unappropriated elasticity memory block is distributed to described processor core;
Operating position to the elasticity memory block that distributes is monitored, and satisfying first when imposing a condition, discharges the elasticity memory block that distributes.
The present invention also provides a kind of scheduling memory device that is applied to polycaryon processor, comprising:
The original allocation unit is used for distributing the initialization memory block according to memory configurations information for each processor core, and described memory configurations information comprises divides a plurality of initialization memory block information and a plurality of elasticity memory block information that obtains with physical memory;
The elasticity allocation units are used at each processor core, monitor the internal memory surplus of described processor core, when determining that described internal memory surplus is lower than first setting threshold, unappropriated elasticity memory block are distributed to described processor core;
First releasing unit is used for the operating position of the elasticity memory block that distributes is monitored, and satisfying first when imposing a condition, discharges the elasticity memory block that distributes.
Utilize the scheduling memory method and apparatus that is applied to polycaryon processor provided by the invention, have following beneficial effect: the dynamic of Memory Allocation is better, can satisfy the newly-increased memory requirements that application change is brought; Effectively improve the internal memory overall utilization rate.
Description of drawings
Fig. 1 is the existing synoptic diagram that adopts static programming mode storage allocation;
The scheduling memory method flow diagram that is applied to polycaryon processor that Fig. 2 provides for the embodiment of the invention;
Fig. 3 divides the internal memory synoptic diagram for the scheduling memory method that is applied to polycaryon processor that the embodiment of the invention provides;
Fig. 4 is initialization memory block allocation flow figure in the embodiment of the invention;
Fig. 5 is at processor core operational process scheduling memory process flow diagram in the embodiment of the invention;
Fig. 6 is from other processor core allotment internal memory process flow diagrams in the embodiment of the invention;
Fig. 7 returns to the processor core process flow diagram for allocating internal memory in the embodiment of the invention;
The scheduling memory structure drawing of device that is applied to polycaryon processor that Fig. 8 provides for the embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples the scheduling memory method and apparatus that is applied to polycaryon processor provided by the invention is illustrated in greater detail.
Polycaryon processor is popularized gradually in the application of various fields such as communication, network, computing machine, the memory source of multiple nucleus system is planned and is shared out the work and becomes more and more important, the arrangement utilization factor that how to make each processor core obtain to satisfy the memory source of application demand and improve physical memory is an important problem, and the present invention adopts the mechanism of a kind of intellectual monitoring, elasticity allotment effectively to utilize physical memory and satisfies the processing demands of different IPs.
The scheduling memory method that is applied to polycaryon processor that the embodiment of the invention provides as shown in Figure 2, may further comprise the steps:
Step 201 is distributed the initialization memory block according to memory configurations information for each processor core, and described memory configurations information comprises divides a plurality of initialization memory block information and a plurality of elasticity memory block information that obtains with physical memory;
Step 202 at each processor core, is monitored the internal memory surplus of described processor core, when determining that described internal memory surplus is lower than first setting threshold, unappropriated elasticity memory block is distributed to described processor core, and particularly, this first setting threshold can be set as required;
Step 203 is monitored the operating position of the elasticity memory block that distributes, is satisfying first when imposing a condition, discharge the elasticity memory block that distributes, particularly, first imposes a condition can set as required, surpasses conditions such as a period of time is not used as the elasticity memory block.
Adopt the scheduling memory method that is applied to polycaryon processor of the embodiment of the invention, by planning elasticity memory block, after distributing initial memory block for each processor core, guarantee the basic operation of processor core execution, in the operational process of processor core, can be according to the needs of practical business pattern to internal memory, dynamically carry out scheduling memory, therefore the dynamic of Memory Allocation is better, can satisfy the newly-increased memory requirements that application change is brought, and effectively improves the internal memory overall utilization rate.
As shown in Figure 3, the memory block that obtains after with whole physical memory piecemeal of present embodiment is divided into two classes:
1) initialization memory block, this part memory block is similar to the memory block in the static memory allocation scheme, can arrange by guestimate, also can distribute identical memory size by each processor core;
2) elasticity memory block can adopt equal large scale memory block to be used as the elasticity memory block under the not high situation of scheduling accuracy requirement, and under height scheduling accuracy requirement, the elasticity memory block is made up of the memory block of different size, can satisfy different dispatching requirement.
Preferably, when carrying out the internal memory division, the number of initialization memory block is not less than the number of processor core, and the number of elasticity memory block is not less than the number of processor core, as shown in Figure 3, the number of the number of initialization memory block, elasticity memory block all equates with the number of processor core.
Preferably, at each processor core, determine that its internal memory surplus is lower than first setting threshold, and the elasticity memory block further comprises when all being assigned with:
From the initialization memory block that the processor core that is not less than first setting threshold for the internal memory surplus distributes, release portion initialization memory block is distributed to the processor core that described internal memory surplus is lower than first setting threshold;
Operating position to assigned portions initialization memory block is monitored, and when satisfied second imposes a condition, described partially-initialized memory block is returned to the processor core that discharges described partially-initialized memory block.
If the embodiment of the invention some processor core after the elasticity memory block all distributes still needs to add internal memory, then can from the initialization memory block more than needed of other processor core, cut apart allotment according to monitored results, elasticity memory block except monitor allocation, the operating position that also needs the initial memory block of part of monitor allocation, with the unwanted partially-initialized memory block of timely release, in order to avoid influence the operation of processor core.
The embodiment of the invention is supervised Memory Allocation on the processor core, when polycaryon processor starts, preferentially begin to distribute from the initialization memory block, guarantee the basic operation of each processor core, in order to satisfy actual needs, can from the elasticity memory block, distribute according to the actual requirements.Preferably, the embodiment of the invention is recorded as the initialization Memory Allocation that each processor core distributes by configuration file in advance.
The embodiment of the invention can the periodic monitor processor core the internal memory surplus, in time to satisfy the high processor core of memory demand; The embodiment of the invention can regularly determine whether to need to discharge the elasticity memory block that has been assigned with, in time to discharge when not required at the elasticity memory block, uses with the processor core that more needs internal memory to other; The embodiment of the invention can regularly determine whether to give back the partially-initialized of cutting apart memory block, to return to original processor core when not required at the partially-initialized memory block of cutting apart, thereby realize dynamically updating of internal memory, above-mentioned each timing can be to carry out timing simultaneously, also can be respectively regularly.
Provide the preferred embodiment that is applied to the scheduling memory method of polycaryon processor provided by the invention below, mainly comprise following flow process:
1) distributes the initialization memory block
As shown in Figure 4, comprising:
Step 401, processor core starts;
Step 402, after processor starts, read memory configurations information, for processor core distributes the initialization memory block, described memory configurations information comprises divides a plurality of initialization memory block information and a plurality of elasticity memory block information that obtains with physical memory, particularly, be that initial blocking memory block 0～N is distributed to processor core 0～N, specifically how to distribute, can be under the situation of dividing according to the business model of each processor core at each initialization memory block, according to the business model of each processor, distribute with the initialization memory block of business model coupling and give corresponding processor core.Certainly, also can distribute the principle of an initialization memory block to distribute arbitrarily by each processor core in the equal situation of each initialization memory block.
Step 403, the operating system of processor core begins memory management according to the initialization memory block that distributes, each processor core operation one cover operating system, all physical resources of each operating system management self comprise the initialization memory block of distribution.
2) operating position of each processor core of monitoring in the processor core operational process is carried out the internal memory dynamic dispatching according to monitoring result, at each processor core, regularly carries out the monitoring task, as shown in Figure 5, carries out following steps:
Step 500 when arriving certain hour, starts the monitoring task;
Step 501 reads the internal memory surplus that current processor is examined;
Step 502 judges whether the internal memory surplus is lower than thresholding 1; If the internal memory surplus is lower than thresholding 1, execution in step 503, otherwise execution in step 503 ';
Step 503 is inquired about unallocated elasticity memory block information;
Step 504 has determined whether unappropriated elasticity memory block, if unappropriated elasticity memory block is arranged, execution in step 505 is not if having unappropriated elasticity memory block, then execution in step 505 ';
Step 505 ', carry out the allotment of initialization memory block;
When carrying out the allotment of initialization memory block, the internal memory surplus that at first defines which processor core is not less than thresholding 1, these processor cores are examined as target, this processor core is as application nuclear, as shown in Figure 6, carry out following treatment scheme: step 601, authorize to target and to send the allotment memory request, discharge current do not use and occupancy is lower than the partially-initialized memory block of thresholding 3 with indicating target nuclear; After step 602, target stone grafting are received the allotment memory request, calculate the situation that takies of self initialization memory block; Step 603 judges whether occupancy is lower than certain thresholding, if carry out execution in step 604, otherwise determine to distribute failure, execution in step 605; Step 604, the partially-initialized memory block that occupancy is lower than thresholding 3 discharges; Step 605 sends allocation result; Step 606, receiving target are authorized the allocation result of sending, and the partially-initialized memory block that discharges is distributed to this processor core.
As seen, the embodiment of the invention still has urgent memory requirements if some handles nuclear under the situation of elasticity memory block deficiency, can allocate from the more nuclear of initial memory block free memory.Application nuclear need be according to other processing nuclear in the above-mentioned flow process Ergodic Theory, up to finding the target nuclear that can satisfy the allotment condition in select target nuclear.
After the allotment of initialization for causing memory block, the operating position that the processor core of the partially-initialized memory block of acceptance allotment need be followed the tracks of this internal memory falls after rise if internal memory uses, and need give back this partially-initialized memory block, as shown in Figure 7, comprising:
Step 700, when the current not use of the partially-initialized memory block that definite allotment is come and occupancy are lower than first thresholding, execution in step 701; Step 701 discharges this partially-initialized memory block, and authorizes to original target and to send the release memory request; After step 702, target stone grafting are received and discharged memory request, add this partially-initialized memory block that discharges to native processor nuclear; Step 703, transmit operation result are given original application nuclear; Step 704, application nuclear is determined to discharge successfully.
Step 505, application elasticity memory block;
Step 506 is added unappropriated elasticity memory block in this processor core to, and this monitoring task finishes, and returns execution in step 500;
Step 503 ', if the internal memory surplus is not less than thresholding 1, judge then whether this processor core exists the elasticity memory block that does not re-use of distribution, and this elasticity memory block release back internal memory surplus is higher than thresholding 2, if there is execution in step 504 ';
Step 504 ', discharge this type of elasticity memory block, certainly, also can determine whether the elasticity memory block according to the factor whether memory block is not used above certain hour.
The embodiment of the invention arranges two thresholdings in the monitoring flow process, thresholding 1 expression starts the current internal memory surplus of distributing the elasticity memory block, and thresholding 2 expressions can discharge the current internal memory surplus of elasticity memory block, and thresholding 2 will be higher than thresholding 1.The setting of threshold value generally need be with reference to the application demand of this processor core, historical high low value and entire system internal memory situation, go out a rational thresholding by simulation calculation, do not need the internal memory that uses to avoid applying for frequently discharging or to take for a long time.
The above-mentioned flow process of the embodiment of the invention can adopt the device that is independent of outside the processor core to realize, namely realized handling the distribution of nuclear initialization memory block by this device, and the elasticity memory block managed between the device nuclear throughout dispatch, when carrying out scheduling memory between multinuclear, realizes in this device the schedule information exclusive reference, namely this device is managed concentratedly the Memory Allocation situation of all processor cores, at synchronization, only the internal memory use of a processor is made amendment, can not revise the internal memory operating position of a plurality of processor cores simultaneously.
Management to the elasticity memory block that distributed on each processor core in the embodiment of the invention distributes, and also can be application, the realizing interface of elasticity memory block are registered operating system to processor core, is called by the operating system interface unification.
Based on same inventive concept, a kind of scheduling memory device that is applied to polycaryon processor also is provided in the embodiment of the invention, because principle and a kind of scheduling memory method that is applied to polycaryon processor of this device solves problem, therefore the enforcement of these equipment can repeat part and repeat no more referring to the enforcement of method.
A kind of scheduling memory device that is applied to polycaryon processor as shown in Figure 8, comprising:
Original allocation unit 800 is used for distributing the initialization memory block according to memory configurations information for each processor core, and described memory configurations information comprises divides a plurality of initialization memory blocks and a plurality of elasticity memory block that obtains with physical memory;
Elasticity allocation units 801 are used at each processor core, monitor the internal memory surplus of described processor core, when determining that described internal memory surplus is lower than first setting threshold, unappropriated elasticity memory block are distributed to described processor core;
First releasing unit 802 is used for the operating position of the elasticity memory block that distributes is monitored, and satisfying first when imposing a condition, discharges the elasticity memory block that distributes.
The scheduling memory device that is applied to polycaryon processor that the embodiment of the invention provides adopts the mode of reserving the elasticity memory block to satisfy monitoring, distribution, the releasing mechanism of the allotment of polycaryon processor elasticity internal memory; The internal memory original allocation is effectively simple more, reduces the initial assessment difficulty; The dynamic of Memory Allocation is better, can satisfy the newly-increased memory requirements that application change is brought; Effectively improve the internal memory overall utilization rate.
Those skilled in the art should understand that embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt complete hardware embodiment, complete software embodiment or in conjunction with the form of the embodiment of software and hardware aspect.And the present invention can adopt the form of the computer program of implementing in one or more computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) that wherein include computer usable program code.
The present invention is that reference is described according to process flow diagram and/or the block scheme of method, equipment (system) and the computer program of the embodiment of the invention.Should understand can be by the flow process in each flow process in computer program instructions realization flow figure and/or the block scheme and/or square frame and process flow diagram and/or the block scheme and/or the combination of square frame.Can provide these computer program instructions to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, make the instruction of carrying out by the processor of computing machine or other programmable data processing device produce to be used for the device of the function that is implemented in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame appointments.
These computer program instructions also can be stored in energy vectoring computer or the computer-readable memory of other programmable data processing device with ad hoc fashion work, make the instruction that is stored in this computer-readable memory produce the manufacture that comprises command device, this command device is implemented in the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame.
These computer program instructions also can be loaded on computing machine or other programmable data processing device, make and carry out the sequence of operations step producing computer implemented processing at computing machine or other programmable devices, thereby be provided for being implemented in the step of the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame in the instruction that computing machine or other programmable devices are carried out.
Although described the preferred embodiments of the present invention, in a single day those skilled in the art get the basic creative concept of cicada, then can make other change and modification to these embodiment.So claims are intended to all changes and the modification that are interpreted as comprising preferred embodiment and fall into the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.

Claims (13)

1. a scheduling memory method that is applied to polycaryon processor is characterized in that, comprising:
Distribute the initialization memory block according to memory configurations information for each processor core, described memory configurations information comprises divides a plurality of initialization memory block information and a plurality of elasticity memory block information that obtains with physical memory;
At each processor core, monitor the internal memory surplus of described processor core, when determining that described internal memory surplus is lower than first setting threshold, unappropriated elasticity memory block is distributed to described processor core;
Operating position to the elasticity memory block that distributes is monitored, and satisfying first when imposing a condition, discharges the elasticity memory block that distributes.
2. the method for claim 1 is characterized in that, determines that described internal memory surplus is lower than first setting threshold, and the elasticity memory block further comprises when all being assigned with:
From the initialization memory block that the processor core that is not less than first setting threshold for the internal memory surplus distributes, release portion initialization memory block is distributed to the processor core that described internal memory surplus is lower than first setting threshold;
Operating position to assigned portions initialization memory block is monitored, and when satisfied second imposes a condition, described partially-initialized memory block is returned to the processor core that discharges described partially-initialized memory block.
3. method as claimed in claim 2, it is characterized in that, from the initialization memory block that the processor core that is not less than first setting threshold for the internal memory surplus distributes, release portion initialization memory block is distributed to the processor core that described internal memory surplus is lower than first setting threshold, specifically comprises:
The processor core that is not less than first setting threshold to the internal memory surplus sends the allotment memory request, is lower than the partially-initialized memory block of the 3rd setting threshold with the current not use of instruction processorunit nuclear release and occupancy;
Receive the allocation result of the processor core transmission of release portion initialization memory block, the partially-initialized memory block that discharges is distributed to the processor core that described internal memory surplus is lower than first setting threshold.
4. method as claimed in claim 2 is characterized in that, when satisfied second imposes a condition, described partially-initialized memory block is returned to the processor core that discharges described partially-initialized memory block, comprising:
Determine that the current use of described partially-initialized memory block and occupancy are lower than the 3rd setting threshold, return to described partially-initialized memory block the processor core that discharges described partially-initialized memory block.
5. method as claimed in claim 2 is characterized in that, whether the operating position of regularly definite assigned portions initialization memory block satisfies second imposes a condition.
6. the method for claim 1 is characterized in that, the internal memory surplus of periodic monitor processor core, and timing determines whether the operating position of the elasticity memory block of distribution satisfies first and impose a condition.
7. as the arbitrary described method of claim 1～6, it is characterized in that, when satisfied first imposes a condition, discharge the elasticity memory block that distributes, specifically comprise:
The elasticity memory block that distributes surpasses the setting duration and is not used, and discharges the elasticity memory block that distributes;
Or distribute to the elasticity memory block that discharges processor core and be not used, and after discharging the elasticity memory block that is not used, the free memory amount of described processor core is higher than when setting second threshold value, discharges the elasticity memory block that distributes.
8. method as claimed in claim 7 is characterized in that, described first setting threshold is less than setting second threshold value.
9. a scheduling memory device that is applied to polycaryon processor is characterized in that, comprising:
The original allocation unit is used for distributing the initialization memory block according to memory configurations information for each processor core, and described memory configurations information comprises divides a plurality of initialization memory block information and a plurality of elasticity memory block information that obtains with physical memory;
The elasticity allocation units are used at each processor core, monitor the internal memory surplus of described processor core, when determining that described internal memory surplus is lower than first setting threshold, unappropriated elasticity memory block are distributed to described processor core;
First releasing unit is used for the operating position of the elasticity memory block that distributes is monitored, and satisfying first when imposing a condition, discharges the elasticity memory block that distributes.
10. device as claimed in claim 9 is characterized in that, also comprises:
Cutting unit, be used for determining that described internal memory surplus is lower than first setting threshold, and when the elasticity memory block all has been assigned with, from the initialization memory block that the processor core that is not less than first setting threshold for the internal memory surplus distributes, release portion initialization memory block is distributed to the processor core that described internal memory surplus is lower than first setting threshold;
Second releasing unit is used for the operating position of assigned portions initialization memory block is monitored, and when satisfied second imposes a condition, described partially-initialized memory block is returned to the processor core that discharges described partially-initialized memory block.
11. device as claimed in claim 10, it is characterized in that, described cutting unit, from the initialization memory block that the processor core that is not less than first setting threshold for the internal memory surplus distributes, release portion initialization memory block is distributed to the processor core that described internal memory surplus is lower than first setting threshold, specifically comprise: the processor core that is not less than first setting threshold to the internal memory surplus sends the allotment memory request, is lower than the partially-initialized memory block of the 3rd setting threshold with the current not use of instruction processorunit nuclear release and occupancy; Receive the allocation result of the processor core transmission of release portion initialization memory block, the partially-initialized memory block that discharges is distributed to the processor core that described internal memory surplus is lower than first setting threshold.
12. device as claimed in claim 10, it is characterized in that, second releasing unit, concrete for determining that the current use of described partially-initialized memory block and occupancy are lower than the 3rd setting threshold, return to described partially-initialized memory block the processor core that discharges described partially-initialized memory block.
13. as the arbitrary described device of claim 9～12, it is characterized in that, first releasing unit, concrete being used for is not used above setting duration at the elasticity memory block that distributes, and discharges the elasticity memory block that distributes; Or distribute to the elasticity memory block that discharges processor core and be not used, and after discharging the elasticity memory block that is not used, the free memory amount of described processor core is higher than when setting second threshold value, discharges the elasticity memory block that distributes.
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