CN102495357B - Input vector monitoring concurrency built-in self-test circuit based on comparator and response analyzer - Google Patents
Input vector monitoring concurrency built-in self-test circuit based on comparator and response analyzer Download PDFInfo
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Abstract
An input vector monitoring concurrency built-in self-test circuit based on a comparator and a response analyzer relates to a test device of a SOC. In the current test, hardware cost is high; test time delay is long so that several circuits which have many input pins can not be monitored. By using the circuit of the invention, the above problems can be solved. A detected integrated circuit has n original input signals. The t original input signals are selected from the original input signals to be address signals and the n-t original input signals are selected to be non-address signals. Combinations of the t address signals are different. The signal is selected through an alternative multiplexer and the signal is sent to a test generator and the detected integrated circuit. The comparator compares the selector signal with a column output signal and sends a comparison signal to the test generator. The test generator and the detected integrated circuit issue an output signal and an actual output signal to the response analyzer respectively. The response analyzer compares the two signals and sends a test result. The circuit can be used for detecting the circuit which can not be detected in the past.
Description
Technical field
The present invention relates to the proving installation of SOC.
Background technology
Past four, development of integrated circuits was followed Moore's Law always during the decade, and namely the scale of integrated circuit was twice expansion every 18 months, had entered the deep-submicron stage now.Along with scale and the integrated level of integrated circuit improves constantly, the manufacturing cost of chip also decreases, yet the raising of chip complexity makes that the testing cost of chip is more and more higher.Because the testing cost of chip is the part of chip total cost, it is increasing that this makes that the chip testing cost accounts for the proportion of total cost, and the testing cost that therefore how to reduce chip is the problem with regard to having become people to be concerned about very much also.
The semiconductor development of science and technology make VLSI (very large scale integrated circuit) particularly performance of processors be greatly improved.Yet along with the size of transistor and interconnection reduces, the lifting of the reduction of supply voltage and circuit running frequency, the possibility that circuit breaks down is also increasing.In the actual motion of circuit, mainly can run into following three kinds of faults.
(1) permanent fault---this fault mainly is that the physical imperfection by circuit causes that along with the progress of semiconductor design and process technology, this defective probability of happening is more and more lower, but still can exist in chip.
(2) transient fault---this fault is unrepeatable, mainly is that factors such as electromagnetic interference (EMI) cause by high energy particle (cosmic rays, alpha ray).Along with the raising of integrated circuit integrated level and the reduction of supply voltage, now circuit is easy to be subjected to the influence of the transient fault that high energy particle brings out, and this fault become the main reason of circuit malfunction, and common have single-particle inversion and a soft fault.
(3) intermittent defect---this fault mainly be caused by circuit running frequency, voltage and other environmental factors and under identical condition, can repeat to take place.
Transient fault has become the main fault of harm chip operation, yet the off-line built-in self-test can not the testing circuit transient fault, so people have proposed a lot of online built-in self-tests, it is exactly wherein a kind of that input vector is monitored concurrent built-in self-test.
People have proposed input vector and have monitored concurrent built-in self-test before, as C-BIST, RC-BIST, MCBIST, SWIM etc. method, but work as the input pin of circuit-under-test more for a long time, and these methods all exist hardware cost and test to delay time excessive and cause the immesurable situation of circuit-under-test.
Summary of the invention
To such an extent as to the objective of the invention is to monitor the problem that the hardware cost that exists in the concurrent built-in self-test is too high, the more circuit of test more excessive input pins of time-delay can't be monitored in order to solve existing input vector, and the input vector that has proposed a kind of response analysis of device based on the comparison device is monitored concurrent built-in self-test circuit.
The input vector of the response analysis of device based on the comparison device of the present invention is monitored concurrent built-in self-test circuit and is comprised test set generator, output response analyzer, comparer and alternative MUX; Tested integrated circuit has n position input end, the input signal of described input end is the original input signal of upper level circuit output, the original input signal of upper level circuit output is 0 or 1 signal, in the original input signal of n position upper level circuit output, select the t position as the address signal of upper level circuit output, remaining n-t position is as the non-address signal of upper level circuit output, wherein
The number of alternative MUX is n+t, wherein, the address signal that t alternative MUX of first alternative MUX to the is respectively applied to the output signal of gated counter or the output of upper level circuit sends to t input end of test set generator, the address signal that 2t alternative MUX of t+1 alternative MUX to the is respectively applied to the output signal of gated counter or the output of upper level circuit sends to t input pin of first input pin to the of tested integrated circuit, when described n＞t+1,2t+1 alternative MUX to the n+t alternative MUX is respectively applied to select the row output signal of the row output terminal of the non-address signal of upper level circuit output or test set generator to send to t+1 input pin to a n input pin of tested integrated circuit, 2t+1 alternative MUX to the n+t alternative MUX also is respectively applied to select the row output signal of the row output terminal of the non-address signal of upper level circuit output or test set generator to send to n-t signal input part of first signal input part to the of comparer, comparer, all signals that are used for its input end is received compare, and send compare result signal to the comparison signal input end of test set generator; The line output end of test set generator sends the line output signal to the generation signal input part of response analysis device, the output terminal of tested integrated circuit sends real output signal to the actual signal input end of response analysis device, the test signal that the generation signal arrangement that the response analysis device is used for receiving generates, also be used for described test signal and actual signal are compared, and to outwards sending test result by fault bit flag output terminal.
The present invention realizes by reducing test set generator (test generator) and output response analyzer 2 two-part hardware costs, the method of taking be in test set generator 1 part because or door be to have Sheffer stroke gate to constitute, n input or door be by the constituting with door of n two inputs, so reduce or the input port number of door can reduce the Sheffer stroke gate number of actual needs.Experimental result shows, monitors concurrent built-in self-test with the input vector of people's proposition before and compares, and concurrent test time-delay and the hardware cost that can reduce test circuit to a great extent of the present invention makes some original immesurable circuit to be detected.
Description of drawings
Fig. 1 monitors the structural representation of concurrent built-in self-test circuit for the input vector of device response analysis device based on the comparison, and Fig. 2 is the structural representation of test set generator 1, and Fig. 3 is the structural representation of output response analyzer 2.
Embodiment
Embodiment one: in conjunction with Fig. 1 present embodiment is described, the input vector of the response analysis of the device based on the comparison device of present embodiment is monitored concurrent built-in self-test circuit and is comprised test set generator 1, output response analyzer 2, comparer 3 and alternative MUX 4;
Tested integrated circuit 5 has n position input end, the input signal of described input end is the original input signal of upper level circuit output, the original input signal of upper level circuit output is 0 or 1 signal, in the original input signal of n position upper level circuit output, select the t position as the address signal of upper level circuit output, remaining n-t position is as the non-address signal of upper level circuit output, wherein
The number of alternative MUX 4 is n+t, wherein,
The address signal that first alternative MUX 4 to t alternative MUX 4 is respectively applied to the output signal of gated counter or the output of upper level circuit sends to t input end of test set generator 1,
The address signal that t+1 alternative MUX 4 to 2t alternative MUX 4 is respectively applied to the output signal of gated counter or the output of upper level circuit sends to t input pin of first input pin to the of tested integrated circuit 5,
When described n＞t+1, the alternative MUX 4 that 2t+1 alternative MUX is 4 to n+t are respectively applied to select the row output signal of the row output terminal of the non-address signal of upper level circuit output or test set generator 1 to send to t+1 input pin to a n input pin of tested integrated circuit 5, the alternative MUX 4 that 2t+1 alternative MUX is 4 to n+t also are respectively applied to select the row output signal of the row output terminal of the non-address signal of upper level circuit output or test set generator 1 to send to n-t signal input part of first signal input part to the of comparer 3, when n=t, then do not have above-mentioned signal and send;
Comparer 3, all signals that are used for its input end is received compare, and send compare result signal to the comparison signal input end of test set generator 1;
The line output end of test set generator 1 sends the line output signal to the generation signal input part of response analysis device 2,
The output terminal of tested integrated circuit 5 sends real output signal to the actual signal input end of response analysis device 2,
The test signal that the generation signal arrangement that response analysis device 2 is used for receiving generates also is used for described test signal and actual signal are compared, and to outwards sending test result by fault bit flag output terminal.
Embodiment two: in conjunction with Fig. 2 present embodiment is described, present embodiment and embodiment one difference be test set generator 1 comprise T test vector, a T line output and door and n-t row output or;
The t of test set generator 1 input end receives the t bit address signal of upper level circuit output, the t bit address signal combination of upper level circuit output becomes a plurality of input signals inequality, the corresponding test vector of each input signal, and the input signal of correspondence is sent to the input end of test vector generator
The number of described test vector is T, and the figure place of each test vector is n, and then the test set in the test set generator 1 constitutes the matrix of a T * n;
T row in n in the described matrix row are selected as address bit, test set are constituted each row in the matrix of a T * n as a set, if subclass v of all row
I1, v
I2, v
I3V
ItAll be inequality, wherein 1≤i≤T namely claims v
I1, v
I2, v
I3V
ItBe the row difference;
Each test vector has an output bus, and the number of output bus is T, and the output signal of each output bus output is respectively v
I (t+1), v
I (t+2), v
I (t+3)V
In,
The corresponding row output of one column signal of output bus output or door, the column signal of exporting when output bus is high level, then the input end receive logic of row output or door is worth 1, the output terminal output logic value 1 of described row output or door, the output terminal of row output or door is the row output terminal of test set generator 1, then the row output terminal is n-t
The corresponding line output of delegation's signal of output bus output and door, the capable signal of exporting when output bus is high level, then line output is worth 1 with an input end receive logic of door, described line output is the comparison signal input end of test set generator 1 with another input end of door, line output receives comparison signal with another input end of door, line output is the line output end of test set generator 1 with the output terminal of door, and then the line output end is T.
Other structure is identical with embodiment one with connected mode.
For example, 5 test vectors are arranged in Table 1,6 input positions that comprise in six each test vectors of letter representation of f with a.Select a, b and d to can be used as address bit, because the combination of their a, b and d all is different for these 5 test vectors, that is to say that a, b and d are capable different (row-distinct), can also choose a, b and c etc. equally.But c, e and f combination just cannot be as address bits, because combination (1,0,1) has occurred at test vector 1 and 5 middle parts, they are not row different (row-distinct).
Table one, test set signal table
| a | b | c | d | e | f | |
| vector1 | 0 | 0 | 1 | 1 | 0 | 1 |
| vector2 | 0 | 1 | 1 | 0 | 1 | 1 |
| |
1 | 0 | 1 | 1 | 1 | 0 |
| vector4 | 0 | 0 | 0 | 0 | 1 | 1 |
| |
1 | 1 | 1 | 0 | 0 | 1 |
The output signal signal table of the output bus output of table two, test set
| d | | f | |
| vector1 | |||
| 1 | 0 | 1 | |
| vector2 | 0 | 1 | 1 |
| |
1 | 1 | 0 |
| vector4 | 0 | 1 | 1 |
| vector5 | 0 | 0 | 1 |
Embodiment three: present embodiment is described in conjunction with Fig. 3, present embodiment and embodiment one or two differences are that output response analyzer 2 comprises m or door and m response analysis comparer, the input bus of output response analyzer 2 is the generation signal input part of response analysis device 2, the signal of input bus output corresponding one or, the signal of exporting when input bus is high level, then or door input end receive logic value 1, described or the door output terminal output logic value 1, or the output terminal connection response of door is analyzed the test signal input end of comparer, the actual signal input end of response analysis comparer is the actual signal input end of response analysis device 2, the actual signal input end of response analysis comparer connects the output terminal of tested integrated circuit 5, the output terminal of m response analysis comparer is connected with m input end of output or door, and the output terminal of output or door is the output terminal of response analysis device 2.Other structure is identical with embodiment one or two with connected mode.
Present embodiment comprises online and two test patterns of off-line.For the ease of the operational process of narration circuit, suppose that equally [1: 3] position of tested integrated circuit 5 input positions is address bit.
On-line testing, the input vector of the response analysis of device based on the comparison device of the present invention is monitored the on-line testing method of operation of concurrent built-in self-test circuit and is monitored the similar of the concurrent built-in self-test on-line testing method of operation with existing input vector, just the present invention's test need be in test set all test vectors all produce the value that the hit signal reexamines later in the output response analyzer 2 and whether equate with expectation value.Monitor in the concurrent built-in self-test circuit at the input vector of device response analysis device based on the comparison, output response analyzer 2 has been stored the output response of each test vector in the test set.It is all that whether check circuit output at this moment is corresponding identical with expectation value when any one test vector reaches circuit-under-test in the test set.In addition, monitor at existing input vector that logical block Li arrives the first time that can only record any one test vector in the test set in the concurrent built-in self-test, monitoring at the input vector of device response analysis device does not based on the comparison then need in the concurrent built-in self-test circuit to adopt this logical block, and whether the input vector of device response analysis device based on the comparison to monitor output response that concurrent built-in self-test circuit all will compare circuit-under-test identical with the expectation value of depositing in the output response analyzer 2 because test vector arrives repeatedly in the test set.
Off-line test, in some cases, when circuit during in normal operation in the test set some test vector never reach the input end of circuit-under-test, need transfer circuit to the off-line test pattern for testing circuit to the detection case of all faults this moment.The off-line test that also needs simultaneously circuit in tests such as manufacturing test adds the off-line test pattern while and also can eliminate add the needed hardware cost of off-line test in addition in circuit so monitor at the input vector of device response analysis device based on the comparison in the concurrent built-in self-test circuit.
The same with the on-line testing of the concurrent built-in self-test circuit of input vector monitoring of response analysis device based on accumulator, based on the comparison the difference of the off-line test of the off-line test of the concurrent built-in self-test circuit of the input vector of device response analysis device monitoring and the concurrent built-in self-test of existing input vector monitoring be equally need to be not all in test set test vector all produce the hit signal whether reexamine in output response analyzer 2 data the same with desired value later, but the output response that all can check this moment when as long as in test set, any one test vector produces hit whether with output response analyzer 2 in the desired value of having stored equate.
When the input port number of circuit-under-test is too much (greater than 40), the test time-delay of adopting existing input vector to monitor concurrent built-in self-test circuit will reach the unacceptable stage of people.So in order to reduce the concurrent test time-delay of test circuit, monitor concurrent built-in self-test with existing input vector and compare, to monitor the topmost improvement of concurrent built-in self-test circuit be to change the output response analyzer 2 based on totalizer into the output response analyzer 2 of device based on the comparison to the input vector of device response analysis device based on the comparison.Because the output response analyzer 2 of device need get up the output respective stored of all test vectors in the test set based on the comparison, so will change the raising that the output response analyzer 2 of device based on the comparison can cause the test circuit hardware cost based on the output response analyzer 2 of totalizer into.In order to solve the method that the excessive problem this paper of hardware cost has also proposed effectively to reduce hardware cost, it mainly is the hardware cost 1 that reduces circuit two sides) the test set generator, by reducing the hardware cost that two input nand gate numbers reduce the test set generator.2) output response analyzer 2, thereby reduce the hardware cost that needs monitored output port number to reduce output response analyzer 2 by output port optimization.
Content of the present invention is not limited only to the content of the respective embodiments described above, and the combination of one of them or several embodiments equally also can realize the purpose of inventing.
Claims (3)
- One kind based on the comparison the input vector of device response analysis device monitor concurrent built-in self-test circuit, it is characterized in that it comprises test set generator (1), response analysis device (2), comparer (3) and alternative MUX (4);Test set generator (1) comprise T test vector, a T line output and door and n-t row output or;Tested integrated circuit (5) has n position input end, the input signal of described input end is the original input signal of upper level circuit output, the original input signal of upper level circuit output is 0 or 1 signal, in the original input signal of n position upper level circuit output, select the t position as the address signal of upper level circuit output, remaining n-t position is as the non-address signal of upper level circuit output, whereinThe number of alternative MUX (4) is n+t, wherein,The address signal that first alternative MUX (4) to t alternative MUX (4) is respectively applied to the output signal of gated counter or the output of upper level circuit sends to t input end of test set generator (1),The address signal that t+1 alternative MUX (4) to 2t alternative MUX (4) is respectively applied to the output signal of gated counter or the output of upper level circuit sends to t input pin of first input pin to the of tested integrated circuit (5)when described n＞t+1, 2t+1 alternative MUX (4) to the alternative MUX (4) of n+t is respectively used to select the row output signal of the row output of the non-address signal of upper level circuit output or test set generator (1) to send to t+1 input pin to a n input pin of tested integrated circuit (5), 2t+1 alternative MUX (4) to the alternative MUX (4) of n+t also is respectively used to select the row output signal of the row output of the non-address signal of upper level circuit output or test set generator (1) to send to n-t signal input part of first signal input part to the of comparator (3),Comparer (3), all signals that are used for its input end is received compare, and send compare result signal to the comparison signal input end of test set generator (1);The line output end of test set generator (1) sends the line output signal to the generation signal input part of response analysis device (2),The output terminal of tested integrated circuit (5) sends real output signal to the actual signal input end of response analysis device (2),The test signal that the generation signal arrangement that response analysis device (2) is used for receiving generates also is used for described test signal and actual signal are compared, and to outwards sending test result by fault bit flag output terminal.
- 2. the input vector of a kind of response analysis of device based on the comparison device according to claim 1 is monitored concurrent built-in self-test circuit, it is characterized in thatT input end of test set generator (1) receives the t bit address signal of upper level circuit output, the t bit address signal combination of upper level circuit output becomes a plurality of input signals inequality, the corresponding test vector of each input signal, and the input signal of correspondence is sent to the input end of test vector generatorThe number of described test vector is T, and the figure place of each test vector is n, and then the test set in the test set generator (1) constitutes the matrix of a T * n;T row in n in the described matrix row are selected as address bit, test set are constituted each row in the matrix of a T * n as a set, if subclass v of all row I1, v I2, v I3V ItAll be inequality, wherein 1≤i≤T namely claims v I1, v I2, v I3V ItBe the row difference;Each test vector has an output bus, and the number of output bus is T, and the output signal of each output bus output is respectively v I (t+1), v I (t+2), v I (t+3)V In,The corresponding row output of one column signal of output bus output or door, the column signal of exporting when output bus is high level, then the input end receive logic of row output or door is worth 1, the output terminal output logic value 1 of described row output or door, the output terminal of row output or door is the row output terminal of test set generator (1), then the row output terminal is n-tThe corresponding line output of delegation's signal of output bus output and door, the capable signal of exporting when output bus is high level, then line output is worth 1 with an input end receive logic of door, described line output is the comparison signal input end of test set generator (1) with another input end of door, line output receives compare result signal with another input end of door, line output is the line output end of test set generator (1) with the output terminal of door, and then the line output end is T.
- 3. the input vector of a kind of response analysis of device based on the comparison device according to claim 2 is monitored concurrent built-in self-test circuit, it is characterized in that response analysis device (2) comprises m or door and m response analysis comparer, the input bus of response analysis device (2) is the generation signal input part of response analysis device (2), the signal of input bus output corresponding one or, the signal of exporting when input bus is high level, then or door input end receive logic value 1, described or the door output terminal output logic value 1, or the output terminal connection response of door is analyzed the test signal input end of comparer, the actual signal input end of response analysis comparer is the actual signal input end of response analysis device (2), the actual signal input end of response analysis comparer connects the output terminal of tested integrated circuit (5), the output terminal of m response analysis comparer is connected with m input end of output or door, and the output terminal of output or door is the output terminal of response analysis device (2).
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| CN101551439A (en) * | 2009-02-24 | 2009-10-07 | 北京时代民芯科技有限公司 | Built-in self-testing method of FPGA input/output module |
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| CN101551439A (en) * | 2009-02-24 | 2009-10-07 | 北京时代民芯科技有限公司 | Built-in self-testing method of FPGA input/output module |
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