CN102495357B - Input vector monitoring concurrency built-in self-test circuit based on comparator and response analyzer - Google Patents

Abstract

An input vector monitoring concurrent built-in self-test circuit based on a comparator response analyzer. It concerns the test setup of the SOC. It solves the problems existing in the existing test that the hardware cost is too high and the test delay is too large so that some circuits with many input pins cannot be monitored. The integrated circuit under test has n original input signals, select t among the original input signals as address signals, and nt as non-address signals, The combination of t address signals is not the same, and the selection signal is sent to the test set generator and the tested integrated circuit through the two-choice multiplexer; the comparator compares the selector signal with the output signal of the column, and sends it to the test set The generator sends a comparison signal; the test set generator and the integrated circuit under test issue the output signal and the actual output signal to the response analyzer respectively, and the response analyzer compares the two signals and sends the test results concurrently. It is applied to some untestable circuits for detection.

Description

A Comparator Response Analyzer Based Input Vector Monitoring Concurrent Built-In Self-Test Circuit

technical field

The invention relates to a testing device for SOC.

Background technique

In the past forty years, the development of integrated circuits has followed Moore's Law, that is, the size of integrated circuits will double every eighteen months, and now it has entered the deep submicron stage. As the scale and integration of integrated circuits continue to increase, the manufacturing cost of the chip is also reduced. However, the increase in the complexity of the chip makes the testing cost of the chip more and more high. Since the chip test cost is a part of the total chip cost, which makes the chip test cost account for an increasing proportion of the total cost, so how to reduce the chip test cost has become a problem of great concern to people.

The development of semiconductor technology has greatly improved the performance of VLSI, especially processors. However, as the size of transistors and interconnects decreases, supply voltages decrease, and circuits operate at higher frequencies, the possibility of circuit failure increases. In the actual operation of the circuit, the following three kinds of faults will be mainly encountered.

(1) Permanent failure-this kind of failure is mainly caused by physical defects in the circuit. With the advancement of semiconductor design and processing technology, the probability of such defects has become lower and lower, but they still exist in the chip.

(2) Transient failure - this kind of failure is not repeatable, mainly caused by high-energy particles (cosmic rays, alpha rays), electromagnetic interference and other factors. With the improvement of integrated circuit integration and the reduction of supply voltage, circuits are now vulnerable to transient faults induced by high-energy particles, and this fault has become the most important cause of circuit failure. The common ones are single event flipping and soft fault.

(3) Intermittent failure - this kind of failure is mainly caused by circuit operating frequency, voltage and other environmental factors and can occur repeatedly under the same conditions.

Transient faults have become the most important faults that endanger the work of chips. However, offline built-in self-test cannot detect circuit transient faults. Therefore, many online built-in self-tests have been proposed. Input vector monitoring concurrent built-in self-test is one of them. .

Previously, people put forward input vector monitoring and built-in self-test methods, such as C-BIST, RC-BIST, MCBIST, SWIM, etc., but when the circuit under test has many input pins, these methods have hardware costs and test delays. When the time is too large, the circuit under test cannot be tested.

Contents of the invention

The purpose of the present invention is to solve the problems of high hardware cost and excessive test delay in the existing input vector monitoring concurrent built-in self-test, so that some circuits with more input pins cannot be monitored, and a new method is proposed. An input vector monitoring concurrent built-in self-test circuit based on a comparator response analyzer.

二选一多路选择器的个数为n+t个，其中，第一个二选一多路选择器至第t个二选一多路选择器分别用于选择计数器的输出信号或上一级电路输出的地址信号发送给测试集发生器的t个输入端，第t+1个二选一多路选择器至第2t个二选一多路选择器分别用于选择计数器的输出信号或上一级电路输出的地址信号发送给被测集成电路的第一个输入引脚至第t个输入引脚，当所述n＞t+1时，第2t+1个二选一多路选择器至第n+t个的二选一多路选择器分别用于选择上一级电路输出的非地址信号或测试集发生器的列输出端的列输出信号发送给被测集成电路的第t+1个输入引脚至第n个输入引脚，第2t+1个二选一多路选择器至第n+t个的二选一多路选择器还分别用于选择上一级电路输出的非地址信号或测试集发生器的列输出端的列输出信号发送给比较器的第一个信号输入端至第n-t个信号输入端，比较器，用于对其输入端接收到的所有信号进行比较，并向测试集发生器的比较信号输入端发送比较结果信号；测试集发生器的行输出端发送行输出信号给响应分析器的发生信号输入端，被测集成电路的输出端发送实际输出信号给响应分析器的实际信号输入端，响应分析器用于将接收到的发生信号整理生成的测试信号，还用于将所述测试信号与实际信号进行比较，并向通过故障位标志输出端向外发送测试结果。The input vector monitoring and built-in self-test circuit based on the comparator response analyzer of the present invention includes a test set generator, an output response analyzer, a comparator and a two-to-one multiplexer; the integrated circuit to be tested has n-bit input terminals , the input signal at the input terminal is the original input signal output by the upper stage circuit, the original input signal output by the upper stage circuit is a 0 or 1 signal, and t bits are selected among the original input signals output by the n bit upper stage circuit As the address signal output by the upper-level circuit, the remaining nt bits are used as the non-address signal output by the upper-level circuit, wherein,

The number of two-to-one multiplexers is n+t, wherein, the first two-to-one multiplexer to the tth two-to-one multiplexer are respectively used to select the output signal of the counter or the last The address signal output by the stage circuit is sent to the t input terminals of the test set generator, and the t+1th two-to-one multiplexer to the 2t two-to-one multiplexer are respectively used to select the output signal of the counter or The address signal output by the upper circuit is sent to the first input pin to the tth input pin of the integrated circuit under test. When the n>t+1, the 2t+1th two-to-one multi-way selection The two-to-one multiplexer from the device to the n+tth is used to select the non-address signal output by the upper stage circuit or the column output signal of the column output terminal of the test set generator to send to the t+th integrated circuit under test 1 input pin to the nth input pin, the 2t+1th two-to-one multiplexer to the n+tth two-to-one multiplexer are also used to select the output of the upper stage circuit A non-address signal or a column output signal from the column output of the test set generator is sent to the first signal input to the ntth signal input of the comparator, which is used to compare all signals received at its input terminals , and send the comparison result signal to the comparison signal input terminal of the test set generator; the line output terminal of the test set generator sends the line output signal to the generation signal input terminal of the response analyzer, and the output terminal of the integrated circuit under test sends the actual output signal To the actual signal input terminal of the response analyzer, the response analyzer is used to sort out the received signal to generate a test signal, and also to compare the test signal with the actual signal, and send the output terminal through the fault bit flag to the outside Send test results.

The present invention is realized by reducing the hardware cost of two parts of the test set generator (test generator) and the output response analyzer 2, and the method that takes is because the OR gate is formed with a NAND gate in the test set generator 1 part, n The input OR gate is composed of n two-input AND gates, so reducing the number of input ports of the OR gate can reduce the number of NAND gates actually needed. Experimental results show that, compared with the input vector monitoring concurrent built-in self-test proposed by people before, the present invention can greatly reduce the concurrent test delay and hardware cost of the test circuit, so that some circuits that were originally untestable can be tested detection.

Description of drawings

FIG. 1 is a schematic structural diagram of an input vector monitoring concurrent built-in self-test circuit based on a comparator response analyzer, FIG. 2 is a structural schematic diagram of a test set generator 1 , and FIG. 3 is a structural schematic diagram of an output response analyzer 2 .

Detailed ways

Embodiment 1: This embodiment is described in conjunction with FIG. 1 . The input vector monitoring and built-in self-test circuit based on the comparator response analyzer in this embodiment includes a test set generator 1, an output response analyzer 2, a comparator 3 and Two to one multiplexer 4;

The integrated circuit 5 under test has an n-bit input terminal, the input signal of the input terminal is the original input signal output by the upper stage circuit, and the original input signal output by the upper stage circuit is a 0 or 1 signal, and the n-bit upper stage In the original input signal output by the circuit, the t bit is selected as the address signal output by the upper circuit, and the remaining nt bits are used as the non-address signal output by the upper circuit, wherein, ${\log }_2^T\≤t\≤\mathrm{no},$

The number of two-to-one multiplexers 4 is n+t, wherein,

The first two-to-one multiplexer 4 to the t-th two-to-one multiplexer 4 are respectively used to select the output signal of the counter or the address signal output by the upper stage circuit to send to the t of the test set generator 1 input terminal,

The t+1th two-to-one multiplexer 4 to the 2t two-to-one multiplexer 4 are respectively used to select the output signal of the counter or the address signal output by the upper circuit to send to the integrated circuit 5 under test. the first input pin to the tth input pin,

When said n>t+1, the 2t+1th two-to-one multiplexer 4 to the n+tth two-to-one multiplexer 4 are respectively used to select the non-address output by the upper stage circuit The column output signal of the column output terminal of the signal or test set generator 1 is sent to the t+1th input pin to the nth input pin of the integrated circuit 5 under test, and the 2t+1th two-to-one multiplexer The 4th to n+tth two-to-one multiplexer 4 is also used to select the non-address signal output by the upper stage circuit or the column output signal of the column output terminal of the test set generator 1 to send to the comparator 3's column output signal. From one signal input terminal to the n-tth signal input terminal, when n=t, no above-mentioned signal is sent;

The comparator 3 is used to compare all the signals received by its input terminal, and send a comparison result signal to the comparison signal input terminal of the test set generator 1;

The line output of the test set generator 1 sends the line output signal to the generation signal input of the response analyzer 2,

The output end of the integrated circuit 5 under test sends the actual output signal to the actual signal input end of the response analyzer 2,

The response analyzer 2 is used for sorting the received generated signal to generate a test signal, and is also used for comparing the test signal with the actual signal, and sending the test result to the output terminal of the fault bit flag.

Specific embodiment two: this embodiment is described in conjunction with Fig. 2, the difference between this embodiment and specific embodiment one is that the test set generator 1 includes T test vectors, T row output AND gates and n-t column output OR gates;

The t input terminals of the test set generator 1 receive the t-bit address signal output by the upper-level circuit, and the t-bit address signal output by the upper-level circuit is combined into a plurality of different input signals, and each input signal corresponds to a test vector , and send the corresponding input signal to the input of the test vector generator,

The number of the test vectors is T, and the number of bits of each test vector is n, then the test set in the test set generator 1 forms a matrix of T×n;

The t column in the n columns in the matrix is selected as the address bit, and each row in the test set constitutes a T×n matrix as a set, if the subsets v _i1 , v _i2 , v _i3 of all rows ...v _it is all different, where 1≤i≤T, that is, v _i1 , v _i2 , v _i3 ...v _it are different rows;

Each test vector has an output bus, the number of output buses is T, and the output signals output by each output bus are v _i(t+1) , v _i(t+2) , v _{i(t+ 3)} ... v _in ,

A column signal output by the output bus corresponds to a column output OR gate. When the column signal output by the output bus is high level, the input terminal of the column output OR gate receives a logic value 1, and the output terminal of the column output OR gate outputs logic Value 1, the output end of the column output OR gate is the column output end of the test set generator 1, then there are n-t column output ends,

The row signal output by the output bus corresponds to a row output AND gate. When the row signal output by the output bus is high level, one input terminal of the row output AND gate receives a logic value 1, and the other input terminal of the row output AND gate is the comparison signal input terminal of the test set generator 1, the other input terminal of the row output AND gate receives the comparison signal, and the output terminal of the row output AND gate is the row output terminal of the test set generator 1, then the row output terminals are T .

Other structures and connection methods are the same as those in the first embodiment.

For example, there are 5 test vectors in Table 1, and six letters from a to f represent the 6 input bits contained in each test vector. Selecting a, b, and d can be used as address bits, because the combinations of a, b, and d are different for these 5 test vectors, that is to say, a, b, and d are row-distinct, Similarly, a, b, and c can also be selected. But the combination of c, e and f cannot be used as address bits, because the combination (1, 0, 1) appears in the middle of test vectors 1 and 5, and they are not row-distinct.

Table 1. Schematic representation of the test set

a b c d e f vector1 0 0 1 1 0 1 vector2 0 1 1 0 1 1 vector3 1 0 1 1 1 0 vector4 0 0 0 0 1 1 vector5 1 1 1 0 0 1

Table 2. Schematic diagram of the output signal of the output bus output of the test set

d e f vector1 1 0 1 vector2 0 1 1 vector3 1 1 0 vector4 0 1 1 vector5 0 0 1

Specific embodiment three: this embodiment is described in conjunction with Fig. 3, and the difference between this embodiment and specific embodiment one or two is that the output response analyzer 2 includes m OR gates and m response analysis comparators, and the output response analyzer 2 The input bus is the signal input end of the response analyzer 2, and the signal output by the input bus corresponds to an OR gate. When the signal output by the input bus is high level, the OR gate input terminal receives a logic value 1, and the OR gate The output terminal outputs a logic value 1, and the output terminal of the OR gate is connected to the test signal input terminal of the response analysis comparator, the actual signal input terminal of the response analysis comparator is the actual signal input terminal of the response analyzer 2, and the actual signal input terminal of the response analysis comparator The input terminal is connected to the output terminal of the integrated circuit 5 under test, the output terminals of the m response analysis comparators are connected to the m input terminals of the output OR gate, and the output terminals of the output OR gate are the output terminals of the response analyzer 2 . Other structures and connection modes are the same as those in Embodiment 1 or 2.

This embodiment includes two test modes, online and offline. For the convenience of describing the operation process of the circuit, it is also assumed that the [1:3] bit of the input bit of the integrated circuit 5 under test is the address bit.

On-line test, the present invention is based on the input vector monitoring of the comparator response analyzer and the online test operation mode of the built-in self-test circuit is similar to the existing input vector monitoring and the concurrent built-in self-test online test operation mode, but the test of the present invention is not It is necessary to check whether the value in the output response analyzer 2 is equal to the expected value after all the test vectors in the test set generate hit signals. In the input vector monitoring concurrent built-in self-test circuit based on the comparator response analyzer, the output response analyzer 2 has stored the output response of each test vector in the test set. When any test vector in the test set reaches the circuit under test, it will be checked whether the output response of the circuit at this time is the same as the expected value. In addition, in the existing input vector monitoring concurrent built-in self-test, the logic unit Li can only record the first arrival of any test vector in the test set, while in the input vector monitoring concurrent built-in self-test based on the comparator response analyzer There is no need to use this logic unit in the circuit, because no matter how many times the test vector comes in the test set, based on the input vector monitoring of the comparator response analyzer and the concurrent built-in self-test circuit will compare the output response of the circuit under test with the output response The expected values stored in analyzer 2 are the same.

Off-line test, in some cases, when the circuit is running normally, some test vectors in the test set have not reached the input of the circuit under test. At this time, in order to detect the detection of all faults in the circuit, the circuit needs to be converted to offline test mode . At the same time, the off-line test of the circuit is also required in the manufacturing test and other tests, so adding the off-line test mode to the input vector monitoring and built-in self-test circuit based on the comparator response analyzer can also eliminate the need for additional off-line testing in the circuit hardware cost.

Like accumulator-based response analyzer input vector monitoring concurrent with on-line testing of BTS circuits, comparator-based response analyzer input vector monitoring concurrent BTS offline testing of existing input vector monitoring concurrent built-in self-test circuits The difference of the offline test built from the test is also that it is not necessary to check whether the data in the output response analyzer 2 is the same as the expected value after all the test vectors in the test set generate hit signals, but only when any test vector in the test set generates a hit It will be checked whether the output response at this time is equal to the expected value stored in the output response analyzer 2.

When the number of input ports of the circuit under test is too large (greater than forty), the test delay of the concurrent built-in self-test circuit using the existing input vector monitoring will reach an unacceptable level. Therefore, in order to reduce the concurrent test delay of the test circuit, compared with the existing input vector monitoring concurrent built-in self-test, the main improvement of the input vector monitoring concurrent built-in self-test circuit based on the comparator response analyzer is that the accumulator-based The output of Response Analyzer2 was changed to Comparator-based Output Response Analyzer2. Because the output response analyzer 2 based on the comparator needs to store the output of all test vectors in the test set correspondingly, changing the output response analyzer 2 based on the accumulator to the output response analyzer 2 based on the comparator will cause the test circuit hardware cost increase. In order to solve the problem of excessive hardware cost, this paper also proposes a method that can effectively reduce hardware cost. It mainly reduces the hardware cost of the circuit in two ways: 1) the test set generator, by reducing the number of two-input NAND gates Reduce hardware costs for test set generators. 2) The output response analyzer 2 reduces the hardware cost of the output response analyzer 2 by reducing the number of output ports to be monitored through output port optimization.

The content of the present invention is not limited to the content of the above-mentioned embodiments, and a combination of one or several specific embodiments can also achieve the purpose of the invention.

Claims (3)

1. A kind of input vector monitoring concurrent built-in self-test circuit based on comparator response analyzer, it is characterized in that it comprises test set generator (1), response analyzer (2), comparator (3) and two select one multiplexer(4); The test set generator (1) includes T test vectors, T row output AND gates and n-t column output OR gates; The integrated circuit (5) under test has an n-bit input terminal, the input signal of the input terminal is the original input signal output by the upper stage circuit, and the original input signal output by the upper stage circuit is a 0 or 1 signal. In the original input signal output by the first-level circuit, the t bit is selected as the address signal output by the upper-level circuit, and the remaining nt bits are used as the non-address signal output by the upper-level circuit, wherein, ${\log }_2^T\&le;t\&le;\mathrm{no},$ Two choose one multiplexer (4) number is n+t, wherein, The first two-to-one multiplexer (4) to the tth two-to-one multiplexer (4) are respectively used to select the output signal of the counter or the address signal output by the upper stage circuit to send to the test set generator t inputs of (1), The t+1th two-to-one multiplexer (4) to the 2t two-to-one multiplexer (4) are respectively used to select the output signal of the counter or the address signal output by the upper circuit to send to the measured The first input pin to the tth input pin of the integrated circuit (5), When said n>t+1, the 2t+1th two-to-one multiplexer (4) to the n+tth two-to-one multiplexer (4) are respectively used to select the upper-level circuit The output non-address signal or the column output signal of the column output terminal of the test set generator (1) is sent to the t+1th input pin to the nth input pin of the integrated circuit (5) under test, the 2t+1th input pin The two-to-one multiplexer (4) to the n+tth two-to-one multiplexer (4) are also used to select the non-address signal output by the upper stage circuit or the test set generator (1) respectively The column output signal of the column output terminal is sent to the first signal input terminal to the n-t signal input terminal of the comparator (3), The comparator (3) is used for comparing all signals received by its input terminal, and sends a comparison result signal to the comparison signal input terminal of the test set generator (1); The line output of the test set generator (1) sends the line output signal to the generation signal input of the response analyzer (2), The output terminal of the integrated circuit under test (5) sends the actual output signal to the actual signal input terminal of the response analyzer (2), The response analyzer (2) is used for sorting the generated test signal from the received generated signal, and is also used for comparing the test signal with the actual signal, and sending the test result to the output terminal of the fault bit flag. 2. A kind of input vector monitoring concurrent built-in self-test circuit based on the comparator response analyzer according to claim 1, it is characterized in that The t input terminals of the test set generator (1) receive the t-bit address signals output by the upper-level circuit, and the t-bit address signals output by the upper-level circuit are combined into a plurality of different input signals, and each input signal corresponds to a test vector, and send the corresponding input signal to the input of the test vector generator, The number of the test vectors is T, and the number of bits of each test vector is n, then the test set in the test set generator (1) forms a matrix of T × n; $\left[\begin{array}{ccc}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; no</span>}}\\ {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}}\\ & & \\ {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}\end{array}\right]$ The t column in the n columns in the matrix is selected as the address bit, and each row in the test set constitutes a T×n matrix as a set, if the subsets v _i1 , v _i2 , v _i3 of all rows ...v _it is all different, where 1≤i≤T, that is, v _i1 , v _i2 , v _i3 ...v _it are different rows; Each test vector has an output bus, the number of output buses is T, and the output signals output by each output bus are v _i(t+1) , v _i(t+2) , v _{i(t+ 3)} ... v _in , $\left[\begin{array}{cccc}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}& & {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; no</span>}}\\ {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}& & {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}}\\ & & & \\ {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}& {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}& & {\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; Tn</span>}}\end{array}\right]$ A column signal output by the output bus corresponds to a column output OR gate. When the column signal output by the output bus is high level, the input terminal of the column output OR gate receives a logic value 1, and the output terminal of the column output OR gate outputs logic Value 1, the output end of the column output OR gate is the column output terminal of the test set generator (1), then the column output terminals are n-t, The row signal output by the output bus corresponds to a row output AND gate. When the row signal output by the output bus is high level, one input terminal of the row output AND gate receives a logic value 1, and the other input terminal of the row output AND gate is the comparison signal input end of the test set generator (1), the other input end of the row output AND gate receives the comparison result signal, and the output end of the row output AND gate is the row output end of the test set generator (1), then row There are T output ports. 3. A kind of input vector monitoring based on comparator response analyzer according to claim 2 is characterized in that response analyzer (2) comprises m OR gates and m response analysis comparators, The input bus of the response analyzer (2) is the occurrence signal input terminal of the response analyzer (2), and the signal output by the input bus corresponds to an OR gate. When the signal output by the input bus is high level, the OR gate input terminal receives a logic value 1, the output terminal of the OR gate outputs logic value 1, the output terminal of the OR gate is connected to the test signal input terminal of the response analysis comparator, and the actual signal input terminal of the response analysis comparator is the actual signal input terminal of the response analyzer (2). The signal input end, the actual signal input end of the response analysis comparator is connected to the output end of the integrated circuit (5) under test, the output ends of the m response analysis comparators are connected with the m input ends of the output OR gate, and the output of the output OR gate Terminal is the output terminal of response analyzer (2).

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