CN102487301A - Method and device for recovering multilink clock - Google Patents
Method and device for recovering multilink clock Download PDFInfo
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- CN102487301A CN102487301A CN2010105689489A CN201010568948A CN102487301A CN 102487301 A CN102487301 A CN 102487301A CN 2010105689489 A CN2010105689489 A CN 2010105689489A CN 201010568948 A CN201010568948 A CN 201010568948A CN 102487301 A CN102487301 A CN 102487301A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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Abstract
The invention discloses a method and a device for recovering a multilink clock. The method and the device are used for a PTN (Packet Transport Network). The method comprises the following steps that: clock domains can be divided, wherein each clock domain comprises one or multiple links; a main clock link can be selected from the one or the multiple links of each clock domain; and the selected main clock link is subjected to the clock recovery processing, and a recovered clock can be used as a transmitter clock of each link in the clock domain to which the selected main clock link belongs. According to the technical scheme disclosed by the invention, the problem of larger expense of a hardware resource in the prior art is solved, and the resources such as an FPGA (Field Programmable Gate Array) clock phase-locked loop, a register and the like are greatly saved.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of multilink clock recovery method and device.
Background technology
In the process of legacy network IPization; A large amount of public switched telephone networks time division multiplexing (TimeDivision Multiplex abbreviates TDM as) business such as (PublicSwitched Telephone Network abbreviate PSTN as) carries over; Need unified the access and transmission; The theory of TDM over IP is arisen at the historic moment, and it sets up one " tunnel " on packet switching network, thereby the tdm data that will be packaged into the IP bag passes through bag grouping conveying network (Packet Transmission Network; Abbreviate PTN as) be transparent to the opposite end, and then realized professional (like E1 or T1) the transparent transmission in packet network of TDM.
Traditional fixed network is a standard with SDH (Synchronous Digital Hierarchy abbreviates SDH as), requires to keep clock synchronization; And network IPization back does not propose concrete requirement to clock synchronization; Therefore when professional when in IP network, transmitting, clock information can be lost, and to be reduced into the local clock of TDM business use asynchronous with the service source clock if stream will wrap in the opposite end; Sliding frame, this just so-called clock synchronization issue just will inevitably appear in long-term accumulation.
In numerous solutions, self-adaptation clock is with its unique advantage---and can adapt to service rate automatically and also occupy one seat, in PTN equipment, be widely used.Yet each bar link of equipment is all implemented the self-adaptive recovery algorithm, needs to consume hardware resources such as a large amount of phase-locked loops and register, and this expense is particularly outstanding under the situation of hardware resource deficiency.
Summary of the invention
Main purpose of the present invention is to provide a kind of multilink clock recovery method and device, one of to address the above problem at least.
According to an aspect of the present invention, a kind of multilink clock recovery method that is applied to wrap grouping conveying network is provided, has comprised: divided clock zone, wherein, comprise one or more links in each clock zone; In one or more links of each clock zone, selected master clock link; Selected master clock link is carried out clock recovery handle, and the clock after will recovering is as the tranmitting data register of each link in the clock zone under the selected master clock link.
According to another aspect of the present invention, a kind of multilink clock recovery device that is applied to wrap grouping conveying network is provided, has comprised: clock zone is divided module, is used to divide clock zone, wherein, comprises one or more links in each clock zone; The master clock link is selected module, is used for the one or more links at each clock zone, selected master clock link; Clock recovery module is used to state selected master clock link and carries out the clock recovery processing, and the clock after will recovering is as the tranmitting data register of each link in the clock zone under the selected master clock link.
Through the present invention; Be divided into a clock zone to a plurality of links in logic; Selected link is as the master clock link in this clock zone, and all links in this clock zone all send data with the clock frequency of this master clock link, have solved the bigger problem of hardware resource expense in the prior art; Practiced thrift the FPGA clock phase-locked loop greatly, resources such as register.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart according to the multilink clock recovery method of the embodiment of the invention;
Fig. 2 is the flow chart of multilink clock recovery method according to the preferred embodiment of the invention;
Fig. 3 is the flow chart of master clock system of selection according to the preferred embodiment of the invention;
Fig. 4 is the flow chart of first kind of master clock changing method according to the preferred embodiment of the invention;
Fig. 5 is the structured flowchart according to the multilink clock recovery device of the embodiment of the invention;
Fig. 6 is the structured flowchart of multilink clock recovery device according to the preferred embodiment of the invention.
Embodiment
Hereinafter will and combine embodiment to specify the present invention with reference to accompanying drawing.Need to prove that under the situation of not conflicting, embodiment and the characteristic among the embodiment among the application can make up each other.
Fig. 1 is the flow chart according to the multilink clock recovery method of the embodiment of the invention.As shown in Figure 1, comprise according to the multilink clock recovery method of the embodiment of the invention:
Step S102 divides clock zone, wherein, comprises one or more links in each clock zone.
Step S104, in one or more links of each clock zone, selected master clock link.
Step S106 carries out clock recovery to selected master clock link and handles, and the clock after will recovering is as the clock of each link in the clock zone under the master clock link that should select.
Through said method, can either satisfy user's clock demand, can practice thrift field programmable gate array (Field Programmable Gate Array abbreviates FPGA as) clock processing unit again to greatest extent.Be divided in a plurality of links in logic in the same clock zone, make each link in this clock zone all send data, guaranteed that every link clock is synchronous in the same clock zone, and be the self-adaptive recovery clock according to selected master clock frequency.This is the method that unit distributes hardware cell with the clock zone, has practiced thrift the FPGA clock phase-locked loop greatly, resources such as register.
Preferably, as shown in Figure 3, among the step S104, it is one of following that the method for selected master clock link can comprise:
Method one: in response to user's operation, selected master clock link from clock zone.
Method two: first link in the selection clock zone is as the master clock link.
The selection scheme of master clock link comprises but does not limit above-mentioned two kinds of schemes.In general, if the user has specific (special) requirements to clock, then can option is provided with this clock zone with manual mode master clock be set through the user; If the user does not have specific (special) requirements, then can adopt the Automatic Program choice mechanism, in case the clock zone link confirms that the link that just adds article one to this clock zone is as the master clock link, the link of follow-up interpolation does not influence the master clock link.
Preferably, it is one of following that the algorithm that the master clock link is carried out clock recovery can comprise: differential clocks algorithm, self-adaptation clock algorithm.
Have multiple clock recovery algorithm to select in the prior art, include but not limited to differential clocks algorithm and self-adaptation clock algorithm, just data is more complete in the prior art for these two kinds of algorithms, and it is the most convenient to realize, repeats no more here.
Preferably, as shown in Figure 2, after the step S106, can also comprise:
Step S108 when the master clock link lost efficacy, reselects a master clock link from affiliated clock zone.
In case selected master clock link service failure, just need in this clock zone, to seek again have effective traffic link as the master clock link, to guarantee system's operate as normal.
Preferably, among the step S108, it is one of following that the method for reselecting a master clock link comprises:
Method one: beginning to search according to sequencing from the next link of selected master clock link can be as the link of master clock link, specifically as shown in Figure 4.
Method two: begin to search the link that can be used as the master clock link according to numbering from the next link of selected master clock link.
Method three: set up failure logging (record), write down the Failure count of every link, after the master clock link of current selected lost efficacy, select the minimum link of Failure count as the master clock link.
Method four: in response to user's operation, selected again master clock link.
In the practical implementation process, can adopt multiple master clock handover scheme to supply the user to select, include but not limited to above-mentioned four kinds of schemes.
Scheme one is to utilize link to add the sequencing of clock zone to, carries out master clock and switches.Suppose that the sequencing that link adds clock zone A to is a, b, c, d.So at first giving tacit consent to a is master clock, in case after a lost efficacy, begin to search from b, up to finding effective clock, if b, c, d lost efficacy, and master clock need not switch so.Here why beginning to search from the back link of master clock link, is the concussion repeatedly for fear of clock selecting, for example: if a link failure; Select the b link as master clock so, in case b lost efficacy, master clock will switch to a link again; After a lost efficacy like this, b normally then switched to b again, switched repeatedly; The concussion of switching occurs, be unfavorable for the raising of the stable and clock quality of self-adaptation clock.
Method two is to utilize the numbering of the link that adds clock zone to as indexed search, and its method is similar with method one, only need index be changed into big or small the getting final product of numbering of link.
Method three utilizes the failure logging (record) of link to search; The every appearance of link was once lost efficacy; Then in its corresponding inefficacy table, add 1; So, only need add to link in the clock zone at the Failure count of this clock zone as index, search the minimum link of Failure count and get final product as the master clock link.
It is master clock that method four is switched certain road for the user specifies, and this can satisfy client's specific demand, needs manually to be provided with.
Below in conjunction with instance above-mentioned preferred embodiment is elaborated.Need to prove that the present invention is not limited to adaptive algorithm, also can introduce other differential clocks algorithms, and consult and carry out.
Suppose that real customer demand is following:
1, the communication equipment of making is linked into x possibly and opens in the SDH network;
2, the communication equipment of making need provide maximum y bar link;
To demand, economize theory most in conjunction with cost, analyze as follows:
Need the maximum x of the access network of throwing the net, the number in minimum clock territory can not be lower than x so, and just the hardware FPGA resource can maximum reduces to and has only x clock processing unit, and z clock processing unit is provided at present, and z＞=x satisfies the demands.Need the link of recovered clock add up to y (y＞=z), thus the user can confirm that (member of individual clock zone of z＜=x) is recorded as A{a respectively to z according to the clock zone at each link place of demand configuration that connects network so
1, a
2, a
3... a
n, B{b
1, b
2, b
3... b
m..., Z{z
1, z
2, z
3... z
k, there is such relation here:
With clock zone A is example, and master clock is selected to switch with master clock and all adopted method two to carry out, and clock recovery algorithm adopts the self-adaptation clock algorithm, and how detailed description realizes satisfying same clock zone internal clock stationary problem under the province of the resource situation below.
A clock zone will be realized clock synchronization, and that just can only have a reference clock, and the clock that so needs a selected link is as master clock, thereby guarantees that other business all send data according to this road clock.Do you so how confirm master clock? According to master clock system of selection two, the link clock of this clock zone is a master clock to confirm to add the first via into.The processing procedure of entire method is:
(1) during initial condition, the default setting first via adds the professional a of A clock zone
1Used clock is a master clock;
(2) other business that add the A clock zone are used a
1The clock that link-recovery comes out is as tranmitting data register;
(3) behind the selected master clock, utilize the adaptive clock recovery algorithm computation to go out regeneration rate, and send data according to this speed.
(4) this is the running of normal operating conditions lower device.In case if link a
1Go wrong, similar service disconnection is perhaps received alarm indication signal (Alarm IndicationSignal abbreviates AIS as), so just needs to switch master clock;
(5) from a
2Begin to judge other clocks in the clock zone, up to searching out one road efficient clock, just there is not any interruption in this road business, and AIS etc. are assumed to a
k, elect this link as master clock, suppose to search all over all y bar business, all there is not efficient clock, master clock also need not switch so.
(6) later on just according to a
kThe recovered clock of link instructs the business of other links to send, up to a
kFault has also appearred in link, again from a
K+1Begin to search, search a always
K-1, till searching active link.If after traveling through all business, still do not find efficient clock, need not carry out clock so and switch.
Fig. 5 is the structured flowchart according to the multilink clock recovery device of the embodiment of the invention.As shown in Figure 5, comprise according to the multilink clock recovery device of the embodiment of the invention:
Clock zone is divided module 52, is used to divide clock zone, wherein, comprises one or more links in each clock zone.
The master clock link is selected module 54, is used for the one or more links at each clock zone, selected master clock link.
Said apparatus is divided in a plurality of links in the same clock zone in logic; Make each link in this clock zone all send data according to selected master clock frequency; Guaranteed that every link clock is synchronous in the same clock zone; And be the self-adaptive recovery clock, practiced thrift the FPGA clock phase-locked loop greatly, resources such as register.
Preferably, the master clock link select module 54 may further include following one of at least:
Manually selected cell 542 is used for the operation in response to the user, selected master clock link from clock zone.
Automatic selected cell 544, first link that is used for selecting clock zone is as the master clock link.
If the user has specific (special) requirements to clock, then can the user be set option is set through manual selected cell 542, the master clock of this clock zone is set with manual mode; If the user does not have specific (special) requirements; Then can pass through automatic selected cell 544, adopt the Automatic Program choice mechanism, in case the clock zone link is confirmed; The link that just adds article one to this clock zone is as the master clock link, and the link of follow-up interpolation does not influence the master clock link.
Preferably, 56 pairs of master clock links of clock recovery module algorithm of carrying out clock recovery can comprise one of following: differential clocks algorithm, self adaptation are kind of algorithms.
Have multiple clock recovery algorithm to select in the prior art, include but not limited to differential clocks algorithm and self-adaptation clock algorithm, just data is more complete in the prior art for these two kinds of algorithms, and it is the most convenient to realize, repeats no more here.
Preferably, as shown in Figure 6, above-mentioned clock apparatus for establishing can further include:
Clock handover module 58 when being used for the inefficacy of master clock link, is reselected a master clock link from affiliated clock zone.
In case the master clock link service failure of current selected, the clock handover module 58 meetings link that there is effective traffic in searching in this clock zone again is as the master clock link, to guarantee system's operate as normal.
Preferably, as shown in Figure 6, clock handover module 58, may further include following one of at least:
Clock handover module 58 can include but not limited to above-mentioned 4 switch units, and the working method of above-mentioned 4 switch units has detailed description in method embodiment, repeat no more here.
From above description, can find out that technical scheme provided by the invention can either satisfy user's clock demand, can practice thrift FPGA clock processing unit to greatest extent again.Through being divided in same clock zone to a plurality of links in logic; Make each link in this clock zone send data according to selected master clock frequency; Guarantee that every link clock is synchronous in the same clock zone, and be the self-adaptive recovery clock, and then satisfied the demand that client traffic transmits; FPGA clock phase-locked loop, resources such as register have been practiced thrift simultaneously greatly.
Obviously, it is apparent to those skilled in the art that above-mentioned each module of the present invention or each step can realize with the general calculation device; They can concentrate on the single calculation element; Perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element; Thereby; Can they be stored in the storage device and carry out, and in some cases, can carry out step shown or that describe with the order that is different from here by calculation element; Perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a multilink clock recovery method is applied to wrap grouping conveying network, it is characterized in that, comprising:
Divide clock zone, wherein, comprise one or more links in each said clock zone;
In said one or more links of each said clock zone, selected master clock link;
Said selected master clock link is carried out clock recovery handle, and with the tranmitting data register of the clock after the said recovery as each link in the clock zone under the said selected master clock link.
2. method according to claim 1 is characterized in that, it is one of following that a said selected master clock link comprises:
In response to user's operation, selected said selected master clock link the clock zone under said;
Select first link in the clock zone under said as said selected master clock link.
3. method according to claim 1 is characterized in that, it is one of following that the said algorithm that said master clock link is carried out clock recovery comprises: differential clocks algorithm, self-adaptation clock algorithm.
4. method according to claim 1 is characterized in that, saidly said master clock link is carried out clock recovery handles, and with after the tranmitting data register of the clock after the said recovery as each link in the clock zone under the said master clock link, also comprise:
When said master clock link lost efficacy, reselect a master clock link the clock zone under said.
5. method according to claim 4 is characterized in that, reselects a master clock link the said clock zone under said and comprises one of following:
Beginning to search according to sequencing from the next link of said selected master clock link can be as the link of master clock link;
Begin to search the link that can be used as the master clock link from the next link of said selected master clock link according to numbering;
Set up failure logging (record), write down the Failure count of every link, select the minimum link of Failure count as the master clock link;
In response to user's operation, selected again master clock link.
6. a multilink clock recovery device is applied to wrap grouping conveying network, it is characterized in that, comprising:
Clock zone is divided module, is used to divide clock zone, wherein, comprises one or more links in each said clock zone;
The master clock link is selected module, is used for the said one or more links at each said clock zone, selected master clock link;
Clock recovery module is used for that said selected master clock link is carried out clock recovery and handles, and with the tranmitting data register of the clock after the said recovery as each link in the clock zone under the said selected master clock link.
7. device according to claim 6 is characterized in that, said master clock link select module comprise following one of at least:
Manually selected cell is used for the operation in response to the user, selected said selected master clock link the clock zone under said;
Automatic selected cell, first link that is used for selecting the clock zone under said is as said selected master clock link.
8. device according to claim 6 is characterized in that, it is one of following that the algorithm that said clock recovery module carries out clock recovery to said master clock link comprises: differential clocks algorithm, self adaptation are kind of algorithms.
9. device according to claim 6 is characterized in that, also comprises:
The clock handover module is used for when said master clock link lost efficacy, reselecting a master clock link the clock zone under said.
10. device according to claim 9 is characterized in that, said clock handover module comprise following one of at least:
The order switch unit, being used for beginning to search according to sequencing from the next link of said selected master clock link can be as the link of master clock link;
The numbering switch unit is used for beginning to search the link that can be used as the master clock link according to numbering from the next link of said selected master clock link;
The inefficacy switch unit is used to set up failure logging (record), writes down the Failure count of every link, when said master clock link lost efficacy, selects the minimum link of Failure count as the master clock link;
The manual switchover unit is used for the operation in response to the user, selected again master clock link.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105689489A CN102487301A (en) | 2010-12-01 | 2010-12-01 | Method and device for recovering multilink clock |
| PCT/CN2011/072125 WO2012071838A1 (en) | 2010-12-01 | 2011-03-24 | Multi-link clock recovery method and apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105689489A CN102487301A (en) | 2010-12-01 | 2010-12-01 | Method and device for recovering multilink clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102487301A true CN102487301A (en) | 2012-06-06 |
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ID=46152758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105689489A Pending CN102487301A (en) | 2010-12-01 | 2010-12-01 | Method and device for recovering multilink clock |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102487301A (en) |
| WO (1) | WO2012071838A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015117387A1 (en) * | 2014-07-23 | 2015-08-13 | 中兴通讯股份有限公司 | Method and device for switching multi-link master clock, and ptn device |
| CN105099806A (en) * | 2014-05-21 | 2015-11-25 | 中兴通讯股份有限公司 | Clock switch method and device |
| WO2017101528A1 (en) * | 2015-12-18 | 2017-06-22 | 中兴通讯股份有限公司 | Method and device for clock link switching and base station |
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| US20060291602A1 (en) * | 2005-06-23 | 2006-12-28 | Intel Corporation | Communications link clock recovery |
| CN101142773A (en) * | 2005-03-18 | 2008-03-12 | 皇家飞利浦电子股份有限公司 | Method for synchronization of network nodes |
| CN101651535A (en) * | 2009-09-01 | 2010-02-17 | 中兴通讯股份有限公司 | Method and system for recovering self-adapted service clock based on PTN |
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2010
- 2010-12-01 CN CN2010105689489A patent/CN102487301A/en active Pending
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2011
- 2011-03-24 WO PCT/CN2011/072125 patent/WO2012071838A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101142773A (en) * | 2005-03-18 | 2008-03-12 | 皇家飞利浦电子股份有限公司 | Method for synchronization of network nodes |
| US20060291602A1 (en) * | 2005-06-23 | 2006-12-28 | Intel Corporation | Communications link clock recovery |
| CN101651535A (en) * | 2009-09-01 | 2010-02-17 | 中兴通讯股份有限公司 | Method and system for recovering self-adapted service clock based on PTN |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099806A (en) * | 2014-05-21 | 2015-11-25 | 中兴通讯股份有限公司 | Clock switch method and device |
| WO2015176442A1 (en) * | 2014-05-21 | 2015-11-26 | 中兴通讯股份有限公司 | Clock switching method and device |
| WO2015117387A1 (en) * | 2014-07-23 | 2015-08-13 | 中兴通讯股份有限公司 | Method and device for switching multi-link master clock, and ptn device |
| CN105306188A (en) * | 2014-07-23 | 2016-02-03 | 中兴通讯股份有限公司 | Multilink master clock switching method, device and PTN equipment |
| WO2017101528A1 (en) * | 2015-12-18 | 2017-06-22 | 中兴通讯股份有限公司 | Method and device for clock link switching and base station |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012071838A1 (en) | 2012-06-07 |
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Application publication date: 20120606 |