CN102487035B - Deposition method of ILD with ultra low k (ULK) and porous structure - Google Patents
Deposition method of ILD with ultra low k (ULK) and porous structure Download PDFInfo
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- CN102487035B CN102487035B CN201010568476.7A CN201010568476A CN102487035B CN 102487035 B CN102487035 B CN 102487035B CN 201010568476 A CN201010568476 A CN 201010568476A CN 102487035 B CN102487035 B CN 102487035B
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Abstract
The invention provides a deposition method of an ILD with a ultra low k (ULK) and a porous structure. The method is suitable for the deposition of a medium material between a first layer metal and silicon and between the layers of the metal. The method comprises the following steps: depositing a layer of etching stopping layer on the metal layer or a silicon chip; depositing a first layer ULK film; using ultraviolet light to irradiate or carrying out heat treatment to the first ULK film and acquiring a first porous material layer; depositing a second layer ULK film; carrying out photoetching to the silicon chip and etching a channel of an integrated circuit on the silicon chip; carrying out chemical-mechanical polishing to the silicon chip so that the second ULK film is exposed; carrying out ultraviolet light irradiation to the silicon chip so as to form a second porous material layer. In the deposition method of the ILD of the porous material of the invention, through adding a layer of pores which can prevent a chemical agent from infiltrating into the porous material during the chemical-mechanical polishing process, a dielectric constant can not be increased and many other problems can be avoided.
Description
Technical field
The present invention relates to a kind of deposition process of inter-level dielectric, be specifically related to a kind of deposition process of inter-level dielectric of the ultralow dielectric with loose structure.
Background technology
In existing semiconductor fabrication process, inter-level dielectric (ILD) has served as each layer of intermetallic dielectric material.Along with manufacturing process is constantly updated and improved, reached at present the even meticulousr yardstick of 45 nanometers (nm).In order to reduce coupling capacitance, the porous materials of a kind of ultralow dielectric (ULK, Ultra Low k, k=2.4) that adopt as dielectric material, to improve the speed of service of integrated circuit more at present.
For the moulding process of inter-level dielectric, take first layer metal forming process as example, in conjunction with Fig. 1-4, it comprises the following steps: as shown in Figure 1, deposit one deck etching stop layer 102 on silicon chip, etch rate is much smaller than the material layer of silicon chip and metal, as SiCN layer; Utilize the method for the meteorological deposit (PECVD) of plasma enhanced chemical or the meteorological deposit of normal pressure chemical (APCVD), deposit super low dielectric constant film 103 on etching stop layer 102 described in silicon chip surface deposit one deck; Utilize ultraviolet light (UV) to irradiate described super low dielectric constant film 103, or described super low dielectric constant film 103 is heat-treated, obtain serving as the porous material layer 104 of ground floor interlevel dielectric material, as shown in Figure 2; Described porous material layer 104 is carried out to etching, etch raceway groove and the linked hole of integrated circuit, and in the raceway groove etching and linked hole, carry out metal deposit, make the bottom of this depositing metal 106 (can be copper) and the behaviour area (AA on silicon chip, Active Area) contact, as shown in Figure 3; Depositing metal 106 is carried out to chemical machinery grinding and polishing (CMP), grind off the unnecessary metal in top layer, thereby, first layer metal just obtained, as shown in Figure 4.Afterwards, repeat above-mentioned steps, to carry out the moulding of the metal of lower one deck.
In above-mentioned processing step, for example, at the chemical-mechanical polishing step of porous material, and in the step of cleaning acidic chemical reagent subsequently, various chemical reagent, as various acid and water, can penetrate in porous material, to porous material, porous material causes corrosion and infringement to adjacent material layer (silicon chip, metal level etc.) even, and then integrated circuit is caused to serious infringement.
Summary of the invention
In view of this, the present invention is directed to technical problem of the prior art, a kind of super low dielectric constant film that can prevent that by setting up one deck chemical reagent from infiltrating is provided, and again this layer of super low dielectric constant film is processed into porous material at subsequent step, can make the inter-level dielectric that formed by porous material with and adjacent materials layer avoid that chemical reagent corrodes, there is the deposition process of inter-level dielectric of the ultralow dielectric of loose structure.
For achieving the above object, technical scheme provided by the invention is as follows:
The deposition process of inter-level dielectric with the ultralow dielectric of loose structure, the deposit that it is applicable to the dielectric material between each layer of intermetallic and first layer metal and silicon, comprises the following steps:
Deposit one deck etching stop layer on metal level or substrate;
Deposit the first super low dielectric constant film on described etching stop layer;
Utilize ultraviolet light to irradiate or heat treatment described in the first super low dielectric constant film, obtain the first porous material layer;
Deposit the second super low dielectric constant film on described the first porous material layer;
To deposit the substrate of described the second super low dielectric constant film carry out photoetching, on substrate, etch the raceway groove of integrated circuit;
Etching depositing metal on the substrate of described raceway groove, after forming metal connecting line, substrate is carried out to chemico-mechanical polishing, described the second super low dielectric constant film is exposed;
Substrate is carried out to ultraviolet light irradiation, make described the second super low dielectric constant film form the second porous material layer.
Preferably; after the step of described deposit one deck the second super low dielectric constant film; and before described step of substrate being carried out to photoetching; also be included in the step of deposit layer protective layer on substrate, this protective layer can protect described second layer super low dielectric constant film to avoid being subject to the infringement of illumination in follow-up lithography step.
Preferably, the thickness of described etching stop layer is 30-60nm.
Preferably, the thickness of described the second porous material layer is 20-50nm.
Preferably, the dielectric constant of described etching stop layer is 3-5.
Preferably, described etching stop layer is nitrogen doped silicon carbide material.
Preferably, the dielectric constant of described the first and second porous material layers is less than 2.5.
Preferably, the material of described the first and second super low dielectric constant films is carbon doped silicon dioxide, silicone glass, a kind of in rotary carbon doped-glass.
Preferably, the material of described the first and second super low dielectric constant films is method deposits that using plasma strengthens chemical meteorological deposit or Films Prepared by APCVD.
The deposition process of the inter-level dielectric of the ultralow dielectric with loose structure of the present invention has following beneficial effect:
The deposition process of the inter-level dielectric of the ultralow dielectric with loose structure of the present invention; second super low dielectric constant film that can prevent that by set up one deck on the first porous material layer chemical reagent from infiltrating; and after etching the raceway groove and linked hole processing step of integrated circuit; again this layer second super low dielectric constant film is processed into the second porous material layer; thereby in above-mentioned etch step; first porous material layer of the second super low dielectric constant film of top to below, has played the protective effect that prevents that chemical reagent from infiltrating.The deposition process of inter-level dielectric of the present invention can make the inter-level dielectric that formed by porous material with and adjacent materials layer avoid being as much as possible subject to the erosion of chemical reagent.
Accompanying drawing explanation
Fig. 1-4th, has the deposition process schematic flow sheet of inter-level dielectric of the ultralow dielectric of loose structure in prior art;
Fig. 5-11st, the deposition process schematic flow sheet of the inter-level dielectric of the ultralow dielectric with loose structure of the present invention.
Embodiment
The deposition process of the inter-level dielectric of the ultralow dielectric with loose structure of the present invention, the super low dielectric constant film that can prevent that by setting up one deck chemical reagent from infiltrating, and after having passed through the steps such as chemico-mechanical polishing and corresponding cleaning, again this layer of super low dielectric constant film is processed into porous material, thereby avoided chemical reagent to infiltrate porous material, can make the inter-level dielectric that formed by porous material with and adjacent materials layer avoid that chemical reagent corrodes.
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Embodiment 1
Fig. 5-11 have shown the processing step of deposition process of the inter-level dielectric of a kind of ultralow dielectric with loose structure of the present invention.
The deposit of the dielectric material between first layer metal and silicon of take is below example, and the deposition process that is applicable to the porous material dielectric material between each layer of intermetallic and first layer metal and silicon of the present invention is described.First layer metal forming process, specifically comprises the following steps:
One, deposit one deck etching stop layer 202 on the silicon substrate that needs moulding first layer metal, as shown in Figure 5, this etching stop layer adopts nitrogen (N) doped silicon carbide material SiCN deposition of materials to obtain; Described etching stop layer, thickness is 30-60nm, dielectric constant is 3-5.
Two, (composition of this first super low dielectric constant film 203 is carbon doped silicon dioxide (carbon doped silicon oxide) to deposit one deck the first super low dielectric constant film 203 above described etching stop layer 202, silicone glass (organo-silicate glass), the mixture of one or several in rotary carbon doped-glass (spin-on carbon dopedglass)), as shown in Figure 5, this the first super low dielectric constant film 203 is positioned at the top of described etching stop layer 202, the dielectric constant of the material of this first super low dielectric constant film 203 is less than 2.5.
Three, utilize ultraviolet light to irradiate or heat treatment described in the first super low dielectric constant film 203, obtain the first porous material layer 204, as shown in Figure 6.Wherein, the temperature for the treatment of with ultraviolet light is 350～400 degrees Celsius, and power is 2000～4000 watts, and time general control is in 5 minutes, and the concrete numerical value of above-mentioned processing parameter need to be set according to the thickness of described the first super low dielectric constant film 203.
Four, (composition of this second super low dielectric constant film 205 is carbon doped silicon dioxide (carbon doped siliconoxide) to deposit one deck the second super low dielectric constant film 205 above described the first porous material layer 204, silicone glass (organo-silicate glass), the mixture of one or several in rotary carbon doped-glass (spin-on carbondoped glass)), as shown in Figure 7, this second super low dielectric constant film 205 is positioned at described the first porous material layer 204 tops, the dielectric constant of the material of this second super low dielectric constant film is less than 2.5.
Five, deposit layer protective layer 206 above described the second super low dielectric constant film 205, as shown in Figure 8 (composition of this protective layer 206 is silicon dioxide).This protective layer 206 can protect described the second super low dielectric constant film 205 to avoid being subject to the infringement of illumination in follow-up lithography step.
Six, to deposit the silicon chip of described second layer super low dielectric constant film 205 carry out photoetching, on silicon chip, etch the raceway groove of integrated circuit, as shown in Figure 9.
Seven, metal connecting line deposit, is etching depositing metal 207 on the silicon chip of described raceway groove, as shown in Figure 9.
Eight, silicon chip is carried out to chemico-mechanical polishing; grind off described second super low dielectric constant film 205 of depositing metal, protective layer 206 and the small part on silicon chip top layer; thereby described the second super low dielectric constant film 205 is exposed completely; as shown in figure 10, the thickness of described the second super low dielectric constant film 205 is now 20-50nm.
Nine, silicon chip being carried out to ultraviolet light irradiation or heat treatment makes described the second super low dielectric constant film 205 form the second porous material layers 208.Wherein, the better effects if of UV-irradiation; Heat treatment needs the strict temperature of controlling, can not be over 400 degrees Celsius; The quality that irradiation the latter should meet the metal material that does not affect silicon chip surface the heat treated time is as the criterion, and those skilled in the art arrange flexibly according to the thickness of described the second super low dielectric constant film 205.Described the second porous material layer 208 and described the first porous material layer 204 have formed the interlevel dielectric material between first layer metal and silicon jointly.
Next, be the moulding of carrying out second layer metal.Its processing step on the silicon chip that need to carry out moulding second layer metal according to above-mentioned from one to nine sequence of process steps, deposit second layer metal.Three, the deposition process of the 4th layer of metal by that analogy.The deposition process of the dielectric material between each wherein relating to layer intermetallic and first layer metal and silicon as mentioned above.
In above-mentioned processing step, the material of described the first and second super low dielectric constant films is method deposits that using plasma strengthens chemical meteorological deposit or the meteorological deposit of normal pressure chemical, carbon doped silicon dioxide (carbon doped silicon oxide), silicone glass (organo-silicate glass), the mixture of one or several in rotary carbon doped-glass (spin-on carbon doped glass).
The deposition process of the inter-level dielectric of the ultralow dielectric with loose structure of the present invention; second super low dielectric constant film that can prevent that by set up one deck on the first porous material layer chemical reagent from infiltrating; and after etching the raceway groove and linked hole processing step of integrated circuit; again this layer second super low dielectric constant film is processed into the second porous material layer; thereby in above-mentioned etch step; first porous material layer of the second super low dielectric constant film of top to below, has played the protective effect that prevents that chemical reagent from infiltrating.The deposition process of inter-level dielectric of the present invention can make the inter-level dielectric that formed by porous material with and adjacent materials layer avoid being as much as possible subject to the erosion of chemical reagent.
In other a kind of embodiment; can also dispense the step of deposit protective layer; in above-mentioned embodiment; after deposit one deck second super low dielectric constant film step of the 4th step; directly carry out the step that silicon chip is carried out to photoetching of the 6th step, etch raceway groove and the linked hole of integrated circuit.This technological process can be simplified procedures, and enhances productivity.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (9)
1. the deposition process of inter-level dielectric with the ultralow dielectric of loose structure, the deposit that it is applicable to the dielectric material between each layer of intermetallic or first layer metal and substrate, is characterized in that, comprises the following steps:
Deposit one deck etching stop layer on metal level or substrate;
Deposit the first super low dielectric constant film on described etching stop layer;
Utilize ultraviolet light to irradiate or heat treatment described in the first super low dielectric constant film, obtain the first porous material layer;
Deposit the second super low dielectric constant film on described the first porous material layer;
To deposit the substrate of described the second super low dielectric constant film carry out photoetching, on substrate, etch the raceway groove of integrated circuit;
Etching depositing metal on the substrate of described raceway groove, after forming metal connecting line, substrate is carried out to chemico-mechanical polishing, described the second super low dielectric constant film is exposed;
Substrate is carried out to ultraviolet light irradiation, make described the second super low dielectric constant film form the second porous material layer.
2. deposition process according to claim 1, is characterized in that, after the step of described deposit one deck the second super low dielectric constant film, and before described step of substrate being carried out to photoetching, is also included in the step of deposit layer protective layer on substrate.
3. deposition process according to claim 1, is characterized in that, the thickness of described etching stop layer is 30-60nm.
4. deposition process according to claim 1, is characterized in that, the thickness of described the second porous material layer is 20-50nm.
5. deposition process according to claim 1, is characterized in that, the dielectric constant of described etching stop layer is 3-5.
6. according to the arbitrary described deposition process of claim 1-5, it is characterized in that, described etching stop layer is nitrogen doped silicon carbide material.
7. according to the arbitrary described deposition process of claim 1-5, it is characterized in that, the dielectric constant of described the first and second porous material layers is less than 2.5.
8. deposition process according to claim 7, is characterized in that, the material of described the first and second super low dielectric constant films is carbon doped silicon dioxide, silicone glass, a kind of in rotary carbon doped-glass.
9. according to the arbitrary described deposition process of claim 1-5, it is characterized in that, the material of described the first and second super low dielectric constant films is method deposits that using plasma strengthens chemical vapor deposition or Films Prepared by APCVD.
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| US9362162B2 (en) * | 2014-08-14 | 2016-06-07 | Globalfoundries Inc. | Methods of fabricating BEOL interlayer structures |
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