CN102486807A

CN102486807A - Sub circuit signature method on basis of subgraph isomorphism

Info

Publication number: CN102486807A
Application number: CN2010105711552A
Authority: CN
Inventors: 宋晓辉; 黄国勇
Original assignee: BEIJING JINGZHI YIDA TECHNOLOGY CO LTD
Current assignee: BEIJING JINGZHI YIDA TECHNOLOGY CO LTD
Priority date: 2010-12-03
Filing date: 2010-12-03
Publication date: 2012-06-06

Abstract

The invention relates to a sub circuit signature method on the basis of subgraph isomorphism and belongs to the field of integrated circuit aided design. During layout and schematic diagram consistency verification processing, the invention provides the sub circuit signature method on the basis of the subgraph isomorphism by aiming at the characteristics of a sub circuit in a large netlist, and the inner topologies of the sub circuits with the same signature are isomorphic and are in the same type. When the sub circuit signature method is used, the matching of sub circuit nodes in the netlist can be fast completed. The method comprises the steps that: firstly, a connection relationship ordered tree of transistors forming the sub circuit is built, then, the ordered tree is subjected to posterior root traversing, structure description character strings are constructed layer by layer until the structure description character strings of the whole sub circuit are obtained, finally, signature heads are added according to internal transistor types of the sub circuit and external port types of the sub circuit, and the sub circuit signature is finally completed through the combination with the structure description character strings of the ordered tree.

Description

Electronic circuit endorsement method based on the subgraph isomorphism

Technical field

The present invention is a kind of electronic circuit endorsement method based on the subgraph isomorphism, belongs to integrated circuit Aided Design field, relates in particular to the layout verification field.

Background technology

Along with the raising of IC design level and technology, the scale of integrated circuit is increasing, and net table verification tool has been proposed increasingly high requirement.

In order to support more massive net table checking; And accomplish quickly and verify flow process; Normally dividing the circuit meshwork list of transistor level according to certain principle, obtain a plurality of electronic circuits, is node then with the electronic circuit; Form a net table higher, and then this higher level net table is done isomorphism relatively than transistor level.

How the electronic circuit node in the marked net table so that realize the electronic circuit node in the net table is mated fast, becomes the key factor that influences net table isomorphism relative efficiency.

Summary of the invention

The objective of the invention is to: a kind of electronic circuit endorsement method of using in the net table verification tool of supplying is provided, so that net table node can be accomplished coupling more fast.

The invention is characterized in: based on the electronic circuit endorsement method of subgraph isomorphism; Make up the transistor annexation tree of forming electronic circuit; While is carried out descending sort according to the number of the degree of depth, degree and the leaf node of subtree to child node, and then accomplishes the structurally ordered tree of whole electronic circuit; Then this ordered tree is adopted back root traversal; Bottom-up structrual description character string of successively constructing nodes at different levels; All by compound the obtaining of its child node structrual description character string, the structrual description character string of whole ordered tree root node is exactly the structrual description character string of whole electronic circuit to the structrual description character string of every grade of node; According to the transistorized type that constitutes electronic circuit, electronic circuit the type of external port is generated electronic circuit signature head at last, the structrual description character string of zygote circuit is accomplished the signature to electronic circuit.The electronic circuit that possesses same signature must be that inner topology isomorphism and type are consistent, utilizes this characteristics, can accomplish the coupling of net table neutron circuit node fast.

Description of drawings

Fig. 1 is a net table checking process flow diagram.

Fig. 2 is the electronic circuit illustration

Fig. 3 makes up the structurally ordered tree synoptic diagram of electronic circuit

Fig. 4 makes up electronic circuit structrual description synoptic diagram

The practical implementation step

(1) shown in Figure 1 is the process flow diagram of net table checking; After schematic diagram net table 2 extracted through the 8a electronic circuit, 10a signed to electronic circuit, and domain 4 extracts generative circuit net table through 6 net tables earlier; Same through the extraction of 8b electronic circuit; 10b signs to electronic circuit then, and latter two net table is netted table relatively 12, through 14 output comparative results.The method that 8a and 8b adopt raceway groove to be communicated with is carried out the electronic circuit extraction, and the electronic circuit that obtains is as shown in Figure 2.

(2) the structurally ordered tree of antithetical phrase circuit structure has following steps:

1) all transistors that constitute electronic circuits all are configured to the phyllome node, join the ordered tree node set, and each node data comprises the annexation (parallel connection or series connection) between the degree of depth, degree, leafy node number and the subtree of this node.If there is N pipe P pipe simultaneously in set, then be divided into two set) then to each set execution in step 2 according to type.

2) the inspection node set to having the node of series, parallel relation, generates new upper level node, and according to the number descending sort of the degree of depth, degree and the leaf node of its subtree, simultaneously, new node adds set, and involved node is deleted from set;

3) circulation carries out 2) up to there not being new node to generate.

Fig. 3 is the synoptic diagram that makes up the structurally ordered tree of the N pipe set 24 in the electronic circuit 20; 30, the 32, the 34th, when generating new node, continue to use the data of an intermediate node; Like A pipe and the series connection of B pipe, generate new node A*B, and A*B and the series connection of C pipe; Then directly the child node of C as A*B, A*B then is updated to A*B*C.And 26 and 28 have the action of ordering when constituting the upper level node.

If electronic circuit comprises N pipe and P pipe simultaneously, and two ordered trees are mutually by chance, and P tube portion circuit connects power supply, and N tube portion circuit ground is compound not gate, 20 circuit for example, otherwise this electronic circuit is split as two independent electronic circuits, each self-contained its structurally ordered tree.

(3) the ordered tree structural texture that step (2) is generated is described character string.This ordered tree is adopted the method for back root traversal; Bottom-up structrual description character string of successively constructing nodes at different levels, if current node is a leafy node, then it describes character string for " 1 "; If the child node of current node all is a leafy node; Then it describes character string for " N " (N is the child node number), and the description character string of other node is described character string compound the obtaining of SP symbol at interval for its whole child nodes, and parallelly connected symbol is "+"; The series connection symbol is " * ", obtains the structrual description character string of ordered tree root node at last.

The structrual description character string of this ordered tree is exactly the structrual description character string of this electronic circuit, if the structrual description character string of two sub-circuit is identical, then it must be the inner topology isomorphism.

(4) in order to realize that net table neutron circuit node matees more quickly and accurately; Type according to the transistor types of forming electronic circuit and electronic circuit outside port increases the signature head; The structrual description character string of zygote circuit obtains electronic circuit and finally signs, and detailed rules and regulations are following:

1) electronic circuit comprises N pipe ordered tree and P pipe ordered tree simultaneously, then is compound not gate, and the signature head is " INV ", and the back adds the structrual description character string of N pipe ordered tree.

2) have only N pipe ordered tree, if in two output ports an end ground connection is arranged, the signature head is " DOWN ", otherwise the signature head is " N ", and the back adds the structrual description character string of this N pipe ordered tree.

3) have only P pipe ordered tree, if in two output ports a termination power is arranged, the signature head is " UP ", otherwise the signature head is " P ", and the back adds the structrual description character string of this P pipe ordered tree.For example the signature of electronic circuit 20 is exactly " INV (((2*1)+3) * 1)+3+1 ", utilizes this signature, can realize that then net table electronic circuit node matees fast and accurately.

Claims

1. based on the electronic circuit endorsement method of subgraph isomorphism; It is characterized in that may further comprise the steps: 1. make up the transistor annexation tree of forming electronic circuit; The number of while according to the degree of depth, degree and the leaf node of subtree sorts to subtree, and then accomplishes the structurally ordered tree of describing whole electronic circuit; 2. this ordered tree is adopted back root traversal; Bottom-up structrual description character string of successively constructing nodes at different levels; All by compound the obtaining of its child node structrual description character string, the structrual description character string of whole ordered tree root node is exactly the structrual description character string of whole electronic circuit to the structrual description character string of every grade of node; 3. according to the transistorized type that constitutes electronic circuit, electronic circuit the type of external port is generated electronic circuit signature head, the structrual description character string of zygote circuit is accomplished the signature to electronic circuit.

2. electronic circuit endorsement method according to claim 1 is characterized in that, the structurally ordered tree that 1. makes up electronic circuit is carried out following steps:

1) transistor of all formation electronic circuits all is configured to the phyllome node, joins the ordered tree node set, if there is N pipe P pipe simultaneously in set, then is divided into two set according to type, then to each set execution in step 2);

2) the inspection node set to having the node of series, parallel relation, generates new upper level node; And according to the number of the degree of depth, degree and the leaf node of its subtree to child node descending sort; Simultaneously, new node adds set, and involved node is deletion from set;

3) circulation carries out 2) up to there not being new node to generate.

3. electronic circuit endorsement method according to claim 1; It is characterized in that; 2. the structrual description of accomplishing electronic circuit is that ordered tree is adopted back root traversal; All by compound the obtaining of its child node structrual description character string, the structrual description character string of whole ordered tree root node is exactly the structrual description character string of whole electronic circuit for bottom-up structrual description of successively constructing nodes at different levels, the structrual description character string of every grade of node.The electronic circuit that the structrual description character string is identical then must be the inner topology isomorphism.

4. electronic circuit endorsement method according to claim 1; It is characterized in that; 3. according to the transistorized type that constitutes electronic circuit, electronic circuit the type of external port is generated electronic circuit signature head; The structrual description character string of this signature zygote circuit is accomplished the signature of electronic circuit, and this signature can make and realize coupling more fast between the electronic circuit node.