CN102480292A - Baseline wander correction system and method thereof - Google Patents
Baseline wander correction system and method thereof Download PDFInfo
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- CN102480292A CN102480292A CN2010105626333A CN201010562633A CN102480292A CN 102480292 A CN102480292 A CN 102480292A CN 2010105626333 A CN2010105626333 A CN 2010105626333A CN 201010562633 A CN201010562633 A CN 201010562633A CN 102480292 A CN102480292 A CN 102480292A
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Abstract
The invention discloses a baseline wander (BLW) correction system and a method thereof. An analog-to-digital converter (ADC) converts an analog input into a digital output; and a slicer maps the digital output to one of a plurality of default values. A BLW correction unit generates a BLW correction value according to a difference value of an input and an output of the slicer; and a correction controller generates a fine correction value and a rough correction value according to the BLW correction value, wherein the fine correction value is used for correcting the digital output of the ADC and the rough correction value is used for correcting the analog input.
Description
Technical field
The present invention relates to a kind of baseline shift (baseline wander) and proofread and correct, particularly relate to a kind of baseline shift corrective system and method for communication receiver.
Background technology
Ethernet is a kind of widely used computer networking technology, can be in order to the construction LAN.For example, the transfer rate of Fast Ethernet or 100BASE-TX can reach per second 100 megabits.In the transmission end, data can be passed through a transformer before transmitting.At receiving terminal, data also can be passed through another transformer before being received by the receiver.Yet transformer itself is just as high pass filter, and it can decay or intercept the direct current composition that transmits signal, thereby produces the baseline shift effect.The baseline of the signal waveform of receiving terminal can receive the influence of baseline shift effect, particularly for a lot of plus or minus package.
There are some conventional methods can be in order to overcome the baseline shift effect.One of method is to use analog-to-digital converter (ADC), is digital signal with the analog signal conversion that receives.Then, use the baseline shift correction mechanism to carry out simultaneously the correction of analog domain and numeric field to received signal.Yet, because analog-to-digital converter tool time delay (latency), particularly pipeline (pipeline) formula analog-to-digital converter own.Therefore, can use delay line or circuit to keep (hold) analog signal usually, this will cause the increase of integrated circuit area and the increase of consumed power.
In view of traditional baseline shift corrective system does not have cost benefit, therefore need the baseline shift correction mechanism that proposes a kind of novelty badly, in order to reduce chip area and consumed power thereof.
Summary of the invention
In view of above-mentioned, one of purpose of the embodiment of the invention is to propose a kind of baseline shift corrective system and method, and it has framework, less chip area and the less power consumption of simplification.
According to the embodiment of the invention, baseline shift (BLW) corrective system comprises analog-to-digital converter (ADC), food slicer (slicer), baseline shift (BLW) correcting unit and correcting controller.Analog-to-digital converter (ADC) converts analog input into numeral output.Food slicer maps to numeral output one of them of a plurality of default values.Baseline shift (BLW) correcting unit produces baseline shift (BLW) corrected value according to the difference of the input and the output of food slicer.Correcting controller according to the BLW corrected value to produce thin corrected value and thick corrected value.Wherein, thin corrected value is exported in order to the numeral of proofreading and correct analog-to-digital converter, and thick corrected value is in order to proofread and correct the analog input of analog-to-digital converter.
Description of drawings
The calcspar of Fig. 1 shows the baseline shift corrective system of the communication receiver of the embodiment of the invention.
Fig. 2 illustration BLW corrected value, thin corrected value and thick corrected value.
The flow chart of Fig. 3 A shows the production method of thin corrected value and thick corrected value.
The numerical value that Fig. 3 B illustration is produced according to Fig. 3 A flow process.
Adjust the detail flowchart of the step of thin/thick corrected value among Fig. 4 A displayed map 3A.
The relation of amplitude M, thin corrected value F and the thick corrected value C of Fig. 4 B illustration (blocking the back) BLW corrected value.
[main element symbol description]
8 adders
9 food slicers
10 baseline shifts (BLW) correcting unit
11 thick/thin correcting controllers
12 analog-to-digital converters (ADC)
13 adders
14 analog gain/skew (gain/offset) circuit
15 digital gain circuits
16 equalizers
The 30-36 step
The 41-58 step
The thin exchange area of DOF
The thick exchange area of AOF
The amplitude of the thick corrected value of AOFM
The exchange area of OFFS BLW corrected value
The S sign bit
M (the BLW corrected value) blocks amplitude
The thin corrected value of F
The thick corrected value of C
The minimum thick step pitch of proofreading and correct of ASTEP
Embodiment
The calcspar of Fig. 1 shows the baseline shift corrective system of the communication receiver of the embodiment of the invention.The baseline shift corrective system is applicable to the Ethernet receiver, but is not limited to this.
In the present embodiment, to produce the BLW corrected value, wherein this difference can be obtained by adder 8 baseline shift (BLW) correcting unit 10 according to the input of food slicer (slicer) 9 and output difference.BLW correcting unit 10 can be implemented by conventional art, for example low pass filter.In general, food slicer is a kind of device that can input be mapped to one of a plurality of default values.
According to one of characteristic of present embodiment, thick/thin correcting controller 11 receives the BLW corrected values from BLW correcting unit 10.According to this BLW corrected value, thick/thin correcting controller 11 can produce thin corrected value and thick corrected value, and wherein thin corrected value comprises a plurality of than low order (LSB) in the BLW corrected value, and thick corrected value then comprises a plurality of higher significance bit (MSB) in the BLW corrected value.Thin corrected value is with slightly to have interdigit between the corrected value overlapping or be called exchange (swap).The width of this exchange area can be two bit widths, but is not limited to this.Fig. 2 illustration BLW corrected value, thin corrected value and thick corrected value.In this was graphic, numeral " 1 " represented 2
-1The position, numeral " 2 " represents 2
-2The position, by that analogy.Thin exchange area in the thin corrected value is denoted as DOF, and the thick exchange area in the thick corrected value then is denoted as AOF.
Thin corrected value is in order to proofread and correct the numeral output of analog-to-digital converter (ADC) 12, and it can be via being positioned at analog-to-digital converter 12 adder 13 afterwards to proofread and correct.On the other hand, thick corrected value is in order to proofread and correct the analog input of analog-to-digital converter 12, and it can be via being positioned at analog-to-digital converter 12 analog gain/skew (gain/offset) circuit 14 before to proofread and correct.
The operating principle of the BLW corrective system of Fig. 1 is following.At first, the thin corrected value that makes apparatus null value DOF is to carry out the thin correction of digital form, and the thick corrected value of this moment is zero.In case when the value of thin exchange area DOF becomes non-zero (for example 01), then non-zero DOF is copied to thick exchange area AOF, carries out the thick correction of analog form according to this.Because analog-to-digital converter 12 generally has time delay, particularly pipeline adc, so non-zero AOF will wait until always that later just can tell on time of delay.When the time comes, must reduce the value (for example being reduced to 00) of thin exchange area DOF with the value that is equivalent to non-zero AOF, to avoid exaggerated correction from 01.In other words, when after time of delay, thin exchange area DOF must reply, and makes thin corrected value and thick corrected value sum be substantially equal to the BLW corrected value.
According to above-mentioned BLW correction principle, analog gain/off-centre circuit 14 does not promptly need to adjust frequently.In other words, the switching frequency of analog gain/off-centre circuit 14 can come lowly than traditional B LW corrective system.Therefore, can effectively reduce consumed power.Moreover the complex circuit designs degree and the circuit area of analog gain/off-centre circuit 14 also can effectively reduce.
BLW corrective system shown in Figure 1 also can comprise digital gain circuits 15, and it receives the correcting digital output of adder 13.Configuration sequence that it should be noted that adder 13 and digital gain circuits 15 can be intercoursed.In addition, be positioned at the equalization that the equalizer 16 after adder 13 or the digital gain circuits 15 can carry out the output of adder 13 or digital gain circuits 15.The output of equalizer 16 then is fed to food slicer 9.
The flow chart of Fig. 3 A shows the production method of thin corrected value and thick corrected value, and the numerical value that Fig. 3 B illustration is produced according to Fig. 3 A flow process.In step 30, receive the BLW corrected value from BLW correcting unit 10.This BLW corrected value converts symbol/amplitude (sign/magnitude) form in step 31, shown in Fig. 3 B.BLW corrected value width through conversion is 11, and its first is sign bit S, and wherein numeral " 1 " represents 2
-1The position, numeral " 2 " represents 2
-2The position, by that analogy, and this BLW corrected value by normalization (normalize) to numerical value " 1 ".
Then,, the one or more of conversion back BLW corrected value are blocked (truncate) than low order (LSB), feasible many positions of amplitude bit width of blocking the bit width of amplitude M than analog-to-digital converter (ADC) in step 32.For example, like Fig. 3 B institute illustration, ADC output has seven amplitude positions, and the amplitude of blocking of BLW corrected value then has eight positions.
In step 33, obtain the maximum variable quantity of BLW corrected value.In this example, maximum variable quantity＜2
-m, m=7 wherein.LT time of delay of hypothetical simulation to digital quantizer (ADC) 12 is 6, then meets inequality 2
nThe Integer n of＞LT is 3.
Next, in step 34, slightly proofread and correct step pitch ASTEP to determine carefully/thick exchange area DOF/AOF that wherein, ASTEP can obtain according to following formula: ASTEP=2 according to minimum
-m2
n=2
-4For the example shown in Fig. 3 B, thin/thick exchange area DOF/AOF is 2 bit wides, that is 2
-3-2
-4(or position 3-4).Therefore, thin corrected value is made up of position 3-8, that is 2
-3-2
-8, wherein, thin exchange area DOF is made up of position 3-4, that is 2
-3-2
-4Thick corrected value is made up of position 1-4, that is 2
-1-2
-4, wherein, thick exchange area AOF is made up of position 3-4, that is 2
-3-2
-4In Fig. 3 B, be labeled as AOFM than the higher significance bit of thick exchange area AOF, the exchange area of blocking amplitude M of BLW corrected value then is labeled as OFFS.
In step 35, according to the BLW corrected value block amplitude M, the minimum thick step pitch ASTEP of correction and time of delay LT, thin corrected value and thick corrected value are carried out adaptability (adaptively) adjustment.Step 35 will cooperate Fig. 4 A and Fig. 4 B to be described further in following content.
Will adjust the back thin/thick corrected value is fed to adder 13 and analog gain/off-centre circuit 14 respectively to carry out before digital-to-analog proofreaies and correct; Thin after this adjustment/thick corrected value is changed back 2 complement code form, to be applicable to analog-to-digital converter (ADC) 12 (steps 36).
The detail flowchart of the step 35 of Fig. 4 A displayed map 3A (that is adjusting thin/thick corrected value), Fig. 4 B is the relation of amplitude M, thin corrected value F and the thick corrected value C of illustration (blocking the back) BLW corrected value then.
In step 41, when M＜2ASTEP, only adjust thin corrected value F, wherein M is the amplitude of blocking of BLW corrected value, and ASTEP is the minimum thick step pitch of proofreading and correct.Shown in Fig. 4 B, before time x, the thin corrected value F in adjustment back can follow amplitude M.
When M＞=2ASTEP, in step 42, adjust thin corrected value F, with thick corrected value C increment (increment), and start delay time (LT) timer.Before timer timing time of delay is accomplished (for example before the time x+LT of Fig. 4 B), only there is thin corrected value F to proofread and correct and tells on for BLW, thick corrected value C does not then tell on as yet.
When timer timing time of delay is accomplished (the for example time x+LT of Fig. 4 B) (step 43), thick corrected value C begins to tell on, and therefore, must thin exchange area DOF be given depreciation (decrement) (step 44), shown in Fig. 4 B.Thin corrected value F and the thick corrected value C sum after time of delay are substantially equal to the amplitude M of BLW corrected value, can be expressed as M (n)=F (n)+C (n-LT), and wherein n represents the time.
Then, in step 45, when the variation delta M of amplitude＜1ASTEP, only adjust thin corrected value F.As Δ M＞=1ASTEP (step 46) and when not having saturated (saturation) situation (that is, thick corrected value C do not have overflow) (step 47), then increase thin corrected value F, thick corrected value C is rised in value and start delay time timer (step 48).When timer timing time of delay is accomplished (step 49), effect can take place in thick corrected value C, therefore must thin exchange area DOF be given depreciation (step 50).On the other hand, if thick corrected value C is saturated, then do not change C value and F value (step 51).
Similar situation, in step 52, when Δ M＜-when 1ASTEP and thick corrected value are non-zero (step 53), then reduce thin corrected value F, thick corrected value C given depreciation and start delay time timer (step 54).When timer timing time of delay is accomplished (step 55), effect can take place in thick corrected value C, therefore must thin exchange area DOF be given depreciation (step 56).
On the other hand, when thick corrected value C is zero (step 53) and thin exchange area DOF when being non-zero (step 57), then thin exchange area DOF is given depreciation (step 58).Otherwise (that is M＜1ASTEP), then flow process is back to the step 41 of beginning when thick corrected value C (step 53) and thin exchange area DOF (step 57) are all zero.
According to the foregoing description, use thin corrected value and thick corrected value to be able to proofread and correct effectively the BLW effect.As previously mentioned, analog gain/off-centre circuit 14 does not need to adjust frequently, so its switching frequency can come lowly than traditional B LW corrective system.Moreover the embodiment of the invention is omitted in the conventional line formula analog-to-digital converter, in order to compensate required huge delay line or circuit of its time of delay.
The above is merely the preferred embodiments of the present invention, is not in order to limit protection scope of the present invention; All other do not break away from equivalent modifications or the modification of being accomplished under the spirit that invention discloses, and all should be included in the scope of claim.
Claims (16)
1. baseline shift corrective system comprises:
Analog-to-digital converter is in order to convert analog input into numeral output;
Food slicer is in order to export one of them that maps to a plurality of default values with said numeral;
The baseline shift correcting unit according to the difference of the input and the output of said food slicer, produces the baseline shift corrected value; And
Correcting controller is according to thin corrected value of said baseline shift correction value generating and thick corrected value;
Wherein said thin corrected value is exported in order to the numeral of proofreading and correct said analog-to-digital converter, and said thick corrected value is in order to proofread and correct the analog input of said analog-to-digital converter.
2. baseline shift corrective system as claimed in claim 1, wherein above-mentioned thin corrected value comprises a plurality of than low order of said baseline shift corrected value; Said thick corrected value comprises a plurality of higher significance bit of said baseline shift corrected value; Have the exchange area of interdigit between said thin corrected value and the said thick corrected value, it corresponds to the thin exchange area of said thin corrected value, and corresponds to the thick exchange area of said thick corrected value.
3. baseline shift corrective system as claimed in claim 2 when after the time of delay of above-mentioned analog-to-digital converter, is then adjusted said thin exchange area, makes said thin correction zone and said thick correction zone sum equal said baseline shift corrected value.
4. baseline shift corrective system as claimed in claim 1 also comprises adder, adds to said thin corrected value in order to the numeral output with said analog-to-digital converter.
5. baseline shift corrective system as claimed in claim 1 also comprises analog gain/off-centre circuit, is positioned at before the said analog-to-digital converter, according to said thick corrected value, with gain or the skew of adjusting said analog input.
6. baseline shift corrective system as claimed in claim 4 also comprises digital gain circuits, is positioned at after the said adder.
7. baseline shift corrective system as claimed in claim 6 also comprises equalizer, is positioned at after the said digital gain circuits, but is positioned at before the said food slicer.
8. baseline shift bearing calibration comprises:
Analog to digital translation, in order to analog input is converted into numeral output;
Receive the baseline shift corrected value; And
According to thin corrected value of said baseline shift correction value generating and thick corrected value;
Wherein said thin corrected value is exported in order to proofread and correct said numeral, and said thick corrected value is in order to proofread and correct said analog input.
9. baseline shift bearing calibration as claimed in claim 8, wherein above-mentioned baseline shift corrected value produces according to the input of food slicer and the difference of output.
10. baseline shift bearing calibration as claimed in claim 8, wherein above-mentioned thin corrected value comprises a plurality of than low order of said baseline shift corrected value; Said thick corrected value comprises a plurality of higher significance bit of said baseline shift corrected value; Have the exchange area of interdigit between said thin corrected value and the said thick corrected value, it corresponds to the thin exchange area of said thin corrected value, and corresponds to the thick exchange area of said thick corrected value.
11. baseline shift bearing calibration as claimed in claim 10 is simulated to the time of delay of digital translation when above-mentioned, then adjusts said thin exchange area, makes said thin correction zone and said thick correction zone sum equal said baseline shift corrected value.
12. baseline shift bearing calibration as claimed in claim 8 also comprises said numeral output is added to said thin corrected value.
13. baseline shift bearing calibration as claimed in claim 8 also comprises according to said thick corrected value, with gain or the skew of adjusting said analog input.
14. baseline shift bearing calibration as claimed in claim 12 also comprises the gain of said numeral output of adjustment and said thin corrected value sum.
15. baseline shift bearing calibration as claimed in claim 8, the step of said thin corrected value of wherein above-mentioned generation and said thick corrected value comprises:
Change said baseline shift corrected value and become symbol/amplitude form;
Block the one or more of said conversion back baseline shift corrected value, make said more said many positions of numeral output of simulating of bit width of blocking amplitude to digital translation than low order;
Obtain the maximum variable quantity of said baseline shift corrected value;
Slightly proofread and correct step pitch according to minimum, to determine said carefully/slightly exchange area; And
According to said baseline shift corrected value block amplitude, said minimum is slightly proofreaied and correct step pitch and said time of delay of simulating to digital translation, adjustment said thin corrected value and said thick corrected value with adjusting.
16. baseline shift bearing calibration as claimed in claim 15 also comprises thin after the said adjustment/thick corrected value is changed back 2 complement code form.
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| CN2010105626333A CN102480292A (en) | 2010-11-25 | 2010-11-25 | Baseline wander correction system and method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103888221A (en) * | 2014-03-20 | 2014-06-25 | 扬智科技股份有限公司 | Baseline drift compensation method, baseline correction module and Ethernet transceiver thereof |
| CN106199116A (en) * | 2016-06-28 | 2016-12-07 | 电子科技大学 | A kind of base line shifts Nonlinear Self-tuning method of digital oscilloscope |
| CN109639305A (en) * | 2017-10-09 | 2019-04-16 | 深圳市中兴微电子技术有限公司 | A kind of method and receiver for realizing data receiver processing |
| CN112886975A (en) * | 2019-11-29 | 2021-06-01 | 深圳市中兴微电子技术有限公司 | Baseline drift elimination device and receiver |
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| US20070195912A1 (en) * | 2006-02-21 | 2007-08-23 | Marvell International Ltd. | Low-latency baseline-wander compensation systems and methods |
| CN101227441A (en) * | 2007-01-17 | 2008-07-23 | 智原科技股份有限公司 | Baseline wander compensation circuit and method thereof |
| WO2010093355A1 (en) * | 2009-02-10 | 2010-08-19 | Agere Systems Inc. | Systems and methods of adaptive baseline compensation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070195912A1 (en) * | 2006-02-21 | 2007-08-23 | Marvell International Ltd. | Low-latency baseline-wander compensation systems and methods |
| CN101227441A (en) * | 2007-01-17 | 2008-07-23 | 智原科技股份有限公司 | Baseline wander compensation circuit and method thereof |
| WO2010093355A1 (en) * | 2009-02-10 | 2010-08-19 | Agere Systems Inc. | Systems and methods of adaptive baseline compensation |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103888221A (en) * | 2014-03-20 | 2014-06-25 | 扬智科技股份有限公司 | Baseline drift compensation method, baseline correction module and Ethernet transceiver thereof |
| CN103888221B (en) * | 2014-03-20 | 2017-08-04 | 扬智科技股份有限公司 | Baseline drift compensation method, baseline correct module and its ethernet transceiver |
| CN106199116A (en) * | 2016-06-28 | 2016-12-07 | 电子科技大学 | A kind of base line shifts Nonlinear Self-tuning method of digital oscilloscope |
| CN106199116B (en) * | 2016-06-28 | 2018-10-16 | 电子科技大学 | A kind of base line shifts Nonlinear Self-tuning method of digital oscilloscope |
| CN109639305A (en) * | 2017-10-09 | 2019-04-16 | 深圳市中兴微电子技术有限公司 | A kind of method and receiver for realizing data receiver processing |
| CN112886975A (en) * | 2019-11-29 | 2021-06-01 | 深圳市中兴微电子技术有限公司 | Baseline drift elimination device and receiver |
| WO2021104382A1 (en) * | 2019-11-29 | 2021-06-03 | 深圳市中兴微电子技术有限公司 | Baseline drift elimination apparatus and receiver |
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Application publication date: 20120530 |