CN102480271B - Be configured with offset cancellation loop continuous time circuit and skew eliminate method - Google Patents

Abstract

The present invention relates to be configured with circuit continuous time of offset cancellation loop.This, circuit included multistage amplifier chain and offset cancellation loop continuous time, and this amplifier chain includes first order amplifier stage and final-stage amplifier stage.This offset cancellation loop is configured to receive the output of final-stage amplifier stage, and offset correction voltage signal provides first order amplifier stage.Offset compensation loop generates a dominant pole and single important parasitic poles, in order to have more preferable stability, and can be advantageously carried out second order in response to amplitude at upper frequency and fall.Invention also discloses other embodiments, aspect and feature.

Description

Be configured with offset cancellation loop continuous time circuit and skew eliminate method

Technical field

The present invention relates generally to circuit.The skew that more particularly, the present invention relate to circuit continuous time eliminates.

Background technology

HSSI High-Speed Serial Interface (" HSSI ") may be used for the communication between device in system.Generally it is desirable that in this system Emitter send following numeral (binary) signal: it has two different level, and any from these level Individual level has the good transition defining (the most precipitous) to another level.This abrupt transition is at full speed sending Data are requisite.Generally apply to damage to the signal sent by the medium that signal is sent to receptor from emitter Consumption.These losses generally include attenuating signal amplitude and reduce transition steepness (transition steepness).

In order to maintain data transmission the most at a high speed, need circuit that these losses are compensated.A kind of compensation technique is So-called equilibrium is used at receptor.Equalizing circuit is typically first electricity met when input signal arrives receptor Road.Equalizing circuit can be designed as being amplified higher frequency, in order to strong and quickly respond at received letter The transition detected in number.This is strong and response rapidly is intended to recover the original steepness of these transition, so that receive Other circuit of device can correctly explain signal, even under the data transfer rate that this signal is the highest.

It is highly desirable to improve equalizer and other of circuit, for HSSI High-Speed Serial Interface and other application continuous time.

Summary of the invention

One embodiment relates to circuit continuous time being configured with offset cancellation loop.This, circuit included multistage continuous time Amplifier chain and offset cancellation loop, multistage amplifier chain includes first order amplifier stage and final-stage amplifier stage.Skew eliminates Loop is configured to receive the output of final-stage amplifier stage, and offset correction voltage signal provides first order amplifier Level.

First order amplifier stage can include input transistors and offset compensation transistor.The drain electrode of offset compensation transistor May be electrically connected to the source electrode of input transistors, and the voltage on the grid of offset compensation transistor can be by offset correction electricity Pressure signal determines.Single trsanscondutance amplifier can be used to produce offset correction voltage signal.Offset compensation loop can generate one Individual dominant pole and single important parasitic poles, in order to there is bigger stability, and can at upper frequency in response to Amplitude realizes second order and falls.Multistage amplifier chain can include multi-stage equalizing device chain.

Another embodiment relates to the method that the skew of circuit continuous time eliminates.Continuous time, input signal was by one Amplifier chain level receives and amplifies, in order to produce output signal continuous time.This, output signal was input to skew continuous time Cancellation loop, and offset cancellation loop generation offset correction voltage signal.This offset correction voltage signal is applied to amplify The grid of the offset compensation transistor of device level.

Another embodiment relates to integrated circuit, and it cascade circuit including having multiple equalizer stage and skew eliminate ring Road, the cascade circuit of equalizer stage includes first order equalizer stage and final stage equalizer stage.First order equalizer stage is configured to Receive differential input signal, and final stage equalizer stage is configured to export differential output signal.Offset cancellation loop is configured For receiving differential output signal, and producing differential offset correction voltage signal, it is applied in first order equalizer stage.The One-level equalizer stage includes at least one pair of input transistors, a pair offset compensation transistor and a pair resistor.Input transistors Grid be configured to receive differential input signal.The drain electrode of each offset compensation transistor is electrically connected to the input crystal of correspondence The source electrode of pipe, and the voltage being applied to the grid of offset compensation transistor determines by differential offset correction voltage signal.Each Described resistor is configured to and the channels connected in parallel of corresponding offset compensation transistor.

Invention also discloses other embodiments, aspect and feature.

Accompanying drawing explanation

Fig. 1 illustrates the custom circuit of the skew elimination for circuit continuous time.

Fig. 2 is the circuit describing the routine techniques for offset cancellation loop signal is applied to first order equalizer stage Figure.

Fig. 3 illustrates the circuit eliminated according to the skew for circuit continuous time of embodiments of the invention.

Fig. 4 is to describe, according to embodiments of the invention, offset cancellation loop signal is applied to first order equalizer/amplification The circuit diagram of device level.

Fig. 5 is to provide the conventional migration technique cancellation loop of Fig. 1 and the offset cancellation loop of the Fig. 3 according to embodiments of the invention Between the Bode diagram of comparison.

Fig. 6 illustrates the transient response of the offset compensation loop according to embodiments of the invention.

Fig. 7 compares conventional migration technique cancellation loop and the forward gain of the offset cancellation loop according to embodiments of the invention.

Fig. 8 illustrate according to embodiments of the invention for eliminate comprise a series of amplifier continuous time circuit inclined The circuit moved.

Fig. 9 is the simplification part of the field programmable gate array (FPGA) that can be configured to realize embodiments of the invention Block diagram.

Figure 10 illustrates the block diagram of the exemplary digital system that can be configured to, with embodiments of the invention.

Detailed description of the invention

Unrestriced purpose for discussion purposes, usually assumes that cascade circuit as described below receives (and output) number The number of it is believed that, these data signals are differential signals.It should be appreciated, however, that the principle of invention disclosed herein can also be applied to Single-ended signal.

Conventional cascade circuit continuous time generally uses such feedback control loop, and it filters output offset voltage, makes it By high gain amplifier and feedback current is applied to circuit the first order, thus reduce in the way of continuous time partially Move.This conventional continuous time cascade circuit with feedback control loop shown in Fig. 1.Noticing, continuous time, circuit was to continuously Time signal carries out operating rather than operating sample variance time signal.

In exemplary circuit 100 shown in FIG, four equalizer stage (Eq1, Eq2, Eq3 and Eq4) are with serial chain side Formula cascades.First order equalizer stage (Eq1) has input load (RL) and receives input current, and input current is defeated equal to skew Enter electric current (I_{OFF_IN}) deduct correcting current (I_CORR).Eq1 can be configured to be amplified higher frequency, in order to increases The transition steepness of input current.

The output of Eq1 is connected to the input of second level equalizer stage (Eq2).The output of Eq2 is connected to third level equalizer The input of level (Eq3).Finally, the output of Eq3 is connected to the input of fourth stage equalizer stage (Eq4).These other levels (Eq2, Eq3 and Eq4) in each can be configured to detected transition increases its steepness further or signal is carried out Shaping.

Illustrating further as in Fig. 1, first order trsanscondutance amplifier (gm1) drive feedback loads (by capacitor C_FAnd resistance Device R_FRepresent), it realizes the dominant pole of this feedback control loop.Miscellaneous part contribution parasitic poles in loop, these parasitic poles Point affects the phase margin of this whole loop.

In the feedback control loop of Fig. 1, there are a dominant pole and three non-trivial parasitic poles (non-trivial parasitic poles).First parasitic poles (parasitic poles 1) is owing to the input of gm1 is (i.e. at offset compensation loop Input) low pass filter (by resistor R_INWith capacitor C_INRepresent) and cause.Second parasitic poles (parasitic poles 2) causing due to second level trsanscondutance amplifier (gm2), gm2 has the input signal (V driven by gm1_CORR) and carry For correcting current (I_CORR) export as it.Trixenie limit (parasitic poles 3) is to lead due to equivalent current summation (∑) Cause, as offset cancellation loop signal (I_CORR) when being applied to the input of first order equalizer stage (Eq1), occur equivalent current to ask With.

The custom circuit of first order equalizer stage shown in Fig. 2 realizes, and it illustrates the applying of offset cancellation loop signal. As it can be seen, first order equalizer stage can include that a pair difference transistor (M1 and M2), impedance (Z1 and Z2) (have in-between Have virtual earth) and tail current source (I1 and I2).In this custom circuit, offset cancellation loop signal (I_CORR) parallel by gm2 The difference current output being fed to tail current source (being I1 and I2 respectively) (is shown as variable current source Iofn and Iofp, wherein I_CORR =Iofp-Iofn) apply.The difference output (OUTP and OUTN) of this first order provides defeated as the difference of next stage (Eq2) Enter.

As discussed above, the voltage of the routine techniques use feedback filtering offseting elimination in circuit for continuous time will Electric current is injected into compensated level.But, applicant have determined that, the stability of custom circuit can be problematic, especially for High-gain loop.Applicant believes that, the unstability of custom circuit is at least partly to cause owing to there is multiple parasitic poles 's.

Compared with eliminating circuit 100 with conventional migration technique as above, offset cancellation circuit 300 disclosed herein provides Following benefit and advantage.First, offset cancellation signal can be maintained at voltage domain during whole, without being changed To current field.Secondly, it can be advantageous to remove second level trsanscondutance amplifier (gm2).3rd, non-trivial in feedback path is parasitic The number of limit is reduced to two from three, and the minimizing of limit number adds the stability of circuit.4th, by directly controlling Switch resistance, it is possible to use less total loop gain compensates same amount of skew.In other words, the scope of skew can be big Skew in conventional method.This is because the electric current changed in compensating switch resistance rather than tail current source.Finally, mend Repay electric current not waste, as in the situation in artifact classification.

Fig. 3 illustrates the circuit 300 eliminated according to the skew for circuit continuous time of embodiments of the invention.At Fig. 3 In shown specific embodiment, four equalizer stage (Eq1, Eq2, Eq3 and Eq4) cascade in the way of serial chain.Other are implemented Example can have different number of level and/or can have cascade amplifier (rather than equalizer) level.

First order equalizer stage (Eq1) receives input current, and it is equal to skew input current (I_{OFF_IN}).Normal with Fig. 1 Rule circuit is contrary, there is not the correcting current (I produced with gm2_CORR) equivalent current summation (∑).But, by gm1 (in conjunction with By C_FAnd R_FThe feedback load represented) correction voltage (V that exports_CORR) it is sent to the first order (without gm2).

In the feedback control loop of Fig. 3, there are a dominant pole and only two non-trivial parasitic poles.First parasitic poles (parasitic poles 1) is that the low pass filter of the input due to gm1 is (by resistor R_INWith capacitor C_INRepresent) and cause. Second parasitic poles (parasitic poles A) causes due to first order equalizer stage (Eq1), and as described below, its for Phase margin analysis can be ignored.Therefore, compared to Figure 1, two harmful parasitic poles have disappeared in the feedback path of Fig. 3 Remove.

Fig. 4 illustrates the circuit realiration (Eq1 in Fig. 3) of the first order equalizer stage according to the embodiment of the present invention, and it illustrates The applying of offset cancellation loop voltage.As described below, it is possible to use this controls voltage and eliminates the skew of cascaded equalization device chain.

As it can be seen, first order equalizer stage can include a pair difference transistor (M1 and M2), a pair skew input crystalline substance Body pipe (MIsp and MIsn), a pair offset compensation transistor (Mofcp and Mofcn).This level also includes that impedance (Z1 and Z2) is (at it Between there is virtual earth), resistor (Rfxp and Rfxn) and current source (I1, I2, Isp and Isn).In this specific implementation, M1 Can be nmos pass transistor with M2, its grid width/length be Win/Lin, MIsp and MIsn can be PMOS transistor, its grid width Degree/length be W1/L1, Mofcp and Mofcn can be nmos pass transistor, its grid width/length is W2/L2.

In this circuit, the voltage output (V of trsanscondutance amplifier/low pass filter combination in Fig. 3_CORR) be directly input into To the first order, input VOFP and VOFN, wherein V as differential offset voltage_CORR=VOFP-VOFN.As shown in Figure 4, difference is inclined Move voltage input (VOFP and VOFN) and (comprised current source Isp and transistor MIsp, and electric current respectively by source class follower circuit Source Isn and transistor MIsn) buffering.Differential voltage input (vsfp and vsfn) of this buffering is applied to offset compensation transistor The grid of (being Mofcp and Mofcn respectively), these transistors are operated in " linearly " district.Note, along with NMOS crystal in linear zone Grid voltage on pipe (such as, Mofcp or Mofcn) increases, and its channel resistance declines.On the other hand, along with in linear zone Gate voltage on nmos pass transistor declines, and its channel resistance increases.

During migration, along with in response in chain DC (direct current) offset, VOFP rise and VOFN decline (otherwise also So), feedback control loop produces differential voltage.Bleeder resistor (Rfxp and Rfxn) allows some electric currents to walk around Mofcp and Mofcn.

In this circuit, correctable offset voltage amplitude parts ground by between Rfxp and Mofcp (and Rfxn and Between Mofcn) ratio of resistance determines.If more current is modulated by Mofcp and Mofcn, then correctable offset voltage Amplitude increase.But, Mofcp and Mofcn also serves as extra source-degeneration resistance device (source degeneration Resistors), which reduce and input the equivalent gain of (M1 and M2) and the bandwidth and the gain that thereby reduce this grade, i.e. Reduce AC (alternating current) performance of this grade.By select proper resistor ratio, it is possible to achieve skew eliminate and equalization stages performance it Between practicality trade off.

Under a kind of egregious cases, if removing Rfxp and Rfxn (being i.e. set to infinity or open circuit), then all electricity Stream is by Mofcp and Mofcn, and is modulated by Mofcp and Mofcn.In this case, although reached maximum attainable can The offset voltage of correction, but the AC performance of equalization stages is in minimum.Maximum attainable correctable offset voltage at least portion Divide ground by variable channel resistance (the i.e. raceway groove electricity of Mofcp and Mofcn of tail current (i.e. I1 and I2) and offset compensation transistor Resistance) the product of scope determine.Under another kind of egregious cases, if Rfxp and Rfxn is arranged to zero (i.e. short circuit), then Electric current is not had to pass through Mofcp and Mofcn and modulated by Mofcp and Mofcn.In this case, correctable offset voltage Amplitude is zero, and the AC performance of equalization stages is in maximum.

Therefore, after giving discussed above and limited fixing Rfxp and Rfxn, it is obvious that differential offset Voltage VOFP and VOFN modulation deviation effectively compensates voltage vocn and vocp, and wherein vocn is the voltage at the source electrode of M1, Vocp is the voltage at the source electrode of M2.These offset compensation voltage vocn and vocp cause differential voltage to export (OUTP and OUTN) In corresponding change in voltage, and the output of these differential voltages provides the differential voltage as next stage (Eq2) to input.

As further shown in Figure 4, non-dominant pole (non-dominant pole A) is generated (this and Fig. 3 by source class follower circuit In non-dominant pole A identical).In a kind of realization of this circuit, non-dominant pole A, at about 5 to 6GHz frequency, here has There is minimum power consumption (about 100 micromicroampere).The frequency of non-dominant pole A is significantly higher than the parasitic pole shown in (several order of magnitude) Fig. 1 The frequency of point.Therefore, for phase margin analysis, non-dominant pole A can be ignored.

Note, in the fig. 4 embodiment, by the size of appropriately designed nmos pass transistor Mofcp and Mofcn and pass through Use PMOS level displacement shifter (MIsp and MIsn is configured to source class follower), can be by nmos pass transistor Mofcp and Mofcn It is maintained in linear zone.Source class follower circuit also serves as fail safe (fail safes).Specifically, source class follower electricity Road can be configured to ensure that if the threshold voltage of MIsp and MIsn is high, then is applied to the gate voltage of Mofcp and Mofcn (vsfp and vsfn) still be enough to hold them in linear zone.

According to embodiments of the invention, offset compensation loop have one important (consequential) secondary limit ( The input of offset compensation loop) and a dominant pole.In one embodiment, although total loop of the circuit 300 in Fig. 3 increases Benefit meeting about 10dB less than total loop gain of circuit in Fig. 1 100, but the circuit of Fig. 3 300 has bigger skew and eliminates energy Power, because it using whole tail current, this tail current can be big.It addition, the loop gain reduction of circuit 300 makes in Fig. 3 Must be easier to stablize this loop.Additionally, due to do not have multiple parasitic poles, the change of technique, voltage and temperature (PVT) is to stable Property has less adverse effect.

Fig. 5 is the conventional migration technique cancellation loop 100 illustrating and providing Fig. 1 and the skew of the Fig. 3 according to the embodiment of the present invention The Bode diagram of the comparison of cancellation loop 300.This Bode diagram illustrates amplitude (in units of dB) and the phase of conventional loop and new loop Position (in units of degree) is to frequency (in units of Hz).In producing this Bode diagram, the offset cancellation loop 300 of Fig. 3 is embodied as There is the loop filter size similar with the conventional migration technique cancellation loop 100 of Fig. 1.

First baud amplitude Figure 50 2 illustrates the loop gain of the conventional migration technique cancellation loop 100 of Fig. 1, and the second baud Amplitude Figure 50 4 illustrates the loop gain of the offset cancellation loop 300 of Fig. 3.First baud phase diagram 506 illustrates that Fig. 1's is conventional inclined Moving the frequency response phase-shifted of cancellation loop 100, the second baud phase diagram 508 illustrates the frequency of the offset cancellation loop 300 of Fig. 3 Rate response phase displacement.

As shown in amplitude figure, the 0dB frequency of conventional migration technique cancellation loop 100 offset cancellation loop 300 higher than Fig. 3 0dB frequency.But, as shown in phase diagram, the conventional migration technique cancellation loop 100 of Fig. 1 has quadravalence more than 100MHz and falls (roll off), and the offset cancellation loop 300 of Fig. 3 has the most precipitous second order more than 300MHz and falls.Therefore, Fig. 1 The phase-shifted figure (starting bending at about 5MHz) of conventional migration technique cancellation loop 100 and the phase of the offset cancellation loop 300 of Fig. 3 Bit Shift figure (starting bending at about 20MHz) is compared, and starts bending under much lower frequency.

This demonstrate that phase margin improvement about 27 degree is (right for this particular dummy angle (simulation comer) In Fig. 1 loop about 60 degree phase margin and for the difference between the phase margin of the loop about 87 degree of Fig. 3).This table Bright, the offset cancellation loop 300 of Fig. 3 conventional migration technique cancellation loop 100 than Fig. 1 is the most more stable.In other words, Fig. 3's is inclined Move cancellation loop 300 and can tolerate the biggest open loop phase displacement (or time delay) before becoming instability.Other In emulation angle, the parasitic poles in the loop 100 of Fig. 1 can make this loop unstable.For given filter size, Fig. 3's Less limit in loop 300 also makes to be easier to manage loop stability.

The Bode diagram of Fig. 5 illustrates, (compared with the area of the loop filter of Fig. 1) is for the loop filter of Fig. 3, similar Area can realize the phase margin more than 80 degree.But, if relatively low phase margin (such as 60 degree) can be tolerated, that The area (compared with the area of the loop filter of Fig. 1) of the loop filter of Fig. 3 can be reduced and keep identical simultaneously Stability.

Fig. 6 illustrates the transient response of the offset compensation loop 300 according to embodiments of the invention.Top illustrate input Signal 602, it starts from 0 volt when time t=0, steps to downwards negative 60 millivolts, then exist during time to approach t=20ns Positive 60 millivolts are upwards stepped to during time to approach t=150ns.Bottom illustrate output signal 604, it is in response to input signal The DC offset voltage of 602.Specifically, with reference to Fig. 3, input signal 602 is corresponding to input signal I_{OFF_IN}Voltage, output letter Numbers 604 corresponding to voltage signal V_{OFF_OUT}.It can be seen that loop 300 needs the every of flower about 50 nanosecond compensated input signal Individual voltage step.From Fig. 6 it is further seen that, for-60mV input step, there is the residual offset of about+1mV, for+60mV , there is the residual offset of about-1mV in input step.

Fig. 7 illustrates the forward gain 702 of the conventional migration technique cancellation loop 100 of Fig. 1 and according to Fig. 3 of embodiments of the invention The forward gain 704 of offset cancellation loop 300.It can be seen that for the offset cancellation loop 300 of Fig. 3, forward gain curve The most relatively low.Applicants believe that, this is because increase transistor Mofcp and Mofcn to decrease the equivalent gain of the first order.Deng The slightly decline of effect gm also makes crest frequency and total bandwidth reduce.Therefore, in order to compensate that the gain of this grade can occur this Decline, it may be necessary to increase DC gain.

Fig. 8 illustrates the circuit 800 eliminated according to the skew for circuit continuous time of the embodiment of the present invention, this circuit 800 circuit including cascade amplifier.The circuit 300 that this circuit 800 is similar in Fig. 3.Difference is, equalizer stage chain (Eq1, Eq2, Eq3 and Eq4) is replaced by more general amplifier stage chain (Amp1, Amp2, Amp3 and Amp4).According to the present invention's Embodiment, first order amplifier stage (Amp1) can realize as shown in Figure 4.

Fig. 9 is the simplification partial block diagram of field programmable gate array (FPGA) 900, and it can include each side of the present invention Face.It should be understood that embodiments of the invention may be used for polytype integrated circuit, such as field programmable gate array (FPGA), PLD (PLD), CPLD (CPLD), programmable logic array (PLA), numeral Signal processor (DSP) and special IC (ASIC).

FPGA 900 includes the programmable logic array block (or LAB) 902 of two-dimensional array in its " core ", and it is by having The length of change and the row interconnecting conductor of speed and the network interconnection of row interconnecting conductor.LAB 902 includes multiple (such as 10) Logic element (or LE).

LE is programmable logic block, and it provides for efficiently realizing user-defined logic function.FPGA has multiple Logic element, it can be configured to realize various combination function and sequential function.Logic element can access interconnection able to programme Structure.Programmable interconnection structure can be programmed to substantially any desired configuration interconnection logic element.

FPGA 900 can also include distributed memory architecture, and it includes having change chi throughout what whole array provided Very little random access memory (RAM) block.Such as, RAM block includes block 904, block 906 and block 908.These memory blocks are also Shift register and fifo buffer can be included.

FPGA 900 may further include Digital Signal Processing (DSP) block 910, and it can realize such as having and add deduct The multiplier of feature.In this illustration, the input/output element (IOE) 912 being positioned at chip periphery is supported multiple single-ended and poor Divide input/output standard.Each IOE 912 is coupled to the outer end (i.e. pin) of FPGA 900.Transceiver (TX/RX) passage battle array Row can be arranged as shown in the figure, and the most each TX/RX channel circuit 920 is coupled to some LAB.TX/RX channel circuit 920 except Outside other circuit, it is also possible to include offset cancellation circuit described here.

Should be appreciated that and be described herein FPGA 900 merely for illustrative purpose, and the present invention can be implemented in multiple In different types of PLD, FPGA and ASIC.

If present invention may also be embodied in FPGA as in the system of one of dry part.Figure 10 illustrates and can embody this The block diagram of the exemplary digital system 1000 of bright technology.System 1000 can be digital computing system, the number programmed Word signal processing system, special digital switching network or other processing systems.Furthermore, it is possible to for this kind of system of multiple Application Design System, such as telecommunication system, automotive system, control system, consumption electronic product, personal computer, Internet traffic and Network etc..Further, system 1000 can be provided on single plate, multiple plate body, or in multiple shells.

System 1000 includes by one or more bus interconnections to processing unit 1002 together, memory cell 1004 and Input/output (I/O) unit 1006.According to this exemplary embodiment, FPGA 1008 is embedded in processing unit 1002. FPGA 1008 may be used for the multiple different purposes in system 1000.Such as, FPGA 1008 can be processing unit 1002 Logic builds block (building block), supports the operation that it is inside and outside.FPGA 1008 is programmed to realize it Logic function necessary to specific role is taken in system work.FPGA 1008 can be coupled exclusively to storage by connecting 1010 Device 1004 and 1012 be coupled exclusively to I/O unit 1006 by connecting.

Processing unit 1002 can direct the data to suitable system unit to process or storing, and performs memorizer In 1004, the program of storage, receives and sends data, or other similar functions via I/O unit 1006.Processing unit 1002 can Be CPU (CPU), microprocessor, floating-point coprocessor, graphics coprocessor, hardware control, microcontroller, It is programmed to act as the field programmable gate array of controller, network controller or any kind of processor or controller.Additionally, In many examples, it is not usually required to CPU.

Such as, one or more FPGA 1008 can substitute for the logical operation of system control cpu.As another example, FPGA 1008 is used as reconfigurable processor, and it can be reprogrammed as required, thus processes and specifically calculate task. Alternatively, FPGA 1008 itself can include Embedded System.Memory cell 1004 can be random access access Memorizer (RAM), read only memory (ROM), hard disk or flexible disk media, flash memory, tape or any other storage dress Put, or the combination of these storage devices.

In the above description, many details are given, thoroughly to understand embodiments of the invention.But, the present invention The foregoing description of the embodiment illustrated limit unintentionally or limit the invention to disclosed precise forms.People in the art Member is it will be recognized that in the case of neither one or more detail, or this can be implemented with additive method, parts etc. Bright.

In other instances, well-known structure or operation are not shown or described in detail, to avoid making the present invention Each side thicken.Although there is described herein specific embodiment and the example of the present invention for illustration purposes, but As it will be appreciated by those skilled in the art that, the most multiple equivalent modifications is possible.Can be according to the most detailed The present invention is made these amendments by thin description.

Claims (20)

1. a circuit, comprising:

Multistage amplifier chain, includes first order amplifier stage and final-stage amplifier stage at described chain；

Offset cancellation loop, its output being configured to receive described final-stage amplifier stage and offset correction voltage signal is carried It is fed to described first order amplifier stage；

Input transistors in described first order amplifier stage, described input transistors has grid, source electrode and drain electrode, Qi Zhongsuo The grid stating input transistors is configured to receive input signal；And

Offset compensation transistor in described first order amplifier stage, described offset compensation transistor has grid, source electrode and leakage Pole, the drain electrode of wherein said offset compensation transistor is electrically connected to the source electrode of described input transistors, and described migration Voltage on the grid of transistor is determined by described offset correction voltage signal.

Circuit the most according to claim 1, farther includes:

Resistor, it is configured to and the channels connected in parallel of described offset compensation transistor, one end thermocouple of wherein said resistor Close the source electrode of described offset compensation transistor, and the other end of described resistor is electrically coupled to described offset compensation transistor Drain electrode.

Circuit the most according to claim 2, farther includes:

Impedance, it is electrically coupled to the source electrode of described offset compensation transistor；And

Tail current source, it is electrically coupled to the source electrode of described offset compensation transistor.

Circuit the most according to claim 3, farther includes:

Source follower circuit in described first order amplifier stage, described source follower circuit be configured to receive described partially Correction voltage signal and produce buffer voltagc, described buffer voltagc is applied on the grid of described offset compensation transistor Voltage.

Circuit the most according to claim 4, wherein said source follower circuit includes current source and has grid, source electrode With the skew input transistors of drain electrode, wherein said offset correction voltage signal is applied to the grid of described skew input transistors Pole, and wherein said buffer voltagc results from the node between the source class of described current source and described skew input transistors On.

Circuit the most according to claim 1, wherein said offset cancellation loop includes single trsanscondutance amplifier, described single Trsanscondutance amplifier exports described offset correction voltage signal.

Circuit the most according to claim 6, wherein said offset cancellation loop farther includes:

Low pass filter, the output after it is configured to receive the output of described final-stage amplifier stage and will filter provides institute State the input of trsanscondutance amplifier.

Circuit the most according to claim 6, wherein said offset cancellation loop farther includes:

Feedback load, it is coupled to the output of described trsanscondutance amplifier.

Circuit the most according to claim 8, wherein said feedback load includes feedback resistor and feedback condenser, described Feedback resistor and feedback condenser both have the one end of the output being electrically connected to described trsanscondutance amplifier and are electrically connected to The other end on ground.

Circuit the most according to claim 1, wherein

Described input signal includes differential input signal,

Described input transistors is configured as receiving in a pair input transistors of described differential input signal,

Described offset correction voltage signal includes differential offset correction voltage signal, and

Described offset compensation transistor is one in a pair offset compensation transistor.

11. circuit according to claim 1, wherein said multistage amplifier chain includes multi-stage equalizing device chain, and first Level amplifier stage and final-stage amplifier stage include first order equalizer stage and final stage equalizer stage respectively.

12. circuit according to claim 1, wherein said offset compensation loop generates a dominant pole and single important Parasitic poles.

13. circuit according to claim 1, wherein said offset compensation loop has in response to amplitude at upper frequency Second order falls.

14. 1 kinds of integrated circuits, comprising:

Cascade circuit, it has multiple equalizer stage, and including first order equalizer stage and final stage equalizer stage, the described first order is equal Weighing apparatus level is configured to receive differential input signal, and described final stage equalizer stage is configured to export differential output signal；

Offset cancellation loop, it is configured to receive described differential output signal and produce differential offset correction voltage signal, Described differential offset correction voltage signal is applied in described first order equalizer stage；

A pair input transistors in described first order equalizer stage, the grid level of wherein said input transistors is configured to receive Described differential input signal；

A pair offset compensation transistor in described first order equalizer stage, the drain electrode of the most each offset compensation transistor is electrically connected Receive the source electrode of the input transistors of correspondence, and the voltage being applied on the grid of described offset compensation transistor is by described difference Point offset correction voltage signal determines；And

A pair resistor, each described resistor is configured to and the channels connected in parallel of corresponding offset compensation transistor.

15. integrated circuits according to claim 14, it farther includes:

Impedance, it is electrically coupled to the source electrode of described offset compensation transistor；And

Tail current source, it is electrically coupled to the source electrode of described offset compensation transistor.

16. integrated circuits according to claim 15, it farther includes: the source electrode in described first order amplifier stage with With device circuit, described source follower circuit is configured to receive described offset correction voltage signal and produce buffer voltagc, Described buffer voltagc is applied for the voltage on the grid of described offset compensation transistor.

17. integrated circuits according to claim 16, wherein said source follower circuit includes current source and has grid The skew input transistors of pole, source electrode and drain electrode, wherein said offset correction voltage signal is applied to described skew input crystalline substance The grid of body pipe, and wherein said buffer voltagc results between the source class of described current source and described skew input transistors Node on.

18. integrated circuits according to claim 14, wherein said offset cancellation loop includes single trsanscondutance amplifier, institute State single trsanscondutance amplifier and export described offset correction voltage signal.

19. integrated circuits according to claim 18, wherein said offset cancellation loop farther includes:

Low pass filter, the output after it is configured to receive the output of described final-stage amplifier stage and will filter provides institute State the input of trsanscondutance amplifier.

20. integrated circuits according to claim 18, wherein said offset cancellation loop farther includes:

Feedback load, it is coupled to the output of described trsanscondutance amplifier.