CN102479721A - Transistor and formation method thereof - Google Patents
Transistor and formation method thereof Download PDFInfo
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- CN102479721A CN102479721A CN2010105682615A CN201010568261A CN102479721A CN 102479721 A CN102479721 A CN 102479721A CN 2010105682615 A CN2010105682615 A CN 2010105682615A CN 201010568261 A CN201010568261 A CN 201010568261A CN 102479721 A CN102479721 A CN 102479721A
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Abstract
A transistor formation method comprises the following steps: providing a substrate and forming a gate structure on a substrate surface; forming a hard mask layer which comprises openings on the substrate surface, wherein the hard mask layer covers a top and two sides of the gate structure and the openings are located on two sides of the gate structure; taking the hard mask layer as a mask to etch the substrate so as to form grooves on the two sides of the gate structure; forming a stress layer which is used to fill with the grooves; forming a protective layer on a stress layer surface; removing the hard mask layer. Correspondingly, the invention also provides a transistor formed by using the above method. By using the transistor and the formation method provided in the invention, losses of the stress layer in a technology of removing the hard mask layer can be reduced and device performance can be improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly transistor and forming method thereof.
Background technology
Improving performance of semiconductor device through the control carrier mobility is the technology that receives extensive concern in the semicon industry.A key element in this technical classification is the stress in the oxide-semiconductor control transistors device channel.If suitably proof stress has improved charge carrier (electronics in the n-channel transistor, the hole in the p-channel transistor) mobility, just can improve drive current, thereby stress can greatly improve transistorized performance.
The stress liner technology forms tensile stress laying (tensile stress liner) on nmos pass transistor; On the PMOS transistor, form compression laying (compressive stress liner); Thereby increased the drive current of PMOS transistor and nmos pass transistor, improved the response speed of circuit.Certificate research, the integrated circuit of the two stress liners technology of use can bring 24% speed lifting.
Because silicon, germanium have identical lattice structure; I.e. " diamond " structure; At room temperature, the lattice constant of germanium is greater than the lattice constant of silicon, so in the transistorized source of PMOS, the drain region forms SiGe (SiGe) and can introduce the compression that lattice mismatch forms between silicon and the germanium silicon; Further improve compression, improve the transistorized performance of PMOS.Correspondingly, form carbon silicon (CSi) in source, the drain region of nmos pass transistor and can introduce the tension stress that lattice mismatch forms between silicon and the carbon silicon, further improve tension stress, improve the performance of nmos pass transistor.
In the prior art, the method that forms germanium silicon (SiGe) at the transistorized source and drain areas of PMOS is, substrate is provided, and said substrate surface is formed with grid structure; Form the hard mask layer that contains opening at said substrate surface, the position of said opening is in the grid structure both sides; With said hard mask layer is the said substrate of mask etching, forms groove in the grid structure both sides; In said groove, form SiGe; Remove said hard mask layer.But in the technology of removing said hard mask layer, can cause the loss of formed SiGe, thereby influence device performance.With the silicon nitride is example, because silicon nitride and modern semiconductors technology have very high compatibility, so often be used to form hard mask layer, in hot phosphoric acid wet method removal hard mask layer, can cause in the source, the drain region SiGe loses, thereby influence device performance.In publication number is the one Chinese patent application of CN10143190, disclose and a kind ofly controlled the method for the structure of formed groove, but still do not addressed the above problem through the control etching technics.
Summary of the invention
In view of this, the problem of the present invention's solution provides a kind of transistor formation method that can reduce the stressor layers loss of transistor grid structure both sides.
For addressing the above problem, transistor formation method provided by the present invention comprises: substrate is provided, is formed with grid structure on the said substrate surface; Form the hard mask layer that contains opening at said substrate surface, said hard mask layer covers the top and the both sides of said grid structure, and said opening is positioned at the grid structure both sides; With said hard mask layer is the said substrate of mask etching, forms groove in the grid structure both sides; Form the stressor layers of filling full said groove; Form protective layer on said stressor layers surface; Remove said hard mask layer.
Preferably, the material of said protective layer is the combination of silica and germanium oxide, or the combination of silica, germanium oxide, silicon germanium oxide.
Preferably, the material of said stressor layers is a SiGe.
Preferably, adopt rapid thermal oxidation process to form said protective layer.
Preferably, adopt furnace oxidation technology to form said protective layer.
Preferably, the technological parameter that forms the technology of protective layer is: temperature 700-1150 ℃, and pressure 100-800Torr, feeding gas is oxygen, gas flow is 0.1-100slm.
Preferably, the sedimentation time of said protective layer is 30-90s.
Preferably, the thickness of said protective layer is the 14-20 dust.
Preferably, the material of said hard mask layer is a silicon nitride.
Preferably, the technology of removing said hard mask layer is that wet method is removed technology.
Preferably, adopt epitaxy technique to form said stressor layers.
Preferably, the reacting gas that epitaxy technique adopted of formation stressor layers comprises silicon-containing gas and germanic gas at least.
Preferably, said silicon-containing gas comprises silicomethane, silicon ethane or dichloro silicomethane.
Preferably, said germanic gas comprises germane.
Correspondingly, the present invention also provides and adopts a kind of transistor, and transistor provided by the present invention comprises: substrate is formed with grid structure on the said substrate surface; Be positioned at the groove of grid both sides, and the stressor layers of filling full said groove; Be positioned at the protective layer on said stressor layers surface.
Preferably, for the PMOS transistor, the material of said stressor layers is a SiGe.
Preferably, for nmos pass transistor, the material of said stressor layers is a carbon silicon.
Preferably, said protective layer forms through rapid thermal oxidation process or furnace oxidation technology.
Preferably, the thickness of said protective layer is the 14-20 dust.
Compared with prior art, the present invention forms protective layer on the stressor layers surface, and in the process of removing hard mask, said protective layer can be protected stressor layers, thereby reduces the loss of stressor layers surface stress material, thereby improves the performance of device.
Description of drawings
Fig. 1 is the schematic flow sheet of transistor formation method provided by the present invention;
Fig. 2 to Fig. 7 is the sketch map of embodiments of the invention.
Embodiment
Can know by background technology; Thereby the stress liner technology is the means that a kind of effective raising carrier mobility speed improves performance of semiconductor device; In the step that forms stressor layers, need to form hard mask, but in the prior art; When removing hard mask, cause the loss of the material on stressor layers surface easily, thereby influence the performance of device.Inventor of the present invention studies this problem, and proposes a kind of can when removing hard mask, the generation of counter stress layer the protection in the present invention, thereby reduces the transistor formation method of stressor layers surfacing loss.
Fig. 1 is the schematic flow sheet of transistor formation method provided by the present invention, comprising:
Step S101 provides substrate, is formed with grid structure on the said substrate surface;
Step S102 forms the hard mask layer that contains opening at said substrate surface, and said hard mask layer covers the top and the both sides of said grid structure, and said opening is positioned at the grid structure both sides;
Step S103 is the said substrate of mask etching with said hard mask layer, forms groove in the grid structure both sides;
Step S104 forms the stressor layers of filling full said groove;
Step S105 forms protective layer on said stressor layers surface;
Step S106 removes said hard mask layer.
The present invention forms protective layer on the stressor layers surface, and in the process of removing hard mask, said protective layer can be protected stressor layers, thereby reduces even avoid the loss of stressor layers surface stress material, thereby improves the performance of device.
In order to make those skilled in the art better understand the present invention, the present invention is elaborated below in conjunction with accompanying drawing and specific embodiment.
Need to prove; Transistor formation method provided by the present invention both can be used to form the PMOS transistor; Also can be used to form nmos pass transistor; In the technology that forms PMOS transistor and formation nmos pass transistor, difference is that the material of stressor layers is different, and is also different through the material of the formed protective layer of oxidation technology.In the present embodiment, be example exemplarily to form the PMOS transistor, the present invention is set forth.
With reference to figure 2, substrate 100 is provided, said substrate is formed with grid structure on 100 surfaces.
Said grid structure comprises gate dielectric layer 210 and is positioned at the grid 220 on the said gate dielectric layer 210.Said substrate 100 can be silicon, germanium silicon, silicon-on-insulator etc.; Said substrate 100 comprises isolation structure 110; Said isolation structure 110 can be the silica fleet plough groove isolation structure, and said isolation structure 110 is used for the formed device of isolation of semiconductor substrate surface.The material of gate dielectric layer 210 can be high K medium materials such as silica or hafnium oxide, and the material of grid 220 can be DOPOS doped polycrystalline silicon, metal, metal silicide or other electric conducting materials.
With reference to figure 3, form the hard mask layer 101 that contains opening on said substrate 100 surfaces, said hard mask layer 101 covers the top and the both sides of said grid structure, and said opening is positioned at the grid structure both sides.
Said opening is used for forming stressor layers at subsequent technique.
The material of said hard mask layer 101 selects to have with backing material the material of big etching selection ratio, and in an embodiment of the present invention, the material of said hard mask layer 101 is silicon nitrides.Said hard mask layer 101 can not be damaged in the step of subsequent etching formation groove with the zone that forms outside source transistor, the drain region by the grill-protected electrode structure.
The step that forms said hard mask layer 101 comprises: form and cover said substrate and the top of grid structure and the silicon nitride layer of both sides; Form the photoresist that contains opening on said silicon nitride layer surface, the opening of said photoresist is positioned at the both sides source transistor to be formed of grid structure, the position in drain region; With said photoresist layer is that the said silicon nitride layer of mask etching is until exposing substrate 100, formation hard mask layer 101.
In the technology of follow-up formation stressor layers, cover top and the both sides that the hard mask layer 101 of said grid structure can the grill-protected electrode structure and can not form stressor layers; In the technology of follow-up formation protective layer, oxidation reaction can not take place in grill-protected electrode structure surface in the hard mask layer 101 that covers said grid structure, thereby avoids the loss of grid width.Suitably the thickness of adjustment hard mask layer 101 both can reach the function of above-mentioned grill-protected electrode structure, can effectively reduce the distance between stressor layers and the grid structure again, thereby improved the performance of device.
In other embodiments of the invention, can also form the thin film dielectric layer on the grid structure surface earlier, in the step that forms groove in subsequent etching grid structure is further protected.
Further, said opening adopts plasma etching method to form.
With reference to figure 4, be the said substrate 100 of mask etching with said hard mask layer 101, form groove 300 in the grid structure both sides.
Utilize lithographic method well known to those skilled in the art, etching forms groove 300 in the substrate 100 of grid structure both sides, the degree of depth of said groove 300 and width can greater than, be less than or equal to the source area that will form and the degree of depth and the width of drain region.In the present embodiment, the degree of depth of said groove 300 is less than the degree of depth of source area and drain region, and the width of said groove 300 is greater than the width of source area and drain region.
Said etching can be any conventional lithographic technique, and such as chemical etching technology or plasma etching technology, in the present embodiment, the using plasma lithographic technique adopts CF
4, CHF
3, CH
2F
2, CH
3F, C
4F
8Perhaps C
5F
8In one or several as reacting gas.
The technology of etching can be plasma etch process, specifically comprises: select inductively coupled plasma type etching apparatus for use, in etching process, for example etching gas comprises Ar and CF
4And CH
2F
2Deng fluoro-gas, CF
4And CH
2F
2Flow-rate ratio is 1: 1 to 1: 4, for example 1: 2,1: 3.In reative cell, feed above-mentioned gas simultaneously, wherein argon gas He plays the effect of dilution etching gas, and its flow is 100sccm～500sccm.Play in the gas of corrasion CF
4Flow be 10sccm～200sccm; CH
2F
2Flow be 10sccm～100sccm.Be that the power output of the radio frequency power source of plasma is 100W～1000W with said gas ionization in the reative cell, the power output of bias voltage source is 100W～1000W.Pressure in the reative cell is set to 5mTorr～20mTorr.Said etching technics can also carry out in other etching apparatus, like capacitance coupling plasma type etching apparatus, inductive couple plasma etching apparatus.
In the present embodiment, can be through control etch period control etching depth.
With reference to figure 5, form the stressor layers 310 of filling full said groove 300.
In the present embodiment, the material of said stressor layers 310 is SiGes.The formation technology of said stressor layers 310 is selective epitaxial growth process.The chamber pressure scope of said selective epitaxial growth is 1～20torr, and temperature range is 550～800 ℃.The reacting gas of said selective epitaxial growth includes silicon-containing gas and germanic gas at least.
The total flow scope of above-mentioned silicon-containing gas is 30～300sccm.The range of flow of said germanic gas is 5～500sccm.Silicon-containing gas in the said reacting gas is silicomethane, silicon ethane or dichloro silicomethane, and said germanic gas comprises germane.In the present embodiment, the total flow of said silicon-containing gas is 200sccm, and the flow of said germanic gas is 300sccm.
Further, said reacting gas can also include hydrogen chloride or hydrogen, perhaps contains hydrogen chloride and hydrogen simultaneously, and the range of flow of said hydrogen chloride gas is 50～200sccm, and the range of flow of said hydrogen is 5～50slm.In the present embodiment, the flow of said hydrogen chloride gas is 100sccm, and the flow of said hydrogen is 30slm.
Wherein, add hydrogen chloride in the said reacting gas in order to guarantee the selectivity of extension.Because in extension SiGe growth course; Only need be in the silicon face epitaxial growth of groove 300; Hard mask layer 101 surfaces need not form SiGe, thus can avoid forming SiGe through adding hydrogen chloride on hard mask layer 101 surfaces, to strengthen the uniformity of stressor layers.
With reference to figure 6, form protective layer 320 on said stressor layers 310 surfaces.
The formation technology of said protective layer 320 can be selected rapid thermal oxidation process or furnace oxidation technology.
In the technology that forms said protective layer 320, the oxidized formation silica of stressor layers 310 surface portion materials, germanium oxide and silicon germanium oxide.The parameter of rapid thermal oxidation process or furnace oxidation technology must be by strict control; To avoid oxidation reaction to cause too much SiGe loss, meanwhile, formed protective layer must be enough fine and close; Be not removed with protection stressor layers 310 in the step of follow-up removal hard mask layer 101; In addition, when forming enough fine and close protective layer 320, also need avoid hard mask layer 101 consequently can't be removed by too much oxidation.With the temperature in the reative cell is example; If temperature is too high; Cause hard mask layer 101 easily and in subsequent step, be difficult to remove,, possibly can't form the protective layer 320 that is enough to protection stressor layers 310 in removing hard mask layer 101 if temperature is low excessively because oxidation reaction takes place.Inventor of the present invention is through a large amount of experimental studies; Measure the protective layer 320 of under different technology conditions, growing and removed the forward and backward thickness of hard mask layer 101; And the thickness of removing hard mask layer 101 forward and backward stressor layers 310, and the thickness of stressor layers 310 losses.Following table is the part experimental data, and the process pressure of the protective layer 320 on sample A, B, C surface is identical with air-flow in the formation following table, and temperature and sedimentation time are inequality, and the unit of thickness is a dust in the table.
Can find out by last table; Consider the measure error in measuring thickness, to sample A and B, in removing the hard mask layer process; Do not cause the loss of stressor layers 310; Stressor layers 310 total losses cause by oxidation technology, are 0.44 because counter stress layer 310 carries out the ratio of protective layer 320 that oxidation obtains and the density of stressor layers 310, so the thickness of the protective layer 320 that the computational methods of the loss amount of the stressor layers 310 that oxidation technology causes are oxidations to be formed multiply by 0.44; The protective layer on sample C surface is not enough in the technology of removing hard mask 101, protect stressor layers not lost, and sample D surface does not have protective layer, and the loss of stressor layers 310 is maximum.The inventor finds that through a large amount of experiments in removing hard mask layer 101 processes, through the technology of reasonable adjusting formation protective layer 320, the stressor layers up to 68% loss can be avoided, thereby can effectively improve the performance of device.
The inventor is through analyzing a large amount of experimental datas; Drawing the optimized parameters that forms protective layer 320 is: temperature 700-1150 ℃, and pressure 100-800Torr, feeding gas is oxygen; Gas flow is 0.1-100slm, and the sedimentation time of protective layer 320 is 30-90s.The thickness of the protective layer 320 that forms is the 14-20 dust.The protective layer 320 that adopts above-mentioned technological parameter to form is being enough to protect stressor layers not removed while in the step of follow-up removal hard mask layer, can not increase the difficulty of the technology of removing hard mask layer.
With reference to figure 7, remove said hard mask layer 101.
Adopt wet method to remove technology and remove hard mask layer 101, in the present embodiment, adopt hot phosphoric acid to remove said hard mask layer 101.Because stressor layers 310 surfaces are formed with protective layer 320, the technology of said above-mentioned removal hard mask layer 101 can not cause the loss of stressor layers 310.
In subsequent step, also be included in technologies such as doping formation source, grid structure both sides, leakage,, repeat no more at this because the technology of formation source, leakage has been well known to those skilled in the art.
Schematically illustrate in the present embodiment in PMOS source transistor, drain region and form silicon Germanium stress layer; And adopt oxidation technology to form the method that protective layer is not lost with the said silicon Germanium stress layer of protection in the technology of follow-up removal silicon nitride hard mask layer at the silicon Germanium stress laminar surface; In other embodiments of the invention; Said stressor layers also can adopt other materials, and such as SiGe boron, perhaps surface coverage has the sige alloy of polysilicon layer.Correspondingly, transistor formation method provided by the present invention also can be used for nmos pass transistor, and wherein the material of stressor layers can be selected materials such as carbon silicon.
Correspondingly, the present invention also provides through the formed transistor of above-mentioned transistor formation method.Please continue with reference to figure 7, transistor provided by the present invention comprises: substrate 100, and said substrate is formed with grid structure on 100 surfaces; Be positioned at the grid both sides, be positioned at the groove of grid both sides, and the stressor layers 310 of filling full said groove; Be positioned at the protective layer 320 on said stressor layers 310 surfaces.
Wherein, if formed be the PMOS transistor, the material of said stressor layers 310 is SiGes; If what form is nmos pass transistor, the material of said stressor layers 310 is a carbon silicon.
Said protective layer 320 forms through rapid thermal oxidation process or furnace oxidation technology.The thickness of said protective layer 320 is 14-20 dusts.
To sum up, the present invention is through forming the method for protective layer on the stressor layers surface, and the protection stressor layers no longer is removed in the subsequent technique, thereby reduces the loss of stressor layers, and improves the performance of device.
The above is merely specific embodiment of the present invention; In order to make those skilled in the art better understand spirit of the present invention; Yet protection scope of the present invention is not a limited range with the specific descriptions of this specific embodiment; Any those skilled in the art can make an amendment specific embodiment of the present invention, and not break away from protection scope of the present invention in the scope that does not break away from spirit of the present invention.
Claims (19)
1. a transistor formation method is characterized in that, comprising:
Substrate is provided, is formed with grid structure on the said substrate surface;
Form the hard mask layer that contains opening at said substrate surface, said hard mask layer covers the top and the both sides of said grid structure, and said opening is positioned at the grid structure both sides;
With said hard mask layer is the said substrate of mask etching, forms groove in the grid structure both sides;
Form the stressor layers of filling full said groove;
Form protective layer on said stressor layers surface;
Remove said hard mask layer.
2. according to the transistor formation method of claim 1, it is characterized in that the material of said protective layer is the combination of silicon dioxide and germanium oxide, or the combination of silica, germanium oxide, silicon germanium oxide.
3. according to the transistor formation method of claim 2, it is characterized in that, adopt rapid thermal oxidation process to form said protective layer.
4. according to the transistor formation method of claim 2, it is characterized in that, adopt furnace oxidation technology to form said protective layer.
5. according to the transistor formation method of claim 3 or 4, it is characterized in that the technological parameter that forms the technology of protective layer is: temperature 700-1150 ℃, pressure 100-800Torr, feeding gas is oxygen, gas flow is 0.1-100slm.
6. according to the transistor formation method of claim 5, it is characterized in that the sedimentation time of said protective layer is 30-90s.
7. according to the transistor formation method of claim 1, it is characterized in that the thickness of said protective layer is the 14-20 dust.
8. according to the transistor formation method of claim 1, it is characterized in that the material of said hard mask layer is a silicon nitride.
9. according to the transistor formation method of claim 8, it is characterized in that the technology of removing said hard mask layer is that wet method is removed technology.
10. according to the transistor formation method of claim 1, it is characterized in that the material of said stressor layers is a SiGe.
11. the transistor formation method according to claim 10 is characterized in that, adopts epitaxy technique to form said stressor layers.
12. the transistor formation method according to claim 10 is characterized in that, the reacting gas that epitaxy technique adopted that forms stressor layers comprises silicon-containing gas and germanic gas at least.
13. the transistor formation method according to claim 12 is characterized in that, said silicon-containing gas comprises silicomethane, silicon ethane or dichloro silicomethane.
14. the transistor formation method according to claim 12 is characterized in that, said germanic gas comprises germane.
15. a transistor is characterized in that, comprising:
Substrate is formed with grid structure on the said substrate surface;
Be positioned at the groove of grid both sides, and the stressor layers of filling full said groove;
Be positioned at the protective layer on said stressor layers surface.
16. the transistor according to claim 15 is characterized in that, for the PMOS transistor, the material of said stressor layers is a SiGe.
17. the transistor according to claim 15 is characterized in that, for nmos pass transistor, the material of said stressor layers is a carbon silicon.
18. the transistor according to claim 15 is characterized in that, said protective layer forms through rapid thermal oxidation process or furnace oxidation technology.
19. the transistor according to claim 15 is characterized in that, the thickness of said protective layer is the 14-20 dust.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103594374A (en) * | 2012-08-17 | 2014-02-19 | 中国科学院微电子研究所 | Manufacturing method for semiconductor device |
| CN107403725A (en) * | 2016-05-19 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of silicon nitride film minimizing technology and semiconductor devices |
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| US20100052074A1 (en) * | 2008-08-26 | 2010-03-04 | Chien-Ting Lin | Metal gate transistor and method for fabricating the same |
| CN101673676A (en) * | 2008-09-10 | 2010-03-17 | 台湾积体电路制造股份有限公司 | Method of fabricating semiconductor device |
| CN101872742A (en) * | 2009-04-22 | 2010-10-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method |
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| US20100052074A1 (en) * | 2008-08-26 | 2010-03-04 | Chien-Ting Lin | Metal gate transistor and method for fabricating the same |
| CN101673676A (en) * | 2008-09-10 | 2010-03-17 | 台湾积体电路制造股份有限公司 | Method of fabricating semiconductor device |
| CN101872742A (en) * | 2009-04-22 | 2010-10-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103594374A (en) * | 2012-08-17 | 2014-02-19 | 中国科学院微电子研究所 | Manufacturing method for semiconductor device |
| CN103594374B (en) * | 2012-08-17 | 2017-03-08 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| CN107403725A (en) * | 2016-05-19 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of silicon nitride film minimizing technology and semiconductor devices |
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