CN102467218A - Method for turning off power - Google Patents
Method for turning off power Download PDFInfo
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- CN102467218A CN102467218A CN2010105542412A CN201010554241A CN102467218A CN 102467218 A CN102467218 A CN 102467218A CN 2010105542412 A CN2010105542412 A CN 2010105542412A CN 201010554241 A CN201010554241 A CN 201010554241A CN 102467218 A CN102467218 A CN 102467218A
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Abstract
The invention discloses a method for turning off power and is applicable to a server system. The server system is provided with a first node, a second node and a power supply, and the first node and the second node share the power supply. The method for turning off the power comprises the following steps of: according to a power turning-off signal, respectively executing a power turning-off program by using the first node and the second node; starting an interception program to intercept an accomplishment signal which is generated in the power turning-off program, and triggering interruption; processing the interruption by using an interruption processing program to detect whether the first node and the second node accomplish the power turning-off program; and when the first node and the second node accomplish the power turning-off program, closing the interception program, restoring the generated accomplishment signal, and providing the power supply to turn off the power.
Description
Technical field
The invention relates to a kind of server system and power-off disposal route, and particularly relevant for a kind of server system and power-off disposal route of common source supply.
Background technology
In general; Can dispose the computer systems of at least two independent runnings in server (server) system of part; And the shared each other power supply unit of these two computer systems and a baseboard management controller (baseboard management controller; BMC), saving traditional server, and then reduce cost to the demand of the device space and the quantity of power supply unit.
When server system was in normal operation and user and pushes the power switch on the server system, baseboard management controller can be given computer system by corresponding generation power-off signal, carries out the power-off program to cause the operating system in the computer system.When accomplishing the power-off program, can computer system produce a completion power-off signal to power supply unit, with the power supply that supply was provided of cutting off the electricity supply, to reach the effect of power-off.
Yet, because above-mentioned two computer systems are independent running each other, that is computer system carry out power-off program institute's time spent also can be different.Therefore, when server system when carrying out the power-off handling procedure, if one of them computer system is accomplished power-off program earlier, promptly can produce and accomplish the power-off signal and cut off the electricity supply to power supply unit.At this moment, because power supply unit has stopped providing power supply, will cause another the computer system generation data loss of not accomplishing the power-off program as yet and the situation of access errors.
Summary of the invention
The present invention provides a kind of server system and power-off disposal route, makes the node in the server system can carry out power-off synchronously, causes the situation of data loss and access errors to take place to avoid nonsynchronous power-off process.
The present invention proposes a kind of power-off disposal route, is suitable for a server system, and this server system has first node, Section Point and power supply unit, and first node and the shared above-mentioned power supply unit of Section Point.Above-mentioned power-off disposal route comprises the following steps.According to the power-off signal, first node and Section Point are carried out the following step respectively.At first, carry out the power-off program.Then, start a hook procedure,, and trigger one first interruption with the completion signal that produces in the interception power-off program.Afterwards, handle above-mentioned first by interrupt handling routine and interrupt, whether accomplish the power-off program to detect first node and Section Point.Then, accomplished the power-off program, then closed this hook procedure, and recovered the completion signal that produces in this power-off program, and transmitted and accomplish signal to power supply unit, with the power supply of powered-down supply when first node and Section Point.
In one embodiment of this invention; The input port of above-mentioned first node couples the output port of Section Point; And the output port of first node couples the input port of Section Point, and whether accomplishes the power-off program and comprise the following steps detecting first node and Section Point.In the detection step of first node, whether the input port whether output port of detection first node produces first logical signal and first node receives second logical signal.And in the detection step of Section Point, whether the input port whether output port of detection Section Point produces second logical signal and Section Point receives first logical signal.
In one embodiment of this invention, the step of the above-mentioned completion signal that in recovering the power-off program, produces comprises a preset value is write a register.
In one embodiment of this invention, (system management interrupt, SMI), and above-mentioned interrupt handling routine is system management interrupt handling procedure (SMI handler) for system management interrupt in above-mentioned first interruption.
In one embodiment of this invention, above-mentioned power-off disposal route more comprises by baseboard management controller generation power-off signal.
In one embodiment of this invention, above-mentioned step in the power-off program of execution comprises according to one second interruption, carries out the power-off program by an operating system.
In one embodiment of this invention, above-mentioned second interrupt for system's control interruption (system control interrupt, SCI).
In one embodiment of this invention, first node and Section Point comprise CPU, north bridge chips and South Bridge chip respectively.North bridge chips couples CPU.South Bridge chip couples north bridge chips.Wherein, the South Bridge chip of first node couples the South Bridge chip of Section Point, and the input port of the South Bridge chip of first node and output port couple the output port and the input port of the South Bridge chip of Section Point respectively.
The present invention is by starting a hook procedure; With the completion signal that produces in the interception power-off program; When accomplishing signal and tackled, promptly trigger an interruption, confirm that to utilize interrupt handling routine to handle above-mentioned interruption first node and Section Point all accomplish the power-off program.After confirming completion, just carry out the power-off action of power supply unit.Thus, first node and Section Point can carry out power-off synchronously, and two nodes are nonsynchronous to carry out power-off to avoid, and cause the situation of data loss and access errors to take place.
Description of drawings
For let above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention, wherein:
Fig. 1 illustrates the calcspar into the server system of one embodiment of the invention.
Fig. 2 illustrates the process flow diagram into the power-off disposal route of one embodiment of the invention.
The main element symbol description:
100: server system
110: power supply unit
120,130: node
121,131: CPU
122,132: north bridge chips
123,133: South Bridge chip
140: baseboard management controller
GPIA, GPIB: input port
GPOA, GPOB: output port
S202～S218: each step of the power-off disposal route of one embodiment of the invention
Embodiment
Fig. 1 illustrates the calcspar into the server system of one embodiment of the invention.Please with reference to Fig. 1, server system 100 comprises power supply unit 110, node 120 and 130 and baseboard management controller 140.Power supply unit 110 is in order to provide a power supply.Node 120 and 130 is coupled to each other, and common source supply 110.In the present embodiment, node 120 and 130 can be respectively an independently computer system.
Node 120 comprises CPU (central processing unit; CPU) 121, north bridge chips (north bridge) 122 and South Bridge chip (south bridge) 123; And the relation of coupling of CPU 121, north bridge chips 122 and South Bridge chip 123 is as shown in Figure 1, so repeat no more.Node 130 comprises CPU 131, north bridge chips 132 and South Bridge chip 133, and the relation of coupling of CPU 131, north bridge chips 132 and South Bridge chip 133 is as shown in Figure 1, so repeat no more.Wherein, The South Bridge chip 123 of node 120 couples the South Bridge chip 133 of node 130; And the input port GPIA of South Bridge chip 123 couples the output port GPOB of South Bridge chip 133, and the output port GPOA of South Bridge chip 123 couples the input port GPIB of South Bridge chip 133.
Baseboard management controller (baseboard management controller; BMC) 140 couple node 120 and 130 (that is South Bridge chip 123 and 133); In order to push the state of a power switch (not illustrating) according to the user; Give node 120 and 130 and produce the power-off signal, carrying out the power-off handling procedure, but and then the powered-down supply provide to the power supply of node 120 and 130.
More than, couple relation with it with rough explanation server system 100 included elements.Below, how explanation server system 100 is carried out power supply close the program of handling.
At first, for example during user's pushing power switch, baseboard management controller 130 can receive the message of above-mentioned pushing power switch, and produces the power-off signal according to this and give South Bridge chip 123 and 133.Then; South Bridge chip 123 and 133 can produce system control respectively and interrupt (system control interrupt; SCI) give operating system; To carry out the power-off program, for example carry out advanced configuration and power supply interface (advanced configuration and power interface, ACPI) in the standard defined S3, S4 or S5 program to its state.
In general; When operating system is accomplished the power-off program; Can produce one and accomplish signal, for example a preset value write to register (for example sleep type register), and the power-off program that South Bridge chip just can be learnt this node according to the preset value in the register (completion signal) is to accomplish; And produce a signalisation power supply unit with its power-off, to reach the effect of power-off.
But, in the present embodiment, when operating system is carried out in the process of power-off program; South Bridge chip 123 and 133 can start a hook procedure; So that the completion signal that interception power-off program produces when the completion signal is tackled, promptly produces one and interrupts giving CPU 121 and 131.
Then; CPU 121 can start interrupt handling routine and handle above-mentioned interruption; And the output port GPOA that controls South Bridge chips 123 through north bridge chips 122 produces for example first logical signal of high voltage potential " 1 "; Expression node 120 has been accomplished the power-off program; CPU 131 also can start interrupt handling routine and handles above-mentioned interruption in addition, and produces second logical signal of high logic voltage current potential " 1 " through the output port GPOB of north bridge chips 132 control South Bridge chips 133, and expression node 130 has been accomplished the power-off program.
Because the input port GPIA of South Bridge chip 123 couples the output port GPOB of South Bridge chip 133, so the input port GPIA of South Bridge chip 123 can receive second logical signal of high voltage potential " 1 ".So; When the output port GPOA that receives second logical signal and the South Bridge chip 123 of high voltage potential " 1 " when the input port of South Bridge chip 123 produced first logical signal of high voltage potential " 1 ", expression node 120 had confirmed that egress 120 and 130 all accomplishes the power-off ordering.
On the other hand, because the input port GPIB of South Bridge chip 133 couples the output port GPOA of South Bridge chip 123, so the input port GPIB of South Bridge chip 133 can receive first logical signal of high voltage potential " 1 ".So; When the output port GPOB that receives first logical signal and the South Bridge chip 133 of high voltage potential " 1 " when the input port of South Bridge chip 133 produced second logical signal of high voltage potential " 1 ", expression node 130 had confirmed that egress 120 and 130 all accomplishes the power-off ordering.
Then, node 120 and 130 can be closed hook procedure respectively, and recovers to produce the completion signal.Then, South Bridge chip 123 and 133 can will accomplish signal respectively be sent to power supply unit 110, the power supply that provides with the powered-down supply.Thus; The node 120 of present embodiment and 130 can carry out power-off synchronously; And can occurrence node 120 do not accomplish the power-off programs and node 130 does not accomplish as yet that power-off program or node 130 are accomplished the power-off programs and node 120 when not accomplishing the power-off program as yet; The power supply of power supply unit is but closed, and causes node 120 or node 130 that the situation of data loss and access errors takes place.
In the present embodiment, above-mentioned interruption can be that (system management interrupt, SMI), and above-mentioned interrupt handling routine can be system management interrupt handling procedure (SMI handler) to system management interrupt.In addition, above-mentioned South Bridge chip 123 and 133 input port and output port be universal input and output port (general purpose input/output, GPIO).Above-mentioned first logical signal and second logical signal all are high voltage potential " 1 "; All to have accomplished the foundation of power-off program as detecting node 120 and 130; But present embodiment is not limited thereto; Also can first logical signal and second logical signal be replaced by low voltage potential " 0 ", all accomplish the power-off program in regular turn to detect node 120 and 130 as decision node.
By the explanation of the above embodiments, can summarize a kind of process flow diagram of power-off disposal route.Fig. 2 illustrates the process flow diagram into the power-off disposal route of one embodiment of the invention.The power-off disposal route of present embodiment is suitable for server system shown in Figure 1 100.Please with reference to Fig. 2, in step S202, baseboard management controller produces the power-off signal.Then, according to the power-off signal, first node (the for example node 120 of Fig. 1) is carried out the following step S204～S210 and step S212～216 respectively with Section Point (the for example node 130 of Fig. 1).
In step S204, according to the power-off signal, first node is carried out the power-off program.Then, in step S206, start hook procedure,, and trigger an interruption with the completion signal that produces in the interception power-off program.Afterwards, in step S208, interrupt handling routine is handled above-mentioned interruption, whether accomplishes the power-off program to detect first node and Section Point.Then, in step S210, when first node and Section Point have been accomplished the power-off program, close hook procedure, and recover the completion signal that produces in the power-off program, and send power supply unit to, with the power supply of powered-down supply.
In addition, the step of whether accomplishing the power-off program at detection first node and the Section Point of above-mentioned steps S208 also comprises: whether the input port whether output port of detection first node produces first logical signal and first node receives second logical signal.
On the other hand, in step S212, according to the power-off signal, Section Point is carried out the power-off program.Then, in step S214, start hook procedure,, and trigger an interruption with the completion signal that produces in the interception power-off program.Afterwards, in step S216, interrupt handling routine is handled above-mentioned interruption, all accomplishes the power-off program to confirm first node and Section Point.Then, in step S218, when first node and Section Point have been accomplished the power-off program, close hook procedure, and recover the completion signal that produces in the power-off program, and send power supply unit to, with the power supply of powered-down supply.
In addition, the step of whether accomplishing the power-off program at detection first node and the Section Point of above-mentioned steps S216 also comprises: whether the input port whether output port of detection Section Point produces second logical signal and Section Point receives first logical signal.
Thus, the first node of present embodiment and Section Point can carry out the action of power-off synchronously, produce nonsynchronous power-off action to avoid two nodes, and cause the situation of data loss and access errors to take place.
In sum; The present invention is by starting a hook procedure, with the completion signal that produces in the interception power-off program, when the completion signal is tackled; Promptly trigger an interruption, confirm that to utilize interrupt handling routine to handle above-mentioned interruption first node and Section Point all accomplish the power-off program.After confirming completion, just carry out the power-off action of power supply unit.Thus, first node and Section Point can carry out power-off synchronously, and two nodes are nonsynchronous to carry out power-off to avoid, and cause the situation of data loss and access errors to take place.
Though the present invention discloses as above with preferred embodiment; Right its is not that any those skilled in the art are not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little modification and perfect, so protection scope of the present invention is when being as the criterion with what claims defined.
Claims (8)
1. power-off disposal route; Be suitable for a server system; This server system has a first node, a Section Point and a power supply unit, and this first node and shared this power supply unit of this Section Point, and this power-off disposal route comprises:
According to a power-off signal, this first node and this Section Point are carried out the following step respectively:
Carry out a power-off program;
Start a hook procedure, with tackle produce in this power-off program one accomplish signal, and trigger one first and interrupt;
Handle this first interruption by an interrupt handling routine, whether accomplish this power-off program to detect this first node and this Section Point; And
Accomplished this power-off program when this first node and this Section Point, then closed this hook procedure, and recovered this completion signal of producing in this power-off program, and be sent to this power supply unit, to close a power supply of this power supply unit.
2. power-off disposal route as claimed in claim 1; It is characterized in that; One input port of this first node couples an output port of this Section Point; And an output port of this first node couples an input port of this Section Point, whether accomplishes the step of this power-off program and comprises and detect this first node and this Section Point:
In the detection step of this first node, whether the input port whether output port that detects this first node produces one first logical signal and this first node receives one second logical signal; And
In the detection step of this Section Point, whether the input port whether output port that detects this Section Point produces this second logical signal and this Section Point receives this first logical signal.
3. power-off disposal route as claimed in claim 1 is characterized in that, the step of this completion signal that recovers to produce in this power-off program comprises:
One preset value is write a register.
4. power-off disposal route as claimed in claim 1 is characterized in that, this first interruption is a system management interrupt, and this interrupt handling routine is a system management interrupt handling procedure.
5. power-off disposal route as claimed in claim 1 is characterized in that, more comprises:
Produce this power-off signal by a baseboard management controller.
6. power-off disposal route as claimed in claim 1 is characterized in that, comprises in the step of carrying out a power-off program:
According to one second interruption, carry out this power-off program by an operating system.
7. power-off disposal route as claimed in claim 6 is characterized in that, this second interruption is that system control is interrupted.
8. power-off disposal route as claimed in claim 1 is characterized in that, this first node and this Section Point comprise respectively:
One CPU;
One north bridge chips couples this CPU; And
One South Bridge chip couples this north bridge chips,
Wherein, this South Bridge chip of this first node couples this South Bridge chip of this Section Point, and an input port of this South Bridge chip of this first node and an output port couple an output port and an input port of this South Bridge chip of this Section Point respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105542412A CN102467218A (en) | 2010-11-11 | 2010-11-11 | Method for turning off power |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105542412A CN102467218A (en) | 2010-11-11 | 2010-11-11 | Method for turning off power |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102467218A true CN102467218A (en) | 2012-05-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105542412A Pending CN102467218A (en) | 2010-11-11 | 2010-11-11 | Method for turning off power |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102750477A (en) * | 2012-06-11 | 2012-10-24 | 腾讯科技（深圳）有限公司 | Method and system for controlling closing of terminal |
| CN103645789A (en) * | 2013-11-27 | 2014-03-19 | 苏州贝克微电子有限公司 | Method for controlling power supply of integrated circuit to be switched off with software |
| CN108919933A (en) * | 2018-07-13 | 2018-11-30 | 浪潮电子信息产业股份有限公司 | Power supply control system and method of multi-node server |
| CN110895431A (en) * | 2018-09-13 | 2020-03-20 | 纬创资通股份有限公司 | Power control method of storage device and electronic system using the same |
-
2010
- 2010-11-11 CN CN2010105542412A patent/CN102467218A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102750477A (en) * | 2012-06-11 | 2012-10-24 | 腾讯科技（深圳）有限公司 | Method and system for controlling closing of terminal |
| WO2013185569A1 (en) * | 2012-06-11 | 2013-12-19 | 腾讯科技（深圳）有限公司 | Method and system for controlling switch-off of terminal, and computer storage medium |
| CN102750477B (en) * | 2012-06-11 | 2014-03-19 | 腾讯科技（深圳）有限公司 | Method and system for controlling closing of terminal |
| CN103645789A (en) * | 2013-11-27 | 2014-03-19 | 苏州贝克微电子有限公司 | Method for controlling power supply of integrated circuit to be switched off with software |
| CN108919933A (en) * | 2018-07-13 | 2018-11-30 | 浪潮电子信息产业股份有限公司 | Power supply control system and method of multi-node server |
| CN110895431A (en) * | 2018-09-13 | 2020-03-20 | 纬创资通股份有限公司 | Power control method of storage device and electronic system using the same |
| CN110895431B (en) * | 2018-09-13 | 2021-07-23 | 纬创资通股份有限公司 | Power control method of storage device and electronic system using the same |
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Application publication date: 20120523 |