CN102456408A - Multi-level cell NOR flash memory device - Google Patents
Multi-level cell NOR flash memory device Download PDFInfo
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- CN102456408A CN102456408A CN2010105266677A CN201010526667A CN102456408A CN 102456408 A CN102456408 A CN 102456408A CN 2010105266677 A CN2010105266677 A CN 2010105266677A CN 201010526667 A CN201010526667 A CN 201010526667A CN 102456408 A CN102456408 A CN 102456408A
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- flash memory
- memory device
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- type flash
- multilevel
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- 239000000758 substrate Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 230000026683 transduction Effects 0.000 abstract description 8
- 238000010361 transduction Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 16
- 238000002955 isolation Methods 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 239000004744 fabric Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052723 transition metal Inorganic materials 0.000 description 2
- 150000003624 transition metals Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
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- 229910052796 boron Inorganic materials 0.000 description 1
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- 238000012163 sequencing technique Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Abstract
The invention discloses a multi-level cell NOR flash memory device, comprising: the memory cell comprises a plurality of gate lines, a plurality of source regions and drain regions, a plurality of source lines, a plurality of bit lines and a plurality of power lines, wherein each bit line has a specific sheet resistance, and in addition, a specific number of bit lines are arranged between two adjacent power lines. Therefore, better transduction value and uniformity can be achieved, and the production yield is improved.
Description
Technical field
The invention relates to a kind of anti-or type flash memory device, more particularly about a kind of anti-or type flash memory device of multilevel-cell of promoting semiconducting behavior.
Background technology
Along with the user constantly strengthens down electronic product functions such as mobile phone, music player (MP3 Player), audio and video player, digital camera, e-book; The system data amount also increases day by day; And requiring to have stable and access speed at a high speed, therefore the manufacturer of flash memory constantly actively increases the density and the access speed of internal memory in the chip, so flash memory is gradually by single layer cell (Single Level Cell; SLC) turn to multilevel-cell (Multi Level Cell, MLC) development.Through the technology of MLC, can reach the flash memory component of multi-layered high-density, and bigger storage volume and storage speed is provided.
The NOR flash memory have at a high speed write and wipe ability, and full address and data interface are arranged, and can read at random; So the NOR flash memory not needing to be suitable for frequent renewal, for example: BIOS or firmware, it has 10; 000 to 1,000, the life-span of 000 erase cycle.The scope of NOR type flash memory application at present; Motherboard on personal computer can utilize the NOR type flash memory stores BIOS data; Mobile phone, portable electric device also can use NOR type flash memory to come the storage system data, through its reading speed at a high speed, satisfy the start demand of hand-held device.
Yet in the read-write process of flash memory, the phenomenon of the voltage decline of initial provision can take place in the generation of stray capacitance (Parasitic Capacitance).So, the reduction of whole uniformity coefficient can take place when critical voltage distribution memory cell, wherein this critical voltage is an important parameter of flash memory device, and the following general who has surrendered of whole uniformity coefficient causes the characteristic of device to reduce and reduce the production yield.
Summary of the invention
A purpose of the present invention is to propose a kind of have preferable transduction value (Transconductance, the anti-or type flash memory device of multilevel-cell GM).
Another object of the present invention is to provide a kind of multilevel-cell anti-or type flash memory device, each memory cell wherein (memory cell) has preferable homogeneity (uniformity).
For reaching above-mentioned purpose and other purpose; Anti-or the type flash memory device of multilevel-cell of the present invention comprises: many gate lines separate through a gate insulator and semiconductor substrate, with the grid usefulness as a plurality of memory cells; Wherein, each said gate line has a metal silicide layer; Plurality of source regions and drain region are formed in this semiconductor substrate and between said gate line, use with source electrode and drain electrode as said memory cell; Many source electrode lines are coupling part source areas, and wherein the sheet resistance of each said source electrode line is every square 100 to 300 nurse difficult to understand (ohm/sq); Multiple bit lines, it is vertical with said source electrode line, and each said bit line is to electrically connect through a plurality of drain contacts and said drain region; And many power leads, it is parallel with said bit line, and each said power lead is to electrically connect through multiple source polar contact and said source electrode line, wherein, has 16 bit lines between adjacent two power leads.
In an embodiment, this anti-or type flash memory device is through a soft sequencing program.
In an embodiment, this semiconductor substrate can be a silicon substrate.
In an embodiment, the metal of this metal silicide layer is selected from cobalt and titanium.
Through framework of the present invention; Anti-or the type flash memory device of multilevel-cell can obtain a higher transduction value; Preferable transduction value (that is, the transduction value is high more) is being represented under very little grid bias changes can drive higher drain current, therefore can reduce unnecessary stray capacitance and produce; Hereat; The present invention not only can make memory device on electrically, have preferable transduction value and homogeneity, and structure arrangement of the present invention has more promoted the production yield of the anti-or type flash memory device of multilevel-cell, and provides a kind of capacity of user big and have at a high speed and the multilevel-cell of high stability is anti-or the type flash memory device.
Description of drawings
Fig. 1 be according to the present invention in an embodiment part planar configuration skeleton view of the anti-or type flash memory device of multilevel-cell;
Fig. 2 A is along the cross section view of AA line segment among Fig. 1;
Fig. 2 B is along the cross section view of BB line segment among Fig. 1;
Fig. 2 C is along the cross section view of CC line segment among Fig. 1;
Fig. 3 be according to the present invention in an embodiment another planar configuration of the anti-or type flash memory device of multilevel-cell.
Drawing reference numeral:
101 semiconductor substrates
102 assembly isolation structures
103 assembly isolation trenches
110 gate insulators
120 bit lines
122 metals
123 drain electrode contact fenestras
124 impurity diffusion layers
126 impurity diffusion layers
128 metal silicide layers
130 interlayer dielectric
140 power leads
142 metals
The AA profile line
The BB profile line
The CC profile line
The D drain region
The DC drain contact
BL, BLs bit line
The G gate line
The MC memory cell
The S source area
The SL source electrode line
The SC source contact
Embodiment
For fully understanding the object of the invention, characteristic and effect, now through following concrete embodiment, and cooperate appended graphicly, the present invention is done a detailed description, explain as after:
At first see also Fig. 1, be according to the present invention in an embodiment part planar configuration skeleton view of the anti-or type flash memory device of multilevel-cell.Many gate lines G is extended toward column direction (left and right directions among the figure), and according to disposing a space to be used to hold source contact SC at a distance from going up at line direction (above-below direction among the figure) between required.In the diagram, assembly isolation structure 102 roughly is mutually perpendicular arrangement with said gate lines G.Between adjacent two gate lines G and 102 of adjacent two assembly isolation structures have a drain region D; More be formed with a drain contact DC on each drain region D; And electrically connect with a bit line 120 (perspective fashion with dotted line among the figure appears), this bit line 120 extends and electrically connects each drain contact DC with delegation toward line directions.Between adjacent two gate lines G and the source electrode line 128 (seeing also Fig. 2 B) that is formed on the source area S orthogonal with said bit line 120; And through aforesaid source contact SC and a power lead 140 (be Vss, the perspective fashion with dotted line among the figure appears) electric connection.One memory cell MC comprises grid structure (comprise control gate CG and floating gate FG, see also Fig. 2 A) and adjacent drain region D and source area S.
Then please consult Fig. 2 A, Fig. 2 B and Fig. 2 C simultaneously, be respectively among Fig. 1 cross section view along AA, BB and CC line segment.
In Fig. 2 A; Each gate lines G is included on the column direction control gate CG as the character line; And be formed at the floating gate FG of the control gate CG below of each memory cell MC relatively, wherein, this floating gate FG separates with semiconductor substrate 101 through a gate insulator 110; With the grid usefulness as a memory cell MC, this gate insulator 110 can be tunnel oxide insulation courses such as (tunnel oxide layer).In order to increase the operating speed of memory cell MC; One metal silicide layer 128 uses transition metal such as cobalt, titanium or other to belong to together on the surface that transition metal is formed at control gate CG and drain region D; In a preferred embodiment, the metal of this metal silicide layer 128 is selected from cobalt and titanium.Impurity diffusion layer 124 (S) and 126 (D) as source area S and drain region D arrange between gate lines G on line direction shown in Figure 1; And drain region D utilizes between 102 formation of said assembly isolation structure at a distance from forming the drain region D that discontinuous is arranged on column direction shown in Figure 1.On this gate lines G and this metal silicide layer 128, more be formed with an interlayer dielectric medium 130, and form a drain electrode contact fenestra 123 and be placed in one with the metal 122 (DC) that holds as drain contact DC.And be formed with the bit line 120 (BL) on line direction shown in Figure 1 again in the superiors.
Then see also Fig. 2 B, each metal 142 (SC) as source contact SC links with a power lead 140 (Vss), and this power lead 140 (Vss) electrically connects the source contact SC that is positioned at the colleague on line direction shown in Figure 1.Impurity diffusion layer 124 shown in Fig. 2 B strides across assembly isolation trenches 103 (by the assembly isolation structure 102 of etched portions) to form the source electrode line SL on the column direction as shown in Figure 1.In the present invention, the control of planting condition through cloth is that to make the sheet resistance of the source electrode line SL that this impurity diffusion layer 124 (SL) forms be every square 100 to 300 nurse difficult to understand (ohm/sq).
Then see also Fig. 2 C,, and on interlayer dielectric 130, become a circuit as metal 142 (SC) and a bit line 120 (BL) binding of drain contact DC.
Then see also Fig. 3, be according to the present invention in an embodiment another planar configuration of the anti-or type flash memory device of multilevel-cell.The present invention is limited with 16 bit lines 120 (BL) between adjacent two power leads 140 (Vss).Said power lead 140 (Vss) is parallel with said bit line 120 (BL), and each said power lead 140 (Vss) is to electrically connect (seeing also Fig. 2 B) through multiple source polar contact SC and source electrode line SL.
The manufacturing approach of the present invention in an embodiment is to comprise the following step:
(1) forms many bar assemblies isolation structure 102 in semiconductor substrate 101;
(2) form a gate insulator 110 on this semiconductor substrate 101 and said assembly isolation structure 102;
(3) form grid structure on this gate insulator 110 and through Patternized technique to form many gate lines G;
(4) the assembly isolation structure 102 of etched portions serves as that shielding is carried out cloth and planted technology in this semiconductor substrate 101 of said gate line both sides, to form plurality of source regions S and drain region D with said gate lines G;
(5) go up formation one metal silicide layer 128 in said drain region D and gate line G, this impurity diffusion layer 124 (SL) then is many source electrode line SL (seeing also Fig. 1), and wherein the sheet resistance of each said source electrode line is every square 100 to 300 nurse difficult to understand (ohm/sq);
(6) form interlayer dielectric 130, multiple source polar contact SC, a plurality of drain contact DC;
(7) form multiple bit lines 120 (BL) and power lead 140 (Vss), to accomplish the anti-or type flash memory device of the multilevel-cell that has 16 bit lines 120 (BL) between adjacent two power leads 140 (Vss); And
(8) carry out testing electrical property, and in a preferable enforcement state, in the test process of erase-write (erase-program), add a soft sequencing program again, that is:
(8-a) program of erasing;
(8-b) soft sequencing program is that the voltage that applies when being lower than the sequencing program is injected into storage unit;
(8-c) sequencing program.
So, under the specific resistance of specific bit line layout structure of the present invention and source electrode line, collocation has the test process of erasing-write of soft sequencing and more can promote uniformity coefficient and durability degree and then more can promote yield.
Aforesaid said assembly isolation structure 102 can be field oxide, shallow slot isolation structure, and (Shadow Trench Isolation STI) or the isolation structure of other tool insulation effect, is an example with shallow slot isolation structure (STI) in the present embodiment.In sum, the anti-or type flash memory device of multilevel-cell provided by the invention reaches a higher transduction value through structural special arrangement, thereby can reduce the generation of unnecessary stray capacitance.Hereat, the present invention not only can make memory device on electrically, have preferable transduction value and homogeneity, has more promoted the production yield.In addition, the adding of soft sequencing program more can improve aforesaid advantage again.Therefore, the present invention provides the anti-or type flash memory device of multilevel-cell that a kind of capacity of user is big and have high speed and high stability.
The present invention discloses with preferred embodiment hereinbefore, it will be understood by those skilled in the art that so this embodiment only is used to describe the present invention, and should not be read as restriction scope of the present invention.It should be noted,, all should be made as and be covered by in the category of the present invention such as with the variation and the displacement of this embodiment equivalence.Therefore, protection scope of the present invention is when being as the criterion with what claim defined.
Claims (4)
1. the anti-or type flash memory device of a multilevel-cell, it is through a soft sequencing program, it is characterized in that, the anti-or type flash memory device of said multilevel-cell comprises:
Many gate lines separate through a gate insulator and semiconductor substrate, and wherein, each said gate line has a metal silicide layer;
Plurality of source regions and drain region are formed in the said semiconductor substrate and between said gate line;
Many source electrode lines, the coupling part source area, wherein the sheet resistance of each said source electrode line is every square 100 to 300 nurse difficult to understand;
Multiple bit lines, vertical with said source electrode line, each said bit line electrically connects through a plurality of drain contacts and said drain region; And
Many power leads, parallel with said bit line, each said power lead electrically connects through multiple source polar contact and said source electrode line, wherein, has 16 bit lines between adjacent two power leads.
2. the anti-or type flash memory device of multilevel-cell as claimed in claim 1 is characterized in that, said anti-or type flash memory device is through a soft sequencing program.
3. the anti-or type flash memory device of multilevel-cell as claimed in claim 1 is characterized in that said semiconductor substrate is a silicon substrate.
4. the anti-or type flash memory device of multilevel-cell as claimed in claim 1 is characterized in that the metal of this metal silicide layer is selected from cobalt and titanium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105266677A CN102456408A (en) | 2010-10-29 | 2010-10-29 | Multi-level cell NOR flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105266677A CN102456408A (en) | 2010-10-29 | 2010-10-29 | Multi-level cell NOR flash memory device |
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| Publication Number | Publication Date |
|---|---|
| CN102456408A true CN102456408A (en) | 2012-05-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010105266677A Pending CN102456408A (en) | 2010-10-29 | 2010-10-29 | Multi-level cell NOR flash memory device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828602A (en) * | 1992-11-02 | 1998-10-27 | Wong; Chun Chiu Daniel | Memory system having multiple programmable reference cells |
| US20090121275A1 (en) * | 2007-11-08 | 2009-05-14 | Samsung Electronics Co., Ltd. | Non-Volatile Memory Devices Including Blocking and Interface Patterns Between Charge Storage Patterns and Control Electrodes and Related Methods |
-
2010
- 2010-10-29 CN CN2010105266677A patent/CN102456408A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828602A (en) * | 1992-11-02 | 1998-10-27 | Wong; Chun Chiu Daniel | Memory system having multiple programmable reference cells |
| US20090121275A1 (en) * | 2007-11-08 | 2009-05-14 | Samsung Electronics Co., Ltd. | Non-Volatile Memory Devices Including Blocking and Interface Patterns Between Charge Storage Patterns and Control Electrodes and Related Methods |
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Application publication date: 20120516 |