CN102446971A - PMOS (P-channel metal oxide semiconductor) structure for improving transistor carrier mobility - Google Patents
PMOS (P-channel metal oxide semiconductor) structure for improving transistor carrier mobility Download PDFInfo
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- CN102446971A CN102446971A CN2011102652595A CN201110265259A CN102446971A CN 102446971 A CN102446971 A CN 102446971A CN 2011102652595 A CN2011102652595 A CN 2011102652595A CN 201110265259 A CN201110265259 A CN 201110265259A CN 102446971 A CN102446971 A CN 102446971A
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Abstract
The invention discloses a PMOS (P-channel metal oxide semiconductor) device for improving transistor carrier mobility, wherein the PMOS device comprises substrates with a plurality of paired active regions, grids, shallow groove insulation regions and a plurality of through holes, wherein a channel is formed between each pair of active regions; the grids are positioned above the channels; two sides of the periphery of each pairing active region are respectively provided with a shallow groove insulation region, and the distance from the shallow groove insulation regions to the channels is a first width; the bottom ends of the plurality of through holes are contact with the active regions, and the other ends of the plurality of through holes are vertically upward; a first interval is positioned between two adjacent through holes at the same side of each grid, and the first space meets the fact that an extending section of the shallow groove insulation region is formed between two adjacent through holes; the active region between two bottom ends of two adjacent through holes is provided with a second width, wherein the second width is the distance from the extending section of each shallow groove insulation region to each channel, and the second width is less than the first width; and the thermal expansion coefficient of each shallow groove insulation region is less than that of the material of each active region.
Description
Technical field
The present invention relates to semiconductor device structure, belong to integrated circuit fields, relate in particular to a kind of PMOS structure that improves transistor carrier mobility.
Background technology
Along with the development of semiconductor related manufacturing process and the IC chip trend of dimension shrinks proportionally; Stress engineering role aspect semiconductor technology and performance of semiconductor device is more and more obvious, and the stress engineering suit is on the semiconductor device that improves transistor carrier mobility.At present, just there are some to be applied on some special chip types, like complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal-Oxide-Semiconductor) device.
Usually, in complicated preparation technology's flow process of cmos device, have various stress, because progressively the dwindling of device size, and the stress of finally staying in the device channel has bigger influence to the performance of device.A lot of stress have improvement to the performance of device, and different types of stress has different influence to the charge carrier in the device (being electronics and hole) mobility.
Fig. 1 is the plan structure figure of mos field effect transistor of a P type of prior art.The material of transistor formed 100 grids 101 is generally gate polysilicon; Be formed into right active area 120 on the substrate 999 of grid 101 both sides (with reference to figure 2); Active area 120 both sides are shallow channel isolation area 200; The raceway groove 104 (with reference to figure 2) of not shown grid 101 vertical belows among Fig. 1, the distance of shallow channel isolation area 200 to raceway groove 104 is the first width a.Among Fig. 1, the length of the first width a equals diameter length and the distance c between through hole 300 and the raceway groove and the summation of the distance b between through hole 300 and the shallow channel isolation area 200 of through hole 300.
Are structural representations of the mos field effect transistor 100 of a P type again with reference to figure 2; Be provided with side wall separator 106 around the grid 101; Gate oxide layers 105 is isolated grid 101 and raceway groove 104 insulation; If apply the pressure stress F along channel direction at raceway groove 104, then the hole mobility of PMOS device 100 increases, and this result is that we are desired.
Therefore; Whole generation preparation of devices is kept under the prerequisite of uncomplicatedization; Utilize stress engineering to improve the performance of semiconductor device; A kind of compression of utilizing on stress factors applies the PMOS device with increase the channel direction especially is provided, and the device architecture and the process that improve the hole mobility in the PMOS device just seem particularly important.
Summary of the invention
The objective of the invention is to improve transistor carrier mobility through the structure that designs a kind of active area.
The present invention discloses a kind of PMOS device that improves transistor carrier mobility, comprising:
Substrate with some paired active areas, each is to being formed with raceway groove between the active area;
Grid is positioned at said raceway groove top;
The both sides of the periphery of said paired active area are respectively arranged with shallow channel isolation area, and the distance of said shallow channel isolation area to said raceway groove is first width;
Some through holes, its bottom contacts said active area, and the other end is straight up;
Wherein, between two adjacent through-holes of said grid the same side, have first spacing, said first spacing satisfies the extension that between said two adjacent through-holes, forms shallow channel isolation area;
Active area between the two adjacent through-holes bottoms has second width, the distance of the extension that said second width is said shallow channel isolation area to said raceway groove, and said second width is less than said first width;
The material coefficient of thermal expansion coefficient of said shallow channel isolation area is less than the material coefficient of thermal expansion coefficient of said active area.
Above-mentioned device, wherein, said paired active area comprises source electrode and drain electrode.
Above-mentioned device, wherein, said active area comprises silicon.
Above-mentioned device, wherein, said shallow channel isolation area comprises silicon dioxide.
The present invention makes shallow channel isolation area improve greatly the compression effect that raceway groove applies through dwindling the distance between part shallow channel isolation area and the raceway groove, thereby plays the effect of the transistor carrier mobility that improves the PMOS device.Device of the present invention has simple in structure, the advantage that adapts with traditional handicraft.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, the part parts have been amplified.
Fig. 1 shows in the prior art, the plan structure figure of the mos field effect transistor of a P type;
Fig. 2 shows in the prior art, the structural representation of the mos field effect transistor of a P type; And
Fig. 3 shows according to of the present invention, a kind of PMOS structure that improves transistor carrier mobility.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further elaborated.Embodiment described herein only is used to explain the present invention, and is not used in qualification protection scope of the present invention.
With reference to shown in Figure 3 according to of the present invention, a kind of PMOS structure that improves transistor carrier mobility.A kind of PMOS device that improves transistor carrier mobility comprises:
The both sides of the periphery of said paired active area 120 are respectively arranged with shallow channel isolation area 200 (not indicating among Fig. 3, with reference to figure 1), and the distance of said shallow channel isolation area 200 to said raceway groove 104 is the first width a;
Some through holes 300, its bottom contact said active area 120, and the other end straight up;
Between two adjacent through-holes of said grid the same side, has the first spacing e; The said first spacing e satisfies the extension 210 that between said two adjacent through-holes 300, forms shallow channel isolation area 200; The part of active area 120 as shown in Figure 3 is respectively arranged with the extension 210 of a shallow channel isolation area 200 between three through holes 300 of each side of grid 101.
Among Fig. 3, the extension 210 of channel separating zone 200 is parts of channel separating zone 200, and the material of extension 210 is identical with the material of channel separating zone 200.
Visible from Fig. 3; Because the second width d is littler than the first width a; Compare prior art; Reduced distances between shallow channel isolation area 200 of the present invention and the raceway groove 104 has increased shallow channel isolation area 200 and has acted on the compression in the device channel 104, thereby has improved the hole mobility of PMOS device.Comparing prior art, mainly is through two are strengthened with the spacing between the side through hole 300, makes shallow channel isolation area 200 extend a segment length between with side through hole 300 to two, thereby has formed second width.
Further, in conjunction with reference to figure 2, said paired active area 120 comprises source electrode 102 and drain electrode 103.
In a specific embodiment, said active area comprises that (thermal coefficient of expansion is about 2.5 * 10-6/K) to silicon.
More particularly, said shallow channel isolation area comprises that (thermal coefficient of expansion is about 0.5 * 10-6/K) to silicon dioxide.
The present invention makes shallow channel isolation area improve greatly the compression effect that raceway groove applies through dwindling the distance between part shallow channel isolation area and the raceway groove, thereby plays the effect of the transistor carrier mobility that improves the PMOS device.Device of the present invention has simple in structure, the advantage that adapts with traditional handicraft.
Those skilled in the art combine prior art and the foregoing description can realize said variant, and such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (4)
1. PMOS device that improves transistor carrier mobility comprises:
Substrate with some paired active areas, each is to being formed with raceway groove between the active area;
Grid is positioned at said raceway groove top;
The both sides of the periphery of said paired active area are respectively arranged with shallow channel isolation area, and the distance of said shallow channel isolation area to said raceway groove is first width;
Some through holes, its bottom contacts said active area, and the other end is straight up;
It is characterized in that between two adjacent through-holes of said grid the same side, having first spacing, said first spacing satisfies the extension that between said two adjacent through-holes, forms shallow channel isolation area;
Active area between the two adjacent through-holes bottoms has second width, the distance of the extension that said second width is said shallow channel isolation area to said raceway groove, and said second width is less than said first width;
The material coefficient of thermal expansion coefficient of said shallow channel isolation area is less than the material coefficient of thermal expansion coefficient of said active area.
2. device according to claim 1 is characterized in that, said paired active area comprises source electrode and drain electrode.
3. device according to claim 1 and 2 is characterized in that said active area comprises silicon.
4. device according to claim 1 and 2 is characterized in that said shallow channel isolation area comprises silicon dioxide.
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| CN2011102652595A CN102446971A (en) | 2011-09-08 | 2011-09-08 | PMOS (P-channel metal oxide semiconductor) structure for improving transistor carrier mobility |
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| CN2011102652595A CN102446971A (en) | 2011-09-08 | 2011-09-08 | PMOS (P-channel metal oxide semiconductor) structure for improving transistor carrier mobility |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256426A (en) * | 2017-07-12 | 2019-01-22 | 恩智浦有限公司 | Semiconductor switching device and method |
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| US20040256674A1 (en) * | 2003-06-20 | 2004-12-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20060027876A1 (en) * | 2004-08-03 | 2006-02-09 | Samsung Electronics Co., Ltd. | CMOS device with improved performance and method of fabricating the same |
| US20070284582A1 (en) * | 2006-06-08 | 2007-12-13 | Shinichi Saito | Semiconductor device and manufacturing method of the same |
| CN101124668A (en) * | 2004-10-29 | 2008-02-13 | 飞思卡尔半导体公司 | Transistor structure with dual trench for optimized stress effect and method therefor |
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2011
- 2011-09-08 CN CN2011102652595A patent/CN102446971A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256674A1 (en) * | 2003-06-20 | 2004-12-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20060027876A1 (en) * | 2004-08-03 | 2006-02-09 | Samsung Electronics Co., Ltd. | CMOS device with improved performance and method of fabricating the same |
| CN101124668A (en) * | 2004-10-29 | 2008-02-13 | 飞思卡尔半导体公司 | Transistor structure with dual trench for optimized stress effect and method therefor |
| US20070284582A1 (en) * | 2006-06-08 | 2007-12-13 | Shinichi Saito | Semiconductor device and manufacturing method of the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256426A (en) * | 2017-07-12 | 2019-01-22 | 恩智浦有限公司 | Semiconductor switching device and method |
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Application publication date: 20120509 |