CN102446813A - Production method of interconnecting structure - Google Patents
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- CN102446813A CN102446813A CN2010105089494A CN201010508949A CN102446813A CN 102446813 A CN102446813 A CN 102446813A CN 2010105089494 A CN2010105089494 A CN 2010105089494A CN 201010508949 A CN201010508949 A CN 201010508949A CN 102446813 A CN102446813 A CN 102446813A
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Abstract
The invention provides a production method of an interconnecting structure, which comprises the following steps that: a semiconductor substrate is provided, and a low-K dielectric layer is formed on the semiconductor substrate; a hard mask layer is formed on the low-K dielectric layer; the low-K dielectric layer and the hard mask layer are annealed; and an interconnecting structure is formed inside the substrate and the low-K dielectric layer after being annealed by adopting the hard mask layer as a mask. Due to the adoption of the method, the resistance of the interconnecting structure can be reduced, and the remote control (RC) time constant of a device can be reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the manufacture method of interconnection structure.
Background technology
Along with the continuous development of semiconductor technology, size of semiconductor device is more and more littler, and the RC late effect of interconnection structure is increasing to the opening speed influence of device.In order to reduce the RC late effect, prior art replaces the big aluminium of resistivity with the little copper of resistivity, to reduce the resistance of metal interconnecting wires; And, utilize dielectric materials (the K value is less than silica) to replace traditional silica (its K value is 3.9), to reduce the capacitor C between metal interconnecting wires.Because metallic copper is difficult to etching, prior art utilizes dual-damascene technics to make copper interconnection structure.
With reference to figure 1～Fig. 3, be the copper interconnection structure manufacture method cross-sectional view of prior art.
At first, please refer to Fig. 1, Semiconductor substrate 10 is provided.On said Semiconductor substrate 10, form etching barrier layer 20, low-K dielectric layer 30, hard mask layer 40, photoresist layer 50 successively.Wherein, the material of said etching barrier layer 20 is a silicon nitride; The material of said low-K dielectric layer 30 is NCC diamond (Black Diamond, its K value is 2.5); The material of said hard mask layer 40 is a metal, for example is titanium nitride, the method (PVD) that its formation method is a physical vapour deposition (PVD); Has opening in the said photoresist layer 50, exposed portions serve hard mask layer 40.
Then; Please refer to Fig. 2, carry out etching technics, said hard mask layer 40 and low-K dielectric layer 30 and etching barrier layer 20 are carried out etching; In said etching barrier layer 20 and part low-K dielectric layer 30, form contact hole 70; In said part low-K dielectric layer 30 and hard mask layer 40, form groove 80, said groove 80 is overlapped with said contact hole 70, so that behind follow-up filling metal, can form interconnection structure.
Then, remove hard mask layer 40 and the photoresist layer 50 that is positioned at low-K dielectric layer 30 top.
Then, please refer to Fig. 3, in said contact hole 70 and groove 80, fill copper, and carry out flatening process.Make to be full of the copper metal in the said contact hole 70, form contact plunger, be used for lower electrode is drawn; Be full of the copper metal in the said groove 80, form metal interconnecting wires, be used for a same metal level electrical connection or a layer electrode rewiring together.Said contact plunger and metal interconnecting wires constitute dual damascene interconnect structure 90.
, publication number can find more information in being the one Chinese patent application of CN101325172 about prior art.
In reality, utilize the switching speed of the device that said method forms slow, can't satisfy demands of applications.
Summary of the invention
The problem that the present invention solves has provided a kind of manufacture method of interconnection structure, and said method has improved the switching speed of device, has satisfied demands of applications.For addressing the above problem, the present invention provides a kind of manufacture method of interconnection structure, comprising:
Semiconductor substrate is provided, is formed with the low-K dielectric layer on the said Semiconductor substrate;
On said low-K dielectric layer, form hard mask layer;
Said low-K dielectric layer and said hard mask layer are annealed;
With said hard mask layer is mask, forms interconnection structure in substrate after annealing and the low-K dielectric layer.
Alternatively, the material of said hard mask layer is metal or metallic compound.
Alternatively, said hard mask layer utilizes physical gas-phase deposition to make.
Alternatively, before forming said hard mask layer, also be included in the step that forms the cap layer on the said low-K dielectric layer.
Alternatively, saidly be annealed into boiler tube annealing or RTP annealing.
Alternatively, said annealing is carried out within 1 minute～10 hours after forming hard mask layer.
Alternatively, the time of said annealing is 10～1000 seconds.
Alternatively, the pressure of said annealing is 1～760 holder.
Alternatively, the gas of said annealing is one or more in argon gas, helium, the nitrogen, and the gas flow scope of said annealing is 5～1000sccm.
Alternatively, the temperature range of said annealing is 300～500 degrees centigrade.
Alternatively, said interconnection structure is a dual-damascene structure.。
Compared with prior art, the present invention has the following advantages:
The present invention anneals to said low-K dielectric layer and said hard mask layer; Eliminated hard mask layer and put on the stress on the low-K dielectric layer, avoided said stress to push said low-K dielectric layer, eliminated said low-K dielectric layer because the problem that the stress extruding deforms; Thereby the size of interconnection structure that guarantees follow-up formation is even; Reduce the resistance of interconnection structure, thereby improved the switching speed of device, satisfied demands of applications.
Description of drawings
Fig. 1～Fig. 3 is the manufacture method cross-sectional view of the interconnection structure of prior art.
Fig. 4 is the interconnection structure schematic top plan view that prior art forms.
Fig. 5 is an interconnection structure manufacture method schematic flow sheet of the present invention.
Fig. 6～Fig. 9 is the interconnection structure manufacture method cross-sectional view of one embodiment of the invention.
Figure 10 is the interconnection structure schematic top plan view that method of the present invention forms.
Embodiment
The switching speed of the device that existing method is made is slower, can't satisfy technological requirement.Discovering through the inventor, cause the slow-footed reason of devices switch to be because the RC time constant of device is big, is because the interconnection line and the contact hole of interconnection structure wave (wiggling) and cause the big reason of RC time constant.The size of the said contact plunger that waves the interconnection line that shows as interconnection structure usually and/or interconnection line below is inhomogeneous.As shown in Figure 4, the plan structure sketch map of the dual damascene interconnect structure of making for existing method.The size of the interconnection structure 90 on the Semiconductor substrate 10 is inhomogeneous, and said interconnection structure 90 is bending.Only show the interconnection line of interconnection structure 90 among the figure, the contact plunger that is positioned at the interconnection line below is not shown.
Because the size of interconnection line and contact plunger is inhomogeneous, has increased the resistance of interconnection structure, thereby has increased the RC time constant of device, has reduced the reaction speed of device, finally influences the performance of device.
The inventor further discovers; Said interconnection line and the uneven reason of contact plunger size are owing to exist due to the bigger stress between the low-K dielectric layer of hard mask layer and below; Because low-K dielectric is softer; Deformed easily by said stress, thereby make the in uneven thickness of said low-K dielectric layer.When subsequent etching technology; The contact hole that forms in the low-K dielectric layer and the size of groove are inhomogeneous; Thereby make that the last interconnection line and the contact plunger size that form behind the metal level of filling is inhomogeneous; Finally increase the resistance of interconnection structure, thereby increased the RC time constant of device, influenced the switching speed of device.
Accordingly, the present invention provides a kind of manufacture method of interconnection structure, please refer to Fig. 5, comprising:
Step S1 provides Semiconductor substrate, is formed with the low-K dielectric layer on the said Semiconductor substrate;
Step S2 forms hard mask layer on said low-K dielectric layer;
Step S3 anneals to said low-K dielectric layer and said hard mask layer;
Step S4 is a mask with said hard mask layer, forms interconnection structure in substrate after annealing and the low-K dielectric layer.
To combine concrete embodiment that technical scheme of the present invention is carried out detailed description below.
Please refer to Fig. 6～Fig. 9, be the interconnection structure manufacture method cross-sectional view of one embodiment of the invention.
With reference to figure 6, Semiconductor substrate 100 is provided, be formed with etching barrier layer 200, low-K dielectric layer 300, cap layer 400 on the said Semiconductor substrate 100 successively.
Particularly, the material of said Semiconductor substrate 100 can be silicon, silicon-on-insulator etc.
Said etching barrier layer 200 is used to protect Semiconductor substrate 200 surfaces, avoids said Semiconductor substrate 200 in etching technics, to sustain damage.In the present embodiment, the material of said etching barrier layer 200 is silicon nitride or silicon oxynitride.
In the present embodiment, said low-K dielectric layer 300 is formed on the said etching barrier layer 200.In other embodiment, said low-K dielectric layer 300 can directly be formed on the Semiconductor substrate 200.
The common K value of the K value of said low-K dielectric layer 300 less than silica.In the present embodiment, the K value of said low-K dielectric layer is less than 2.5, and its material can be NCC diamond (Black Diamond).
As preferred embodiment, also be formed with cap layer 400 on the said low-K dielectric layer 300, said cap layer 400 is used to reduce the stress between the hard mask layer of low-K dielectric layer 300 and follow-up formation, reduces the diastrophic degree of low-K dielectric layer 300.
Then, with reference to figure 7, on said cap layer 400, form hard mask layer 500.The material of said hard mask layer 500 is metal or metallic compound (for example nitride, metal silicide etc.).In the present embodiment, the material of said hard mask layer 500 is a titanium nitride.In other embodiment, the material of said hard mask layer 500 can also be tungsten silicide, titanium silicide etc.
The manufacture method of said hard mask layer 500 is a deposition process, and said deposition process can be the method for physical vapour deposition (PVD) or chemical vapour deposition (CVD).In the present embodiment, the manufacture method of said hard mask layer 500 is the method for physical vapour deposition (PVD).Said hard mask layer 500 thickness ranges are 50～5000 dusts.
Though be provided with cap layer 400 between said hard mask layer 500 and the low-K dielectric layer 300; But still can't effectively reduce hard mask layer 500 and put on the stress on the low-K dielectric layer 300; The softer low-K dielectric layer 300 of material of said stress extruding below possibly cause 300 flexural deformation of low-K dielectric layer.Particularly, said stress comprises and is present in inner stress of hard mask layer 500 and the stress between hard mask layer 500 and the cap layer 400.
The inventor finds, cause the former of said stress because: because physical gas-phase deposition utilizes evaporation, sputter etc. from source material or negative electrode (target) the form generation metal vapors with metal ion, electronics and neutral particle usually.Wherein, said metal ion in semiconductor substrate surface, and becomes metal grain in said semiconductor substrate surface crystallization in the effect deposit of electric field force.A large amount of metal grains is piled up in the surface of Semiconductor substrate, promptly forms hard mask layer 500.Because the restriction of physical gas-phase deposition itself; Thereby the size of the metal grain of said hard mask layer 500 inside there are differences; Said difference makes hard mask layer 500 inside have stress, and makes and have stress between the cap layer 400 of hard mask layer 500 and below.
In order to eliminate said stress, the inventor proposes post-depositional hard mask layer 500 annealing.Said annealing makes the crystal grain in the said hard mask layer 500 get rid of again, eliminates the stress of intergranule, thereby eliminates the stress between hard mask layer 500 and the cap layer 400, reduces the extruding to low-K dielectric layer 300, alleviates the flexural deformation of low-K dielectric layer 300.
Though have the step of heating in the process that physical gas-phase deposition carries out; But the time of said heating is not enough; Can't eliminate the stress between hard mask layer and the Semiconductor substrate; Need utilize extra heating process that the hard mask layer 500 that forms is annealed, with the stress of elimination hard mask layer 500 inside and the stress between hard mask layer 500 and the cap layer 400.
Particularly, said annealing can be boiler tube annealing or rapid thermal annealing.Because the time of rapid thermal anneal process is short, processing speed is fast, therefore, and preferred rapid thermal annealing.
As an embodiment, the technological parameter of said rapid thermal annealing is: annealing time is 10～1000 seconds, and said annealing time is long more, and the effect that eliminates stress is good more.But the time of annealing is long more, may influence the whole heat budget (thermal budget) of product.In reality, those skilled in the art can preferably be provided with according to specific circumstances.
As an embodiment, the pressure of said annealing is 1～760 holder, and the stress between the thickness of pressure during annealing and hard mask layer 500, hard mask layer 500 and the cap layer 400 has relation.The thickness of said hard mask layer 500 is big more, and the pressure of annealing chamber is big more during annealing; Stress between hard mask layer 500 and the cap layer 400 is big more, and the pressure of annealing chamber is big more during annealing.
The temperature range of said annealing is 300～500 degrees centigrade, and said annealing temperature is high more, and the effect that eliminates stress is good more; But temperature is too high, possibly influence the heat budget of product, therefore; In reality; Those skilled in the art can test according to the situation of technology, obtain and the corresponding optimum annealing temperature scope of product, do not do detailed explanation at this.
The gas of said annealing is nitrogen, inert gas or nitrogen and the mixing of inert gas.Inert gas can be argon gas, helium, xenon etc.Mixing of said nitrogen and inert gas can be mixing of nitrogen and a kind of inert gas or mixing of nitrogen and multiple inert gas.。
As an embodiment, the gas flow scope of said annealing is 5～1000sccm.
The inventor finds that also the effect of said stress relieving by annealing has relation with the time interval of the step of said annealing steps and formation hard mask layer 500.Particularly, annealing steps is short more with the time interval of the step that forms hard mask layer 500, and the effect of stress relieving by annealing is good more.For the effect that guarantees to anneal, annealing steps should carry out in 1 minute～10 hours after forming hard mask layer 500 usually.
For the effect of verifying that annealing reduces the stress that reduces between hard mask layer 500 and the cap layer 400; The inventor has carried out the stress intensity test between annealing front and back hard mask layer 500 and the cap layer 400; Find that the stress after the annealing reduces 60～80% than the preceding stress of annealing; Can reduce of the extruding of said stress so effectively, thereby reduce the deformation extent of said low-K dielectric layer 300 the low-K dielectric layer 300 of below.
Then, be mask with said hard mask layer 500, form interconnection structure in substrate after annealing and the low-K dielectric layer.In the present embodiment, said interconnection structure is a dual-damascene structure, and said dual-damascene structure comprises contact plunger that is formed in the contact hole and the interconnection line that is formed in the groove.In other embodiment, said interconnection structure also is merely and is formed at the contact plunger in the contact hole or is formed at the interconnection line in the groove.
Please refer to Fig. 8,, carry out etching technics, in said cap layer 400, part low-K dielectric layer 300, form groove 800, formation contact hole 700 in said cap layer 400, part low-K dielectric layer 300 and etching barrier layer 200 as an embodiment.Said groove 800 is overlapped with contact hole 700, so that can form interconnection structure after filling metal level in both.Because the stress that low-K dielectric layer 300 receives reduces before the annealing relatively, thereby the distortion of low-K dielectric layer 300 reduces, make that the size of said groove 800 and contact hole 700 is more even.
The concrete steps that form groove 800 and contact hole 700 are technology as well known to those skilled in the art, do not do detailed explanation at this.
Then,, remove the hard mask layer 500 of said cap layer 400 and cap layer 400 top, expose low-K dielectric layer 300 with reference to figure 9.Then, plated metal in said groove 800 and contact hole 700 forms the metal level that covers said low-K dielectric layer 300, and said metal level is filled full said groove 800 and contact hole 700.The formation method of said metal level can be methods such as physical vapour deposition (PVD), chemical vapour deposition (CVD), plating.The material of said metal is a copper.At last, carry out flatening process, remove the unnecessary copper that is positioned at low-K dielectric layer 300 top, make that being positioned at contact hole 700 constitutes interconnection structure 900 with the metal that is positioned at groove 800.
With reference to Figure 10, be the interconnection structure schematic top plan view of method formation of the present invention.Because after forming hard mask layer; Utilize annealing steps that said hard mask layer is annealed; Eliminated the stress between hard mask layer and the cap layer, thereby reduced the squeezing action of said stress, eliminated the low-K dielectric layer because deformation takes place in extruding to the low-K dielectric layer.The groove and the contact hole that form when making subsequent etching are more even; The final interconnection line and the contact plunger that form behind the metal of filling is more even; Thereby reduced the resistance of metal interconnecting wires, when etching, the width of the groove that said interlayer dielectric layer 300 forms 800 (combination Fig. 9) is more even.Thereby the width of the metal interconnecting wires 900 that forms is even, has reduced the resistance of metal interconnecting wires, has reduced the RC time constant of device, has improved the performance of device, has satisfied demands of applications.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (11)
1. the manufacture method of an interconnection structure is characterized in that, comprising:
Semiconductor substrate is provided, is formed with the low-K dielectric layer on the said Semiconductor substrate;
On said low-K dielectric layer, form hard mask layer;
Said low-K dielectric layer and said hard mask layer are annealed;
With said hard mask layer is mask, forms interconnection structure in substrate after annealing and the low-K dielectric layer.
2. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, the material of said hard mask layer is metal or metallic compound.
3. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, said hard mask layer utilizes physical gas-phase deposition to make.
4. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, before forming said hard mask layer, also is included in the step that forms the cap layer on the said low-K dielectric layer.
5. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, saidly is annealed into boiler tube annealing or RTP annealing.
6. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, said annealing is carried out within 1 minute～10 hours after forming hard mask layer.
7. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, the time of said annealing is 10～1000 seconds.
8. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, the pressure of said annealing is 1～760 holder.
9. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, the gas of said annealing is one or more in argon gas, helium, the nitrogen, and the gas flow scope of said annealing is 5～1000sccm.
10. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, the temperature range of said annealing is 300～500 degrees centigrade.
11. the manufacture method of interconnection structure as claimed in claim 1 is characterized in that, said interconnection structure is a dual-damascene structure.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800628A (en) * | 2012-09-11 | 2012-11-28 | 上海华力微电子有限公司 | Method for producing dual damascene structure capable of preventing pattern collapsing |
| CN105633011A (en) * | 2014-11-27 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of interconnection structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020172898A1 (en) * | 2001-05-17 | 2002-11-21 | Honeywell International Inc. | Layered hard mask and dielectric materials and methods therefor |
| CN100476021C (en) * | 2003-02-04 | 2009-04-08 | 泰格尔公司 | Method to deposit an impermeable film onto a porous low-K dielectric film |
| CN101461042A (en) * | 2006-05-31 | 2009-06-17 | 东京毅力科创株式会社 | Heat treatment method, heat treatment apparatus and substrate processing apparatus |
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2010
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020172898A1 (en) * | 2001-05-17 | 2002-11-21 | Honeywell International Inc. | Layered hard mask and dielectric materials and methods therefor |
| CN100476021C (en) * | 2003-02-04 | 2009-04-08 | 泰格尔公司 | Method to deposit an impermeable film onto a porous low-K dielectric film |
| CN101461042A (en) * | 2006-05-31 | 2009-06-17 | 东京毅力科创株式会社 | Heat treatment method, heat treatment apparatus and substrate processing apparatus |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800628A (en) * | 2012-09-11 | 2012-11-28 | 上海华力微电子有限公司 | Method for producing dual damascene structure capable of preventing pattern collapsing |
| CN105633011A (en) * | 2014-11-27 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of interconnection structure |
| CN105633011B (en) * | 2014-11-27 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The production method of interconnection structure |
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