CN102437837B - Generation method of media variable bit (MVB) and windows vista 64 bit (WTB) test frame - Google Patents
Generation method of media variable bit (MVB) and windows vista 64 bit (WTB) test frame Download PDFInfo
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Abstract
The invention discloses a generation method of a media variable bit (MVB) and windows vista 64 bit (WTB) test frame, which comprises the following steps that: setting parameters; generating a point sequence; generating each part of a frame; splicing the frame; transmitting the point sequence of the complete frame to the functional signal generator through an order identified by a function signal generator, and generating waveform through the function signal generator. Due to the adoption of the generation method of standard frames, aberrance frames and error frames of the MVB and WTB, the MVB/WTB waveform is edited, a rising edge time, a trailing edge time of the waveform can be adjusted, and the aberrance (altered rising edge time, altered trailing edge time and altered pulse width) and error (altered coding way, error cyclic redundancy check (CRC) verification code, altered starting position, altered ending position and altered frame head) MVB/WTB waveform can be edited, and a waveform transmission frequency can be set without changing original period of the waveform signal; and each part forming the waveform can be used repeatedly, each part is encapsulated by different functions, and the problem that the present waveform editor is free from supporting Manchester encoding edition in WVB/WTB.
Description
Technical field
The present invention relates to the communications field, particularly a kind of generation method of MVB and WTB test frame.
Background technology
When MVB/WTB equipment carries out receiver test, need the MVB/WTB frame of mock standard or the MVB/WTB waveform of distortion or start bit, full stop, start delimiter to be different from the MVB/WTB frame of standard regulation, be used for judging the performance of MVB/WTB equipment under test receiver, current Waveform Editor is not supported the Manchester's code editor in MVB/WTB, cannot arbitrarily adjust rising edge, trailing edge time, during waveform compilation, code element is edited one by one one by one, very loaded down with trivial details and inconvenient.
Summary of the invention
Technical problem to be solved by this invention is, for prior art deficiency, provides a kind of generation method of MVB and WTB test frame, solves current Waveform Editor and do not support the problem of the Manchester's code editor in MVB/WTB.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of generation method of MVB and WTB test frame, and the method is:
The generation method of standard frame is:
1) setup parameter:
A) set the counting and test frame type of tranmitting frequency, waveforms amplitude, selection editor waveform of function signal generator, test frame type is divided into MVB frame and WTB frame, and MVB frame is divided into ESD prime frame, ESD from frame, EMD prime frame, EMD from frame;
B) by the tranmitting frequency of setting, required the counting of calculating 1BT pulsewidth of counting of selecting editor's waveform, the maximum of the amplitude resolution of waveforms amplitude respective function signal generator; If generate distortion frame, change the transmission amplitude of function signal generator, make amplitude depart from the value of standard regulation;
C) set rising edge, trailing edge and count, if ESD type arranges that low level before start bit is counted and stop bit is counted; If generate distortion frame, setting rising edge, trailing edge depart from standard value while counting;
2) generate point sequence: by step 1) the middle parameter of setting, determine rising edge, trailing edge, high level and low level counting, the amplitude of calculation level, determines point sequence; If want generation error frame, the point sequence of generation error;
3) each several part of delta frame: for MVB frame, generate start delimiter, frame data, verification sequence and stop bit; For WTB frame, generate frame head, attribute field 1, HDLC data, FCS-16 verification sequence, attribute field 2 and stop bit; If want generation error frame, verification sequence is made into wrong;
4) frame splicing: MVB frame is stitched together start bit, frame head, frame data, CRC check code, stop bit to form a complete MVB frame; Link data, FCS check code, attribute field, a stop bit that WTB fills frame head, link control field, increase position are stitched together and form a complete WTB frame;
Download: the instruction that the point sequence of complete frame is identified by function signal generator sends in function signal generator, function signal generator generates waveform.
The generation method of standard frame, distortion frame and the erroneous frame of MVB of the present invention and WTB is edited for MVB/WTB waveform, can adjust rising edge, the trailing edge time of waveform, distortion be can edit and (rising edge, trailing edge time changed, change pulse duration), mistake (change coded system, the CRC check code of mistake, changes start bit, stop bit, change frame head) MVB/WTB waveform, can set waveform transmission frequency and not change natural period of waveform signal; The various piece of composition waveform can be reused, and each several part all uses different functions packaged, has solved current Waveform Editor and do not support the problem of the Manchester's code editor in MVB/WTB.
Accompanying drawing explanation
Fig. 1 is the some schematic diagram of editing in function signal generator;
Fig. 2 is that function signal generator 1s sends f 65536 some schematic diagrames;
Fig. 3 is square-wave signal schematic diagram;
Fig. 4 is square-wave waveform schematic diagram in function signal generator;
Fig. 5 is the schematic diagram of the each several part of composition waveform;
Fig. 6 is the flow chart of the inventive method.
Embodiment
Below in conjunction with accompanying drawing, method of the present invention is elaborated.
In function signal generator, random waveform editor amplitude resolution is-2047 to+2047 (function signal generator model difference, amplitude resolution also can be different, but editor's principle is identical.), if for example output amplitude is set to 10Vpp, + 2047 corresponding to+5V, and-2047 corresponding to-5V, waveform can be described and (if waveform is counted, be less than 16384 points with 16384 or 65536 points, residue is counted with null-fill, automatically generates one and has the waveform of 16384; If waveform is counted, be greater than 16384 points, residue is counted with null-fill, generates the waveform of 65536.)。Fig. 1 is the point of editing in function signal generator, and the amplitude of each some acquiescence is 0.
The adjacent time is between points determined by the tranmitting frequency of function signal generator, and frequency determines that time between points has just been determined.As to set function signal generator tranmitting frequency be fHz, function signal generator will send f 16384 or 65536 points (it will be 16384 that transmitting is counted in 1 second, or 65536 by the decision of counting used of editor's waveform), as Fig. 2, sending 16384 or 65536 some times used is 1/fs.Be made as t by the above-mentioned explanation time between consecutive points that can draw, the waveform of supposition transmitting is here 65536 somes compositions (subsequent transmission waveform is counted and is all assumed to be with 65536 some editors),
t＝1/(f*65536)s (1)
Suppose and will edit one as the square-wave signal of Fig. 3, side is 1us wave period, and establishing function signal generator transmission frequency is 200Hz, one-period is used count=1/100000*200*65536=13.1072, because count, can only be integer, be 13 points so round downwards.In function signal generator, waveform compilation is as Fig. 4.Rising edge, trailing edge are counted and are determined rising edge, trailing edge time.In Fig. 4, square wave has only used 26 points to describe, and all the other 65510 points are all defaulted as in 0, figure and all points are not drawn, and have only drawn a part of point.
As an example of MVB example, elaborate below MVB signal generating principle, MVB device signal speed is 1.5Mbit/s, the cycle is 667ns (defining 667ns in IEC61375-1 standard is 1BT), frame is divided into ESD and EMD frame, ESD and EMD frame data all adopt Manchester's code, ESD is different from start bit and the full stop of EMD, start delimiter is identical, start delimiter be one by { start bit, " NH ", " NL ", " 0 ", " NH ", " NL ", " 0 ", " 0 ", " 0 " } composition fixed sequence program, in sequence, " NH " is 1BT high level coding, " NL " is 1BT low level coding, " 0 " is 1BT Manchester's code.
Because periodic width is 1BT, used counting of each cycle:
n＝1BT/t (2)
N is for rounding downwards, and t obtains in 1 formula.
ESD, EMD waveform can be split as some regular governed parts and special part, and each part writes, and as shown in Figure 5, are then stitched together and are converted into the program language that function signal generator can be identified.
A) user oneself definition rising edge Y1, trailing edge Y2 count, and low level L1, L4 count, H1=L2=(n-Y1-Y2)/2, H2=H1+Y1, L3=L2+Y2, L5=L4+Y2.Y1, Y2, L1, L4 is that integer H1, L2 round downwards.Round downwards and can cause pulsewidth to narrow, with the error that has of standard regulation, but tranmitting frequency is very high, and therefore error can be very not large;
B) in cycle, each point downloads to the algorithm of amplitude in function signal generator: the waveform peak-to-peak value sending when us is A, in Fig. 5: amplitude=(the actual magnitude * 2/A of each point) * (2047) of low level mid point, amplitude=(the actual magnitude * 2/A of each point) * 2047 of high level mid point, amplitude=Xn/ (Xn-1) * 4094+ (2047) of rising edge mid point, Xn rounds downwards, amplitude=Xn/ (Xn-1) * (4094)+2047 of trailing edge mid point, Xn represents n point in rising edge, trailing edge, and n value is since 0;
C) by the above, high level, low level, rising edge, trailing edge with how many points are described to calculate, and the amplitude of high level, low level, rising edge, trailing edge mid point can be calculated, all parts in Fig. 5 can be described out;
D) as an example of square frame in Fig. 57 example, describe, the tranmitting frequency of setting function signal generator as us is 400Hz, transmitting is counted and is selected 65536 points, signal period is 1000ns, amplitude 5, by 1 formula, it is 28 that 2 formulas can calculate used the counting of one-period, setting rising edge Y1 is 4, trailing edge Y2 is 4, H1=L2=10, H2=14, L3=14, in high level, the amplitude of 10 points is 2047, the amplitude that low level mid point is 10 is-2047, the amplitude of rising edge mid point is (2047,-682, 682, 2047), the amplitude of trailing edge mid point is (2047, 682,-682,-2047).The sequence description that in Fig. 5, the pattern of square frame 7 can form with a point, this sequence is (2047 ,-682,682,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,682 ,-682 ,-2047 ,-2047,-2047 ,-2047 ,-2047 ,-2047 ,-2047,-2047 ,-2047 ,-2047 ,-2047).By above-mentioned example, know that in Fig. 5, all patterns can be described with a point sequence, the number of point used is all bright in each pattern acceptance of the bid.
As shown in Figure 6, the concrete steps of the inventive method are:
1. setup parameter:
A) first set the counting of tranmitting frequency, waveforms amplitude, selection editor waveform of function signal generator, frame type;
B) from realize in principle steps 1,2, can know set function signal generator tranmitting frequency, count and can calculate that 1BT pulsewidth is required counts, the maximum of the amplitude resolution of waveforms amplitude respective function signal generator;
C) set rising edge, trailing edge is counted, if ESD type, arrange that low level before start bit is counted and stop bit is counted;
2. generation point sequence:
A) after above setting parameter, rising edge Y1, trailing edge Y2, high level H1, H2, low level L1, L2, counting of L3, L4 have all been determined, by the algorithm of amplitude, calculate amplitude a little, and in Fig. 5, all point sequence corresponding to pattern have all been determined.
B) when the sequence of follow-up certain pattern of needs is just directly called the point sequence of certain pattern.
3. the each several part of delta frame:
For MVB frame:
A) generate start delimiter:
1) MVB frame is divided into ESD prime frame, ESD from frame, EMD prime frame, EMD from frame.
2) ESD prime frame start delimiter by: start bit, " NH ", " NL ", " 0 ", " NH, " NL ", " 0 ", " 0 ", " 0 " } fixed sequence program of composition, before start delimiter starts, have the low level of 115ns～135ns;
3) pattern in square frame 1 in Fig. 5 for the low level of 115ns～135ns; Start bit is described with the pattern in square frame 2 in Fig. 5; " NH " first becomes " 11 ", and 1 can use (the note: while using the pattern in square frame 3, last pattern will be low level of square frame 3,4 patterns in Fig. 5; During with pattern in square frame 4, last pattern will be high level); " NL " first becomes " 00 ", and 0 can use (the note: while using the pattern in square frame 5, last pattern will be high level of square frame 5,6 patterns in Fig. 5; During with pattern in square frame 6, last pattern will be low level); " 00 " first becomes " 01 ", and ESD prime frame start delimiter can be exchanged into { start bit, " 1 ", " 1 ", " 0 ", " 0 ", " 0 ", " 1 ", " 1, " 1, " 0 ", " 0 ", " 0 ", " 1 ", " 0 ", " 1 ", " 0 ", " 1 " };
4) ESD prime frame start delimiter is combined to form with 1,2,3,4,5,6 patterns of square frame in Fig. 5, and each pattern is comprised of its corresponding point sequence, and ESD prime frame start delimiter is the point sequence composition of square frame 1,2,3,4,5,6 patterns in Fig. 5;
5) ESD from frame start delimiter by: start bit, " 1 ", " 1 ", " 1 ", " NL, " NH ", " 1 ", " NL ", " NH " } fixed sequence program of composition, before start delimiter starts, have the low level of 115ns～135ns.ESD from frame start delimiter generation method with identical, but " 1 " first becomes " 10 ";
6) ESD prime frame start delimiter by: start bit, " NH ", " NL ", " 0 ", " NH, " NL ", " 0 ", " 0 ", " 0 " } composition fixed sequence program.EMD prime frame start delimiter generation method is with upper identical;
7) EMD from frame start delimiter by: start bit, " 1 ", " 1 ", " 1 ", " NL, " NH ", " 1 ", " NL ", " NH " } composition fixed sequence program.EMD from frame start delimiter generation method with identical;
B) delta frame data:
1) frame data user sets, and frame data are 16 systems, are converted into 2 systems in program.
As the AC of 16 systems, being converted into 2 systems is 10101100;
2) in frame data, be converted into (the note: while using the pattern in square frame 8, last pattern will be high level of square frame 8,9 patterns in 0 use Fig. 5 after 2 systems; During with pattern in square frame 9, last pattern will be low level.The primary last pattern of frame data is last pattern of frame start delimiter.), in frame data, be converted into (the note: while using the pattern in square frame 7, last pattern will be low level of square frame 7,10 patterns in 1 use Fig. 5 after 2 systems; During with pattern in square frame 10, last pattern will be high level.)；
3) data square frame in Fig. 57,8,9,10 patterns that frame data are converted into after 2 systems are combined to form, and each pattern is comprised of its corresponding point sequence, and frame data are the point sequence composition of square frame 7,8,9,10 patterns in Fig. 5;
C) generate verification sequence:
1) verification sequence is that frame data are converted into 80 and the sequence of 1 composition after 2 system data, by CRC check algorithm, calculating;
2) because verification sequence is also 0 and 1 composition, it is to be also combined to form with 7,8,9,10 patterns of square frame in Fig. 5, and verification sequence is the point sequence composition of square frame 7,8,9,10 patterns in Fig. 5;
D) generate stop bit:
1) in MVB frame, ESD stop bit is different from EMD stop bit;
2) (the note: while using the pattern in square frame 11, last pattern will be high level of pattern in square frame 11,12 in Fig. 5 for ESD stop bit; During with pattern in square frame 12, last pattern will be low level), ESD stop bit is the point sequence composition of square frame 11,12 patterns in Fig. 5.ESD stop bit pulsewidth is 125ns～666.67ns, can change by setting the value of L4 the pulsewidth of ESD stop bit;
3) (the note: while using the pattern in square frame 13, last pattern will be high level of square frame 13,14 patterns in Fig. 5 for EMD stop bit; During with pattern in square frame 14, last pattern will be low level), EMD stop bit is the point sequence composition of square frame 13,14 patterns in Fig. 5;
For WTB frame:
1) generate frame head:
A) WTB frame head consists of 1010101010101011 Serial No.s, square frame 7,10 patterns (note: while using the pattern in square frame 7, last pattern will be low level in 0 use Fig. 5 in sequence; During with pattern in square frame 10, last pattern will be high level.), square frame 8,9 patterns (note: while using the pattern in square frame 8, last pattern will be high level in 1 use Fig. 5 in sequence; During with pattern in square frame 9, last pattern will be low level.)。Because in sequence, first 1 does not above have level, so square frame 9 patterns in first 1 use Fig. 5;
B) because WTB frame head is 0 and 1 composition, it is to be combined to form with 7,8,9,10 patterns of square frame in Fig. 5, and WTB frame head is the point sequence composition of square frame 7,8,9,10 patterns in Fig. 5.
2) generate attribute field 1:
Attribute field consists of 01111110 Serial No., and its generation method is identical with generation frame head method.
3) generate HDLC data:
A) HDLC data comprise: target device, link control, source device, link data length, link data composition;
B) target device, link control, source device, link data length, link data has user to arrange, and user is set to the data of 16 systems, in program, be converted into 2 system data, 2 system data are all 0 and 1 compositions, and the generation method of HDLC data is identical with generation frame head method.
4) generate FCS-16 verification sequence;
5) FCS-16 verification sequence is 16 0 and the sequence of 1 composition that link data is generated by FCS-16 checking algorithm;
6) its generation method is also identical with generation frame head method;
7) generate attribute field 2;
8) attribute field 2 and attribute field 1 are identical sequences, and just in attribute field 2 sequences, first 0 is to judge last level of FCS-16 verification sequence while selecting square frame 7,10 pattern in Fig. 5;
9) generate stop bit;
10) (the note: while using the pattern in square frame 15, last pattern will be high level of square frame 15,16 patterns in Fig. 5 for the stop bit of WTB frame; During with pattern in square frame 16, last pattern will be low level), the stop bit of WTB frame is the point sequence composition of square frame 15,16 patterns in Fig. 5.
4. frame splicing:
A) MVB frame couples together by the each several part of MVB frame, i.e. the sequence of the point of the synthetic complete frame of the sequence set of the point of each several part;
B) WTB frame couples together by the each several part of WTB frame, i.e. the sequence of the point of the synthetic complete frame of the sequence set of the point of each several part.
5. download:
The instruction that the sequence of the point of complete frame can be identified by function signal generator sends in function signal generator, and function signal generator will generate waveform.
Distortion frame generating method:
Generation and the above-mentioned steps of distortion frame are identical, and the frame that just distorts, rising edge Y1 is set, departs from standard value during trailing edge Y2, and distortion degree can reach Y1+Y2=n, there is no high level and low level; Or change the transmission amplitude of function signal generator, make amplitude depart from the value of standard regulation.Mistake frame generating method:
Erroneous frame generates identical with above-mentioned steps, when just erroneous frame is selected the pattern in Fig. 5 in generating, should select the point sequence of the pattern in square frame 3,4,5,6 to change the point sequence that selects the pattern in square frame 7,8,9,10 into; Or by the Frame Check Sequence regeneration point sequence of correcting mistakes.
As an example of ESD prime frame example, describe, the data that ESD will send are 9110.
1. setting the tranmitting frequency of function signal generator is 300Hz, and amplitude is made as 5V, and counting of waveform of editor is 65536 points, due to be ESD frame periodic width be 666.67ns.By (1 formula) (2 formula) realizing in principle, can calculate distance t=38.148ns between points, the n=17.476 that counts used of each cycle, rounding up is 18 points.
2. set rising edge Y1=3, trailing edge Y2=3, the low level L1=3 before start bit, stop bit low level L4=5, H1=L2=6, H2=L3=9, L5=8.
Algorithm by amplitude can draw:
1) sequence that in Fig. 5, square frame 1 pattern is comprised of 3 (L3==3) individual point is (2047 ,-2047 ,-2047).
2) sequence that in Fig. 5, square frame 2 patterns are comprised of 18 (H2+Y2+L2=18) individual point is (2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,0,2047,2047,2047,2047,2047,2047,2047).
3) sequence that in Fig. 5, square frame 3 patterns are comprised of 9 (H1+Y1=9) individual point is (2047,0,2047,2047,2047,2047,2047,2047,2047).
4) sequence that in Fig. 5, square frame 4 patterns are comprised of 9 (H2=9) individual point is (2047,2047,2047,2047,2047,2047,2047,2047,2047).
5) sequence that in Fig. 5, square frame 5 patterns are comprised of 9 (Y2+L2=9) individual point is (2047,0 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047).
6) sequence that in Fig. 5, square frame 6 patterns are comprised of 9 (L3=9) individual point is (2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047).
7) sequence that in Fig. 5, square frame 7 patterns are comprised of 18 (Y1+H1+Y2+L2=18) individual point is (2047,0,2047,2047,2047,2047,2047,2047,2047,2047,0 ,-2047,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047).
8) sequence that in Fig. 5, square frame 8 patterns are comprised of 18 (Y2+L2+Y1+H1=18) individual point is (2047,0 ,-2047 ,-2047 ,-2047 ,-2047,-2047 ,-2047 ,-2047 ,-2047,0,2047,2047,2047,2047,2047,2047,2047).
9) sequence that in Fig. 5, square frame 9 patterns are comprised of 18 (H2+Y1+H1=18) individual point is (2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047,-2047 ,-2047 ,-2047 ,-2047,0,2047,2047,2047,2047,2047,2047,2047).
10) sequence that in Fig. 5, square frame 10 patterns are comprised of 18 (H2+Y2+L2=18) individual point is (2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,0 ,-2047,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047).
11) sequence that in Fig. 5, square frame 11 patterns are comprised of 8 (Y2+L4=8) individual point is (2047,0 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047).
12) sequence that in Fig. 5, square frame 12 patterns are comprised of 8 (L5=8) individual point is (2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047 ,-2047).
3.ESD starting delimiter consisting of: 1 style block in Figure 5 ( corresponding to 115ns ~ 135ns LOW ) + Figure 2 Style Box 5 ( corresponding to the start bit ) + Style Box 3 in Figure 5 (corresponding to 1 ) + style box 4 in Figure 5 (corresponding to a ) + style box 5 in Figure 5 ( corresponding to 0 ) + style box 6 in Figure 5 ( corresponding to 0 ) of the pattern block 6 + 5 ( corresponding to 0 ) in block 3 + 5 style ( corresponds to 1 ) + 4 block pattern in Figure 5 (corresponding to a ) + 4 block pattern in Figure 5 (corresponding to a ) + style box 5 in Figure 5 ( corresponding to 0 ) of the pattern block 6 + 5 ( corresponding to 0 ) + 6 block diagram patterns 5 ( corresponding to 0 ) + style box 3 in Figure 5 (corresponding to a ) + 6 in Figure 5 a block pattern ( corresponding to 0 ) + style box 3 in Figure 5 (corresponding to a ) in block 5 + 6 Style ( corresponding to 0 ) + style box 3 in Figure 5 (corresponding to 1 ) , the point sequence is converted to : ( -2047 , -2047 , -2047,2047,2047,2047,2047,2047,2047,2047,2047,2047 , 2047,0,2047,2047,2047,2047,2047,2047,2047 , -2047,0,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047 , 2047,2047,2047,2047,0 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , - 2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047,0,2047,2047,2047,2047,2047 , 2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,2047,0 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047,0,2047,2047,2047,2047,2047,2047,2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047 , -2047,0,2047,2047,2047,2047,2047,2047,2047 ) .
The frame data of 16 systems that 4.ESD sends are 9110, and being converted into 2 system data is 1001000100010000.ESD frame data consists of: Figure 5 box 10 style (corresponding to the 1 box in Figure 5) + 9 style (corresponding to the 0 box in Figure 5) + 8 style (corresponding to the 0 box in Figure 5) + 10 style (corresponding to the 1 box in Figure 5) + 9 style (corresponding to 0) block + 5 in the 8 style (corresponding to the 0 box in Figure 5) + 8 style (corresponding to the 0 box in Figure 5) + 10 style (corresponding to the 1 box in Figure 5) + 9 style (corresponding to the 0 box in Figure 5) + 8 style (corresponding to the 0 box in Figure 5) + 8 style (corresponding to 0) block + Figure 5 the 10 style (corresponding to the 1 box in Figure 5) + 9 style (corresponding to the 0 box in Figure 5) + 8 style (corresponding to 0) + 5 Chinese box 8 style (corresponding to the 0 box in Figure 5) + 8 style (corresponding to 0), are transformed into a sequence of points: (2047204720472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047204720472047204720472047204720472047, 0, -2047, -2047, -204 7, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047204720472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047204720472047204720472047204720472047, 0, -2047 , -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 020472047204720472047204720472047, 0, -2047, -2047, -2047, -2047, -2047, -2047, -2047, -2047, 02047204720472047204720472047).
5. the CRC check sequence 2 system data 1001000100010000 of frame data being calculated by CRC check algorithm is 01111110.Frame Check Sequence consists of: square frame 9 patterns (corresponding 0) in square frame 7 patterns (corresponding 1)+Fig. 5 in square frame 7 patterns (corresponding 1)+Fig. 5 in square frame 7 patterns (corresponding 1)+Fig. 5 in square frame 7 patterns (corresponding 1)+Fig. 5 in square frame 7 patterns (corresponding 1)+Fig. 5 in square frame 10 patterns in square frame 8 patterns in Fig. 5 (corresponding 0)+Fig. 5 (corresponding 1)+Fig. 5, being converted into point sequence is: (2047, 0,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047, 0, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 0,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047, 0, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 0,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047, 0, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 0,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047, 0, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 0,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047, 0, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 0,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047, 0, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 2047, 0,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047,-2047, 0, 2047, 2047, 2047, 2047, 2047, 2047, 2047).
7.ESD each several part all represents with point sequence, and the point sequence of each several part is coupled together and obtains the point sequence of whole frame, by instruction, all points downloaded to function signal generator.
Claims (1)
1. a generation method for MVB and WTB test frame, is characterized in that, the method is:
1) setup parameter:
A) set the counting and test frame type of tranmitting frequency, waveforms amplitude, selection editor waveform of function signal generator, test frame type is divided into standard frame, distortion frame and the erroneous frame of MVB frame and WTB frame, and MVB frame is divided into ESD prime frame, ESD from frame, EMD prime frame, EMD from frame;
B) by the tranmitting frequency of setting, required the counting of calculating 1BT pulsewidth of counting of selecting editor's waveform, the maximum of the amplitude resolution of waveforms amplitude respective function signal generator; If generate distortion frame, change the transmission amplitude of function signal generator, make amplitude depart from the value of standard regulation;
C) set rising edge, trailing edge and count, if ESD type arranges that low level before start bit is counted and stop bit is counted; If generate distortion frame, setting rising edge, trailing edge depart from standard value while counting;
2) generate point sequence: by the parameter of setting in step 1), determine rising edge, trailing edge, high level and low level counting, the amplitude of calculation level, determines point sequence; If want generation error frame, the point sequence of generation error;
3) each several part of delta frame: for MVB frame, generate start delimiter, frame data, verification sequence and stop bit; For WTB frame, generate frame head, attribute field 1, HDLC data, FCS-16 verification sequence, attribute field 2 and stop bit; If want generation error frame, verification sequence is made into wrong;
4) frame splicing: MVB frame is stitched together start bit, frame head, frame data, CRC check code, stop bit to form a complete MVB frame; WTB is stitched together frame head, link control field, link data, FCS check code, attribute field, stop bit to form a complete WTB frame;
5) download: the instruction that the point sequence of complete frame is identified by function signal generator sends in function signal generator, function signal generator generates waveform.
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| US7826381B1 (en) * | 2008-05-30 | 2010-11-02 | Spirent Communications, Inc. | Method and device test data streams bound to emulated devices |
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