CN102437095A - Technique integrating method for double etching barrier layer technology - Google Patents
Technique integrating method for double etching barrier layer technology Download PDFInfo
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- CN102437095A CN102437095A CN2011102502687A CN201110250268A CN102437095A CN 102437095 A CN102437095 A CN 102437095A CN 2011102502687 A CN2011102502687 A CN 2011102502687A CN 201110250268 A CN201110250268 A CN 201110250268A CN 102437095 A CN102437095 A CN 102437095A
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Abstract
The invention provides a technique integrating method for double etching barrier layer technology. The method comprises the following steps: when covering a tensile stress barrier layer on an NMOS (n-channel metal-oxide-semiconductor field-effect transistor), exposing the part of the source region or drain region of the NMOS on one side of a PMOS (p-channel metal-oxide-semiconductor field-effect transistor) adjacent to the PMOS out of the coverage range of the tension barrier layer; and when forming a compressive stress barrier layer on the PMOS, extending the compressive stress barrier layer to the other part of the source region or drain region of the NMOS uncovered by the tensile stress etching barrier layer, thereby avoiding partial coverage of the tensile stress barrier layer and the compressive stress barrier layer. Thus, the invention ensures the quality of the contact through holes in the subsequent manufacture, thereby enhancing the performance of the product.
Description
Technical field
The present invention relates to a kind of method for manufacturing integrated circuit, relate in particular to a kind of technology integrating method that is used for two etching barrier layer technology.
Background technology
In semiconductor fabrication process; Continue to dwindle the entering nanometer era along with characteristic size; Promote the short-channel effect (SCE) that complementary oxide semiconductor (CMOS) device performance of metal is derived; With physical restriction such as traditional dielectric medium (dielectric) thickness convergence limit, thereby the method that is difficult to continue to use simply traditional scaled down is further dwindled semiconductor dimensions.
In order to adapt to the semiconductor development need of smaller szie, people begin for the semiconductor strain technical research.Strain gauge technique is through introducing suitable strain, changes the band structure of channel region silicon, and then improves the mobility of charge carrier rate, thereby can continue to improve the performance of device when making scaled down, therefore receives development and application widely.At present, it is found that multiple technologies can produce strain at channel region, mainly comprised as on the SiGe substrate, forming strained silicon or on dielectric substrate, forming strained silicon (SOI) etc.; Or etching barrier layer (contact etch stop layer; CESL) application, it mainly is can improve the hole mobility of PMOS and the electron mobility of NMOS (as shown in Figure 1) respectively through in raceway groove, introducing suitable compression and tensile stress for an etching barrier layer.Compared to the former, the application of CESL does not need processing procedure is done the just remarkable strain gauge technique of boost device performance of very cataclysm, and manufacturing process is simpler, and practicality is stronger.
Present etching barrier layer technology is general to adopt two etching barrier layers technological, and its processes with strained silicon integrated technology need be optimized separately NMOS and PMOS.Research shows (as shown in Figure 2), introduces the tensile stress nitride of NMOS earlier, the compression of introducing PMOS again more help the performance boost of PMOS (K. Uejima, et. al., VL2007).So the technological process of DCESL is usually: at first above NMOS and PMOS, deposit one deck nitride; Adopt photoetching (using the NWELL light shield) to remove the nitride on the PMOS then, and above NMOS, form one deck tensile stress etching barrier layer; Above NMOS and PMOS, deposit one deck nitride more once more; Last photoetching (using the PWELL light shield), etching is removed the nitride of NMOS top, and above PMOS, forms one deck compression etching barrier layer.
Yet, because the NWELL of CMOS and PWELL have crossover region, according to above-mentioned technological process, can be at the etching barrier layer of NWELL and PWELL crossover region formation two superimposed.And the contact hole of part interface unit (Contact) can drop in this crossover region.And NWELL; Contact hole bottom in the PWELL has only one deck etching barrier layer to compare; The contact hole of this part n/p-well crossover region causes very big difficulty to follow-up contact hole etching (contact etch); Cause contact hole etching obstructed easily, (Fig. 3), so direct properties of product and yield of influencing.
Summary of the invention
The invention provides a kind of technology integrating method that is used for two etching barrier layer technology; It has overcome the defective in the above-mentioned existing pair of etching barrier layer technology, in two etching barrier layer technology, has avoided NWELL and PWELL crossover region to form the etching barrier layer of two superimposed.Thereby guaranteed performance of products.
A kind of technology integrating method that is used for two etching barrier layer technology of the present invention is realized its purpose through following technical scheme:
A kind of technology integrating method that is used for two etching barrier layer technology wherein, may further comprise the steps,
Step 1: on Semiconductor substrate, accomplish the preparation of PMOS and NMOS;
Step 2: deposition one deck nitride-barrier above NMOS and PMOS, etching is removed the nitride-barrier of said PMOS top afterwards, and nitride-barrier forms one deck tensile stress etching barrier layer through the part that is kept after the etching above said NMOS; And be positioned at source region or the drain region of the said NMOS of PMOS one side, its subregion near said PMOS is not covered by said tension force barrier layer;
Step 3: above said NMOS and PMOS, cover one deck nitride-barrier once more; Etching is removed the nitride-barrier that is covered in said tensile stress etching barrier layer top; And above said PMOS, form one deck compression barrier, the compression barrier extends on the another part that is not covered by the tensile stress etching barrier layer in source region or drain region of NMOS;
Step 4: deposition one deck insulating oxide above said PMOS and NMOS; Polishing, and on insulating oxide and tensile stress etching barrier layer, compression barrier, offer contact hole, wherein form the through hole that contacts NMOS grid and source region or drain region respectively, and formation contact the through hole in NMOS grid and source region or drain region respectively;
Step 5: in said contact hole deposition interconnect metal.
Above-mentioned method, wherein, the thickness on said tensile stress barrier layer is 10 ~ 500nm.
Above-mentioned method, wherein, the thickness on said compression barrier layer is 10 ~ 500nm.
Above-mentioned method, wherein, the interconnected metal that described interconnect metal adopts is a tungsten.
Offer about contact hole among the present invention and photoetching technique all is the maturation process technology in this area, thereby no longer do too much elaboration in this manual.
Adopt the present invention's and preparation method thereof advantage to be:
Adopt a kind of technology integrating method that is used for two etching barrier layer technology of the present invention; It has avoided NWELL and PWELL crossover region to form the etching barrier layer of two superimposed in two etching barrier layer technology; Thereby guaranteed in follow-up semiconductor fabrication; Contact hole offer effect, guaranteed that contact hole contacts with the good of device in the substrate, thereby guaranteed performance of products.
Description of drawings
Fig. 1 is an etching barrier layer for the influence of the electron mobility of the hole mobility of PMOS and NMOS;
Fig. 2 is the compression barrier layer of the tensile stress barrier layer of successively introducing NMOS and the PMOS performance impact comparison diagram for PMOS and NMOS;
Fig. 3 is the structural representation after the etching barrier layer in N/PWELL crossover region formation two superimposed that existing two etching barrier layers cause is offered through hole;
Fig. 4 is the structural representation after forming the tensile stress barrier layer above the NMOS among the present invention;
Fig. 5 is the structural representation after forming the compression barrier layer above the PMOS among the present invention;
Fig. 6 offers the structural representation of filling in metal interconnection layer in the through hole among the present invention on NMOS and PMOS.
Embodiment
As shown in Figure 4, adopt a kind of technology integrating method that is used for two etching barrier layer technology of the present invention, it can avoid forming the etching barrier layer of two superimposed at NWELL and PWELL crossover region, thereby has guaranteed performance of products, and it specifically may further comprise the steps,
Step 1: at first on Semiconductor substrate, accomplish the preparation of PMOS and NMOS;
Step 2: as shown in Figure 4; Deposition one deck nitride-barrier above NMOS and PMOS; Etching is removed the nitride-barrier of said PMOS top afterwards, and nitride-barrier forms one deck tensile stress etching barrier layer 8 through the part that is kept after the etching above said NMOS; Be positioned at source region or the drain region of the said NMOS of PMOS one side, its subregion 14 near said PMOS is not covered by said tension force barrier layer;
Step 3: as shown in Figure 5, above said NMOS and PMOS, cover one deck nitride-barrier once more; Etching is removed the nitride-barrier that is covered in said tensile stress etching barrier layer top; And above said PMOS, form one deck compression barrier 9, and compression barrier 9 extends on the another part 14 that is not covered by the tensile stress etching barrier layer in source region or drain region of NMOS; Said tensile stress barrier layer 8 and compression barrier layer 9 are joined, thereby avoided in the existing pair of etching barrier layer technology part tensile stress barrier layer and the overlapping problem of compression barrier layer portions.
Step 4: deposition one deck insulating oxide above said PMOS and NMOS; Polishing, and on insulating oxide and tensile stress etching barrier layer, compression barrier, offer contact hole, wherein form the through hole that contacts NMOS grid and source region or drain region respectively, and formation contact the through hole in NMOS grid and source region or drain region respectively;
Step 5: in step 4,, form interconnect metal 12 at metals such as said contact hole deposits tungsten.
In the present invention, above-mentioned method, wherein, the thickness on said tensile stress barrier layer is 10 ~ 500nm, thereby makes between tensile stress in 100Mpa ~ 3.0Gpa.Equally, the thickness on said compression barrier layer is 10 ~ 500nm, makes between tensile stress in 100Mpa ~ 3.0Gpa.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (4)
1. a technology integrating method that is used for two etching barrier layer technology is characterized in that, may further comprise the steps,
Step 1: on Semiconductor substrate, accomplish the preparation of PMOS and NMOS;
Step 2: deposition one deck nitride-barrier above NMOS and PMOS, etching is removed the nitride-barrier of said PMOS top afterwards, and nitride-barrier forms one deck tensile stress etching barrier layer through the part that is kept after the etching above said NMOS; And be positioned at source region or the drain region of the said NMOS of PMOS one side, its subregion near said PMOS is not covered by said tension force barrier layer;
Step 3: above said NMOS and PMOS, cover one deck nitride-barrier once more; Etching is removed the nitride-barrier that is covered in said tensile stress etching barrier layer top; And above said PMOS, form one deck compression barrier, the compression barrier extends on the another part that is not covered by the tensile stress etching barrier layer in source region or drain region of NMOS;
Step 4: deposition one deck insulating oxide above said PMOS and NMOS; Polishing, and on insulating oxide and tensile stress etching barrier layer, compression barrier, offer contact hole, wherein form the through hole that contacts NMOS grid and source region or drain region respectively, and formation contact the through hole in NMOS grid and source region or drain region respectively;
Step 5: in said contact hole deposition interconnect metal.
2. method according to claim 1 is characterized in that, the thickness on said tensile stress barrier layer is 10 ~ 500nm.
3. according to the method described in the claim 1, it is characterized in that the thickness on said compression barrier layer is 10 ~ 500nm.
4. method according to claim 1 is characterized in that, the interconnected metal that described interconnect metal adopts is a tungsten.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683271A (en) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | Method for depositing pre metal dielectric (PMD) film |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090194819A1 (en) * | 2006-04-28 | 2009-08-06 | International Business Machines Corporation | Cmos structures and methods using self-aligned dual stressed layers |
| CN102130058A (en) * | 2010-01-19 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | CMOS (Complementary Metal Oxide Semiconductor) transistor and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090194819A1 (en) * | 2006-04-28 | 2009-08-06 | International Business Machines Corporation | Cmos structures and methods using self-aligned dual stressed layers |
| CN102130058A (en) * | 2010-01-19 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | CMOS (Complementary Metal Oxide Semiconductor) transistor and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683271A (en) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | Method for depositing pre metal dielectric (PMD) film |
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Application publication date: 20120502 |