CN102426345B - Three-phase harmonic wave source - Google Patents
Three-phase harmonic wave source Download PDFInfo
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- CN102426345B CN102426345B CN 201110262138 CN201110262138A CN102426345B CN 102426345 B CN102426345 B CN 102426345B CN 201110262138 CN201110262138 CN 201110262138 CN 201110262138 A CN201110262138 A CN 201110262138A CN 102426345 B CN102426345 B CN 102426345B
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Abstract
The invention relates to a three-phase harmonic wave source, which comprises a single chip microcomputer and a double-port parallel-port RAM (Random Access Memory), and further comprises a hardware clock, a phase-locked loop module, a 16-bit parallel-port CPLD (Complex Programmable Logic Device) counting and scanning module, a first 8-bit parallel-port D/A (Digital-to-Analog) converter, a second 8-bit parallel-port D/A converter, a third 8-bit parallel-port D/A converter and a fourth 8-bit parallel-port D/A converter, wherein the single chip microcomputer is used for writing in waveform data; the double-port parallel-port RAM is connected with the single chip microcomputer; the hardware clock is used for frequency control; the 16-bit parallel-port CPLD counting and scanning module is used for scanning the double-port parallel-port RAM in real time; both the first 8-bit parallel-port D/A converter and the second 8-bit parallel-port D/A converter are used for formulating an amplitude value and connected with the high-speed single chip microcomputer; and both the third 8-bit parallel-port D/A converter and the fourth 8-bit parallel-port D/A converter are used for controlling output waveforms and connected with the double-port parallel-port RAM. The output ports of the first 8-bit parallel-port D/A converter and the second 8-bit parallel-port D/A converter are connected with a first operational amplifier array; the output end of the first operational amplifier array is connected with REF (Reference) ports of the third 8-bit parallel-port D/A converter and the fourth 8-bit parallel-port D/A converter; the output ends of the third 8-bit parallel-port D/A converter and the fourth 8-bit parallel-port D/A converter are connected with a second operational amplifier array; and the second operational amplifier array is provided with a harmonic wave output end. The three-phase harmonic wave source provided by the invention has the advantages of high reliability, lower hardware cost and higher working efficiency.
Description
Technical field
The present invention relates to a kind of three phase harmonic source.
Background technology
Harmonic electric energy table calibrating installation is the indispensable equipment of electric power electric energy metrical and fields of measurement.Because in recent years, the fast development of world industryization, the widespread use of electron electric power equipment, nonlinear-load occupancy volume in electric system increases year by year, and the electric power quality problem is serious day by day.Therefore, national grid has been strengthened the improvement of harmonic wave and supervision, and releases series of standards and policies such as " State Grid Corporation of China's electrical network quality of power supply technical supervision regulations ".Though, the powerful electric energy meter manufacturer in the whole nation releases the harmonic electric energy table successively, and still, the work of tracing to the source can't launch, its key is not have on the market a harmonic electric energy table calibrating installation that meets the national rule requirement fully, and real technological difficulties are three-phase numeral harmonic source.
The electric energy meter calibrating apparatus development has been walked very long 20 years so far.The appearance of derived digital signal makes electric energy meter calibrating apparatus enter a qualitative leap, and that is exactly that electrician's formula has been moved towards electronic type, develops into program control type afterwards, and even present intellectual.But intellectual and imperfection, the generally requirement that does not all reach the harmonic source dynamic electric energy.
One. based on the digital signal origin system of ROM.This is first generation digital signal origin system, and waveform signal leaves among the ROM, and its block diagram is seen Fig. 1:
This form, output amplitude is realized by CPU control D/A converter B; Output waveform " is read " ROM by CPU gated sweep circuit and is realized.Sinusoidal waveform point of quantification (data form) leaves in the ROM cell.Its advantage is simple, reliable, anti-interference good.Shortcoming is function singleness, and index is low, in early days, and a kind of pattern of signal source preferably of still can yet be regarded as.
But along with the raising of national rule, the degree of distortion of signal source requires lower, can only increase the ROM cell capacity, simultaneously corresponding increase scanning output line quantity; Signal source amplitude adjusting fineness requirement is higher, can only increase the D/A converter figure place, and 10 to 12, in addition higher.This form hardware cost significantly increases, and module area also sharply increases, and function has been used the limit.Can also meet the demands but use.
Two. because the further raising that national rule requires the calibrating installation power factor (PF), especially the requirement to phase equilibrium is more fine and smooth when three-phase is idle, and early stage pattern has been not suitable for the requirement of device.It is mainly reflected in the form of ROM cell and fixes, and the hardware scanning circuit does not have dirigibility again, and phase shift is restricted.So, new signal source mode producing, see Fig. 2: based on the digital signal origin system of host computer (PC).This is second generation digital signal origin system.Waveform signal is directly produced by host computer (mainly being PC).The digital waveform signal that produces sends microprocessor to by communication interface, microprocessor again deposit data in the RAM that can write again.Output waveform is quite flexible, because the PC arithmetic capability is extremely strong, can satisfy the requirement of various conventional tests substantially.But its shortcoming still exists, and it mainly shows: 1, communication speed is slow, if will improve the signal source precision, amount of communication data will be multiplied; 2, the work real-time performance is poor, can't satisfy special voltage, current testing that rules require.
Three, from increasing work efficiency and two aspects that require of system real time are considered, and for satisfying the requirement of harmonic electric energy table dynamic electric energy, digital signal origin system based on DSP or FPGA arises at the historic moment, this is third generation digital signal origin system, it is widely used among the comparatively advanced electric energy meter calibrating apparatus, and its work block diagram as shown in Figure 3.Digital signal processing (Digital Signal Processing, be called for short DSP) and field-programmable gate array (Field Programmable Gate Array is called for short FPGA), development in recent years is rapid, all is fit to the high-speed data computing, and its arithmetic capability is not that single-chip microcomputer can be compared.In the digital signal origin system, it can real-time operation, and sends corresponding data rapidly.It is very flexible to produce sinusoidal waveform or harmonic wave forms, can satisfy the requirement of the various test waveforms of output.
But still there is not enough place in it: 1. poor reliability.Its frequency of operation is very high, and the wiring board cabling requirement is very high, in industrial applications, very easily is interfered, and makes program fleet or overflows, and this is fatal weakness.2. hardware cost height.High-speed dsp or FPGA are expensive, and 16 D/A converter prices are also high, and external crystal oscillator price is also very high, and stability is leading indicator.3. use in the harmonic electric energy meter apparatus, if require the more overtone order of output or lower waveform distortion, calculated amount all will significantly increase, and speed still can be slack-off.The change of each waveform as phase shift, will be recomputated output waveform, and work efficiency descends gradually.
Summary of the invention
In order to overcome existing harmonic source poor reliability, hardware cost is higher, work efficiency is lower deficiency, the invention provides a kind of reliability height, hardware cost is lower, work efficiency is higher three phase harmonic source.
The technical scheme that the present invention solves its technical matters is: a kind of three phase harmonic source, comprise be used to the single-chip microcomputer that writes Wave data, also comprise dual-port parallel port RAM, this dual-port parallel port RAM has data input port, data output, input port, address, address scan mouth, and the data input port of described dual-port parallel port RAM, input port, address are connected with described single-chip microcomputer;
Also comprise hardware clock, phase-locked loop module for control output waveform frequency, described hardware clock is connected with described phase-locked loop module, also comprise for 16 parallel port CPLD counting scan modules that dual-port parallel port RAM carried out real time scan, described 16 parallel port CPLD counting scan module is connected alternately with described phase-locked loop module, and described 16 parallel port CPLD counting scan module also is connected with the address scan mouth of described dual-port parallel port RAM;
Also comprise for the one 8 parallel port digital to analog converter of regulation amplitude, the 28 parallel port digital to analog converter, the data port of described the one 8 parallel port digital to analog converter, the data port of the 28 parallel port digital to analog converter all are connected with described single-chip microcomputer, and the REF mouth of the REF mouth of described the one 8 parallel port digital to analog converter, the 28 parallel port digital to analog converter is connected with the output of base modules;
Comprise that also described the 38 parallel port digital to analog converter, the 48 parallel port digital to analog converter all are connected with the data output of described dual-port parallel port RAM for the 38 parallel port digital to analog converter, the 48 parallel port digital to analog converter of control output waveform;
The delivery outlet of described the one 8 parallel port digital to analog converter, the 28 parallel port digital to analog converter is connected with the first amplifier array, the output terminal of the described first amplifier array is connected with the REF mouth of described the 38 parallel port digital to analog converter, the 48 parallel port digital to analog converter, the output terminal of described the 38 parallel port digital to analog converter, the 48 parallel port digital to analog converter is connected with the second amplifier array, and the described second amplifier array has humorous wave output terminal.
Principle of work of the present invention is: single-chip microcomputer writes Wave data in the RAM of dual-port parallel port by data input port and input port, address, sets up the waveform form, and the address difference that writes can realize phase shift.Single-chip microcomputer sends most-significant byte, the least-significant byte of amplitude signal to the one 8 parallel port digital to analog converter and the 28 parallel port digital to analog converter respectively, the one 8 parallel port digital to analog converter and the 28 parallel port digital to analog converter calculate output voltage by base modules, pass to the first amplifier array, the first amplifier array passing ratio adds up, output valve is passed to the REF mouth of the 38 parallel port digital to analog converter and the 48 parallel port digital to analog converter, thereby stipulate the amplitude of output waveform.
Single-chip microcomputer writes dual-port parallel port RAM with the Wave data of output, dual-port parallel port RAM is by the real time scan of 16 parallel port CPLD counting scan modules, the data of each moment point are write the 38 parallel port digital to analog converter and the 48 parallel port digital to analog converter, the 38 parallel port digital to analog converter and the 48 parallel port digital to analog converter are by the reference voltage of the REF mouth of self, calculate output voltage, send the second amplifier array to, thus the waveform (phase place) that output needs.
By changing the output reference recurrence interval of hardware clock, the frequency of phase locking of control phase-locked loop module.The high-frequency impulse of phase-locked loop module is by 16 parallel port CPLD counting scan modules counting, reach setting value after, feed back to phase-locked loop module, thereby reach phase-locked function.Simultaneously, 16 parallel port CPLD count scan module with each count value of high-frequency impulse, with 16 bit address forms dual-port parallel port RAM are carried out real time scan.Change the output recurrence interval of hardware clock, just changed the sweep frequency of 16 parallel port CPLD counting scan modules, thereby reached the effect that changes the output waveform frequency.
Beneficial effect of the present invention is: 1 is the system of core with the single-chip microcomputer, its condition of work can satisfy the requirement of industrial environment, antijamming capability is strong, be difficult for overflowing or collapsing, the output of signal waveform, with 16 inner waveform forms of parallel port CPLD counting scan module scanning dual-port parallel port RAM, reliable and stable.2. the price of single-chip microcomputer is starkly lower than the price of DSP, and it is convenient to buy; Two 8 parallel port digital to analog converters are formed 16 figure place weighted-voltage D/A converters by the amplifier array, and 8 parallel port digital to analog converters are cheap, technology maturation.3. the exchanges data between each device all adopts parallel interface, adapts to the high amount of traffic amount, and travelling speed is fast, high efficiency.4. the real time data of dual-port parallel port RAM writes and the change ability, is aided with the powerful function of monolithic machine inner microprocessor, and output flexibly, and is real-time.
Description of drawings
Fig. 1 is the schematic diagram of existing a kind of digital signal origin system.
Fig. 2 is the schematic diagram of existing another kind of digital signal origin system.
Fig. 3 is the schematic diagram of existing another kind of digital signal origin system.
Fig. 4 is schematic diagram of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
With reference to Fig. 4, a kind of three phase harmonic source, comprise be used to the single-chip microcomputer 1 that writes Wave data, also comprise dual-port parallel port RAM2, this dual-port parallel port RAM2 has data input port, data output, input port, address, address scan mouth, and the data input port of described dual-port parallel port RAM2, input port, address are connected with described single-chip microcomputer 1;
Also comprise hardware clock 3, phase-locked loop module 4 for control output waveform frequency, described hardware clock 3 is connected with described phase-locked loop module 4, also comprise for 16 parallel port CPLD counting scan modules 5 that dual-port parallel port RAM2 carried out real time scan, described 16 parallel port CPLD counting scan module 5 is connected alternately with described phase-locked loop module 4, and described 16 parallel port CPLD counting scan module 5 also is connected with the address scan mouth of described dual-port parallel port RAM2;
Also comprise the one 8 parallel port digital to analog converter 6 for the regulation amplitude, the 28 parallel port digital to analog converter 7, the data port of described the one 8 parallel port digital to analog converter 6, the data port of the 28 parallel port digital to analog converter 7 all are connected with described single-chip microcomputer 1, and the REF mouth of the REF mouth of described the one 8 parallel port digital to analog converter 6, the 28 parallel port digital to analog converter 7 is connected with the output of base modules 8;
Comprise that also described the 38 parallel port digital to analog converter 9, the 48 parallel port digital to analog converter 10 all are connected with the data output of described dual-port parallel port RAM2 for the 38 parallel port digital to analog converter 9, the 48 parallel port digital to analog converter 10 of control output waveform;
The delivery outlet of described the one 8 parallel port digital to analog converter 6, the 28 parallel port digital to analog converter 7 is connected with the first amplifier array 11, the output terminal of the described first amplifier array 11 is connected with the REF mouth of described the 38 parallel port digital to analog converter 9, the 48 parallel port digital to analog converter 10, the output terminal of described the 38 parallel port digital to analog converter 9, the 48 parallel port digital to analog converter 10 is connected with the second amplifier array 12, and the described second amplifier array 12 has humorous wave output terminal.
Principle of work of the present invention is: single-chip microcomputer 1 writes Wave data in the RAM2 of dual-port parallel port by data input port and input port, address, sets up the waveform form, and the address difference that writes can realize phase shift.Single-chip microcomputer 1 sends most-significant byte, the least-significant byte of amplitude signal to the one 8 parallel port digital to analog converter 6 and the 28 parallel port digital to analog converter 7 respectively, the one 8 parallel port digital to analog converter 6 and the 28 parallel port digital to analog converter 7 calculate output voltage by base modules 8, pass to the first amplifier array 11, the first amplifier array, 11 passing ratios add up, output valve is passed to the REF mouth of the 38 parallel port digital to analog converter 9 and the 48 parallel port digital to analog converter 10, thereby stipulate the amplitude of output waveform.
Single-chip microcomputer 1 writes dual-port parallel port RAM2 with the Wave data of output, dual-port parallel port RAM2 is by the real time scan of 16 parallel port CPLD counting scan modules 5, the data of each moment point are write the 38 parallel port digital to analog converter 9 and the 48 parallel port digital to analog converter 10, the 38 parallel port digital to analog converter 9 and the 48 parallel port digital to analog converter 10 are by the reference voltage of the REF mouth of self, calculate output voltage, send the second amplifier array 12 to, thus the waveform (phase place) that output needs.
By changing the output reference recurrence interval of hardware clock 3, the frequency of phase locking of control phase-locked loop module 4.The high-frequency impulse of phase-locked loop module 4 is by 16 parallel port CPLD counting scan modules, 5 countings, reach setting value after, feed back to phase-locked loop module 4, thereby reach phase-locked function.Simultaneously, 16 parallel port CPLD count scan module 5 with each count value of high-frequency impulse, with 16 bit address forms dual-port parallel port RAM2 are carried out real time scan.Change the output recurrence interval of hardware clock 3, just changed the sweep frequency of 16 parallel port CPLD counting scan modules 5, thereby reached the effect that changes the output waveform frequency.
Claims (1)
1. three phase harmonic source, it is characterized in that: comprise the single-chip microcomputer for generation of Wave data, also comprise dual-port parallel port RAM, this dual-port parallel port RAM has data input port, data output, input port, address, address scan mouth, and the data input port of described dual-port parallel port RAM, input port, address are connected with described single-chip microcomputer;
Also comprise hardware clock, phase-locked loop module for control output waveform frequency, described hardware clock is connected with described phase-locked loop module, also comprise for 16 parallel port CPLD counting scan modules that dual-port parallel port RAM carried out real time scan, described 16 parallel port CPLD counting scan module is connected alternately with described phase-locked loop module, and described 16 parallel port CPLD counting scan module also is connected with the address scan mouth of described dual-port parallel port RAM;
Also comprise for the one 8 parallel port digital to analog converter of regulation amplitude, the 28 parallel port digital to analog converter, the data port of described the one 8 parallel port digital to analog converter, the data port of the 28 parallel port digital to analog converter all are connected with described single-chip microcomputer, and the REF mouth of the REF mouth of described the one 8 parallel port digital to analog converter, the 28 parallel port digital to analog converter is connected with the output of base modules;
Comprise that also described the 38 parallel port digital to analog converter, the 48 parallel port digital to analog converter all are connected with the data output of described dual-port parallel port RAM for the 38 parallel port digital to analog converter, the 48 parallel port digital to analog converter of control output waveform;
The delivery outlet of described the one 8 parallel port digital to analog converter, the 28 parallel port digital to analog converter is connected with the first amplifier array, the output terminal of the described first amplifier array is connected with the REF mouth of described the 38 parallel port digital to analog converter, the 48 parallel port digital to analog converter, the output terminal of described the 38 parallel port digital to analog converter, the 48 parallel port digital to analog converter is connected with the second amplifier array, and the described second amplifier array has humorous wave output terminal.
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| CN 201110262138 CN102426345B (en) | 2011-09-06 | 2011-09-06 | Three-phase harmonic wave source |
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| CN112491075B (en) * | 2020-11-24 | 2022-07-05 | 宁波伟吉电力科技有限公司 | Novel energy storage inverter control device and control method thereof |
| CN116400290B (en) * | 2023-03-23 | 2024-03-19 | 中国电力科学研究院有限公司 | Harmonic signal source generating circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN201345550Y (en) * | 2009-02-09 | 2009-11-11 | 万望龙 | A three-phase non-office amplifying power harmonic power-supply apparatus |
| CN202230197U (en) * | 2011-09-06 | 2012-05-23 | 宁波伟吉电力科技有限公司 | Three-phase harmonic source |
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| JP3884244B2 (en) * | 2001-07-04 | 2007-02-21 | ジーイー・メディカル・システムズ・グローバル・テクノロジー・カンパニー・エルエルシー | RF transmission circuit and MRI apparatus |
| TW201044791A (en) * | 2009-04-24 | 2010-12-16 | Integrated Device Tech | Clock, frequency reference, and other reference signal generator with frequency stability over temperature variation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN201345550Y (en) * | 2009-02-09 | 2009-11-11 | 万望龙 | A three-phase non-office amplifying power harmonic power-supply apparatus |
| CN202230197U (en) * | 2011-09-06 | 2012-05-23 | 宁波伟吉电力科技有限公司 | Three-phase harmonic source |
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