CN102426335A - Method for automatically generating test pattern vector of DSP (Digital Signal Processor) device - Google Patents
Method for automatically generating test pattern vector of DSP (Digital Signal Processor) device Download PDFInfo
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- CN102426335A CN102426335A CN2011102430725A CN201110243072A CN102426335A CN 102426335 A CN102426335 A CN 102426335A CN 2011102430725 A CN2011102430725 A CN 2011102430725A CN 201110243072 A CN201110243072 A CN 201110243072A CN 102426335 A CN102426335 A CN 102426335A
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Abstract
The invention relates to a method for automatically generating a test pattern vector of a DSP (Digital Signal Processor) device. The method comprises the following steps of: coding a source program; simulating by software; establishing a development system; simulating by hardware; guiding, loading and running a final source program; acquiring and recording output information of an outside memory and output information of the DSP device, and forming an initial test pattern vector by taking a first part as a process of Bootloader after the DSP is electrified and reset and a second part as a process of codes running in the DSP; and processing and converting the initial test pattern vector, getting rid of a development tool, and directly supplying output signals of the first part of a test pattern vector to the DSP to be as input information through a simulation chip outer memory of a test system, combining the input information and the output information of the DSP when the second part of the pattern vector is changeless, and generating the test pattern vector. Through the method disclosed by the invention, the automatic generation of the test pattern vector of the DSP can be realized without needing of professional technicians to analyze each instruction period signal, and the signal acquisition is not only easy, but also convenient and reliable.
Description
Technical field
The present invention relates to the generation method of figure vector, particularly is a kind of automatic generation method of DSP element test graphics vector.
Background technology
DSP because of aspects such as weight, volume, performance and price than before large scale integrated circuit have obvious advantages and extensively adopted, the test of DSP is the important step in the DSP design cycle.On the one hand, along with the increase of system complexity, the ratio of transistor size and device pin number will be by exponential increase among the DSP, if measure each circuit, test procedure can become increasingly complex, and test vector also can be more and more darker; On the other hand, in order to protect the possessory interests of IP, IP user often has no way of finding out about it to its internal logic structure, so the emphasis of DSP test is from being to lead that to have turned to towards function be main towards circuit structure and fault.
Adopt functional level to describe the resolution chart vector that the key that realizes the DSP device detection is to obtain measured device.Prior art is general to adopt a plurality of oscillographs to carry out the detection of data at the input and output pin of device, the special messenger to the input/output signal in each cycle analyze, correction and record.Since DSP device pin number reach up to a hundred more than, level of integrated system is high, instruction is complicated; The parallel running of its inner Harvard structure, stream line operation and instruction; Make that the operation result of each clock period is very complicated and be difficult to confirm, in addition, because of the complicacy of communicating by letter between its internal module; Make the result of a lot of instruction operations directly not be transmitted on the output pin of device, signals collecting is difficulty very.Therefore, design automatic generation method ten minutes necessity of a kind of DSP element test graphics vector.
Summary of the invention
The automatic generation method that the purpose of this invention is to provide a kind of DSP element test graphics vector.
For realizing this purpose, the present invention adopts following technical scheme: a kind of automatic generation method of DSP element test graphics vector may further comprise the steps:
A. write source program:
Use assembly language or C language source program in the DSP instruction set;
B. software emulation:
Adopt CCS software that the each several part function of DSP device is simulated, form ultimate source program and executable file and .hex file;
C. build development system:
The .hex burning file to external memory storage, is built the development system of being made up of test macro, development board and adapter, for the DSP device provides outer additional device of power supply, clock, reset signal and the sheet that can normally move and information;
D. simulation hardware:
By development system the signal of the normal operation of DSP device is provided, with the simulation hardware box pass through JTAG mouth on the DSP device with the ultimate source burning program to the DSP device, check process of running program and result through CCS software;
E. Bootstrap Loading and move the ultimate source program:
Break away from the simulation hardware box, by external memory storage the ultimate source program is provided, make DSP device operation Bootloader program, copy ultimate source program is to sheet, and high-speed cruising ultimate source program, the output result;
F. form initial resolution chart vector:
Test macro is gathered and the output information of record external memory storage and the output information of DSP device, forms initial resolution chart vector;
G. generate the resolution chart vector:
The initial resolution chart vector of processing conversion is broken away from development board, by test macro simulation chip external memory, DSP is provided input information.Merge DSP input and output information, generate the resolution chart vector.
Further, said external memory storage is EEPROM.
Further, said simulation hardware box is an XDS560 simulation hardware box.
Adopt the present invention, can realize the automatic generation of DSP resolution chart vector, and need not the professional and technical personnel be analyzed by each instruction cycle signal that signals collecting is not only easy, and convenient and reliable.
Description of drawings
Fig. 1 is a schematic flow sheet of the present invention;
Fig. 2 is a development system structural representation of the present invention;
Fig. 3 is the test macro fundamental diagram;
Fig. 4 is a resolution chart vector forming process synoptic diagram.
Among the figure, " 1 ", " 0 " expression input signal, " H ", " L " represent expected output signal
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is made further detailed description, but this embodiment should not be construed as limitation of the present invention.
A. write source program:
Use the assembly language in the DSP instruction set to write source program;
B. software emulation:
Adopt CCS3.3 software that the each several part function of DSP device is simulated, convert the ultimate source program into executable .out file, and be the .hex file the .out file conversion;
C. build development system:
With the .hex burning file to external memory storage; Build the development system of forming by SP3160V LSI testing system, development board and adapter, for the DSP device provides outer additional device of power supply, clock, reset signal and the sheet that can normally move and information;
D. simulation hardware:
By development system the signal of the normal operation of DSP device is provided, with the simulation hardware box pass through JTAG mouth on the DSP device with the ultimate source burning program to the DSP device, check process of running program and result through CCS3.3 software;
E. Bootstrap Loading and move the ultimate source program:
Break away from the simulation hardware box, by external memory storage the ultimate source program is provided, make DSP device operation Bootloader program, copy ultimate source program is to sheet, and high-speed cruising ultimate source program, the output result;
F. form initial resolution chart vector:
Test macro is gathered and the output information of record external memory storage and the output information of DSP device; The figure vector that collection gets is divided into two parts; First is the process of Bootloader behind the DSP electrification reset; Second portion is the process of code at the DSP internal operation, forms initial resolution chart vector;
G. generate the resolution chart vector:
The initial resolution chart vector of processing conversion is broken away from development board, and the output signal in first's figure vector is simulated chip external memory by test macro; Directly offer DSP as input information; Second portion figure vector is constant, merges DSP input and output information, generates the resolution chart vector.
Embodiment 2
A. write source program:
Use the C language source program in the DSP instruction set;
B. software emulation:
Adopt CCS3.3 software that the each several part function of DSP device is simulated, convert the ultimate source program into executable .out file, and be the .hex file the .out file conversion;
C. build development system:
With the .hex burning file to EEPROM; Build the development system of forming by SP3160V LSI testing system, development board and adapter, for the DSP device provides outer additional device of power supply, clock, reset signal and the sheet that can normally move and information;
D. simulation hardware:
By development system the signal of the normal operation of DSP device is provided, with the simulation hardware box pass through JTAG mouth on the DSP device with the ultimate source burning program to the DSP device, check process of running program and result through CCS3.3 software;
E. Bootstrap Loading and move the ultimate source program:
Break away from the simulation hardware box, by external memory storage the ultimate source program is provided, make DSP device operation Bootloader program, copy ultimate source program is to sheet, and high-speed cruising ultimate source program, the output result;
F. form initial resolution chart vector:
Test macro is gathered and the output information of record external memory storage and the output information of DSP device; The figure vector that collection gets is divided into two parts; First is the process of Bootloader behind the DSP electrification reset; Second portion is the process of code at the DSP internal operation, forms initial resolution chart vector;
G. generate the resolution chart vector:
The initial resolution chart vector of processing conversion is broken away from development board, and the output signal in first's figure vector is simulated chip external memory by test macro; Directly offer DSP as input information; Second portion figure vector is constant, merges DSP input and output information, generates the resolution chart vector.
Embodiment 3
A. write source program:
Use the C language source program in the DSP instruction set;
B. software emulation:
Adopt CCS3.3 software that the each several part function of DSP device is simulated, convert the ultimate source program into executable .out file, and be the .hex file the .out file conversion;
C. build development system:
With the .hex burning file to EEPROM; Build the development system of forming by SP3160V LSI testing system, development board and adapter, for the DSP device provides outer additional device of power supply, clock, reset signal and the sheet that can normally move and information;
D. simulation hardware:
By development system the signal of the normal operation of DSP device is provided, with XDS560 simulation hardware box pass through JTAG mouth on the DSP device with the ultimate source burning program to the DSP device, check process of running program and result through CCS3.3 software;
E. Bootstrap Loading and move the ultimate source program:
Break away from the simulation hardware box, by external memory storage the ultimate source program is provided, make DSP device operation Bootloader program, copy ultimate source program is to sheet, and high-speed cruising ultimate source program, the output result;
F. form initial resolution chart vector:
Test macro is gathered and the output information of record external memory storage and the output information of DSP device; The figure vector that collection gets is divided into two parts; First is the process of Bootloader behind the DSP electrification reset; Second portion is the process of code at the DSP internal operation, forms initial resolution chart vector;
G. generate the resolution chart vector:
The initial resolution chart vector of processing conversion is broken away from development board, and the output signal in first's figure vector is simulated chip external memory by test macro; Directly offer DSP as input information; Second portion figure vector is constant, merges DSP input and output information, generates the resolution chart vector.
Make the content of detailed description in this instructions, belong to the those skilled in the art known prior art.
Claims (3)
1. the automatic generation method of DSP element test graphics vector may further comprise the steps:
A. write source program:
Use assembly language or C language source program in the DSP instruction set;
B. software emulation:
Adopt CCS software that the each several part function of DSP device is simulated, form ultimate source program and executable file and .hex file;
C. build development system:
The .hex burning file to external memory storage, is built the development system of being made up of test macro, development board and adapter, for the DSP device provides outer additional device of power supply, clock, reset signal and the sheet that can normally move and information;
D. simulation hardware:
By development system the signal of the normal operation of DSP device is provided, with the simulation hardware box pass through JTAG mouth on the DSP device with the ultimate source burning program to the DSP device, check process of running program and result through CCS software;
E. Bootstrap Loading and move the ultimate source program:
Break away from the simulation hardware box, by external memory storage the ultimate source program is provided, make DSP device operation Boot loader program, copy ultimate source program is to sheet, and high-speed cruising ultimate source program, the output result;
F. form initial resolution chart vector:
Test macro is gathered and the output information of record external memory storage and the output information of DSP device, forms initial resolution chart vector;
G. generate the resolution chart vector:
The initial resolution chart vector of processing conversion is broken away from development board, by test macro simulation chip external memory, DSP is provided input information.Merge DSP input and output information, generate the resolution chart vector.
2. the automatic generation method of DSP element test graphics vector according to claim 1, it is characterized in that: said external memory storage is EEPROM.
3. the automatic generation method of DSP element test graphics vector according to claim 1 and 2, it is characterized in that: said simulation hardware box is an XDS560 simulation hardware box.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154144A (en) * | 2016-06-23 | 2016-11-23 | 湖北航天技术研究院计量测试技术研究所 | The generation method of CPU element test graphics vector |
Citations (3)
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| JP2001311766A (en) * | 2000-04-28 | 2001-11-09 | Advantest Corp | Semiconductor device testing device and testing method |
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
| CN101165502A (en) * | 2006-10-18 | 2008-04-23 | 上海华虹Nec电子有限公司 | Tester simultaneous test method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2001311766A (en) * | 2000-04-28 | 2001-11-09 | Advantest Corp | Semiconductor device testing device and testing method |
| US20010041967A1 (en) * | 2000-04-28 | 2001-11-15 | Advantest Corporation | Semiconductor device testing apparatus and method for testing semiconductor device |
| CN101165502A (en) * | 2006-10-18 | 2008-04-23 | 上海华虹Nec电子有限公司 | Tester simultaneous test method |
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154144A (en) * | 2016-06-23 | 2016-11-23 | 湖北航天技术研究院计量测试技术研究所 | The generation method of CPU element test graphics vector |
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