CN102422360B - Method to calibrate start values for write leveling in a memory system - Google Patents
Method to calibrate start values for write leveling in a memory system Download PDFInfo
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- CN102422360B CN102422360B CN201080020480.8A CN201080020480A CN102422360B CN 102422360 B CN102422360 B CN 102422360B CN 201080020480 A CN201080020480 A CN 201080020480A CN 102422360 B CN102422360 B CN 102422360B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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Abstract
A memory controller (12) performs a read test for each of a plurality of memory devices (24, 26, 28, 30) to generate a read delay time of each memory device. There is a prime memory device (24) and a subset of memory devices (26, 28, 30). For each memory device of the subset, the read delay time for the prime memory device (24) is compared with the read delay time of each memory device of the subset of memory devices (26, 28, 30) to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device.
Description
Technical field
The disclosure relates generally to semiconductor, and more specifically, relates to the control of the data strobe signal being used by stores synchronized circuit.
Background technology
System clock synchronous operation in Synchronous Dynamic Random Access Memory (SDRAM) and data handling system.The input and output of SDRAM are synchronized with the work of system clock along (active edge).Double data rate (DDR) SDRAM allows to carry out data transmission on the rising edge of clock and negative edge, and the data that provide are thus twices of SDRAM.
Traditional DDR SDRAM uses the bidirectional data strobe signal that is commonly referred to as DQS signal.Data strobe receiver is from SDRAM or Memory Controller receives DQS signal and for DQS signal is provided, make valid data change center into DQS, to meet the foundation of SDRAM and the requirement of retention time.
For example, DDR SDRAM Memory Controller and SDRAM use DQS gating signal, write transmission data are sent to SDRAM() and receive data (reading to transmit) from SDRAM.DQS data strobe signal is for being captured in the each along the upper data that inputing or outputing of DQS data strobe signal.The requirement of industrial standard is that, for the transmission of writing of sdram controller execution, data change center into meet the foundation of SDRAM and the requirement of retention time with DQS.Industrial standard has defined several states of DQS before and after, during the burst-transfer of data.Before the burst-transfer of data, DQS is in being known as the high impedance status of Hi-Z.When DQS is during in Hi-Z, DQS is not stored device controller or SDRAM drives, and therefore has uncertain voltage levvl.In clock period before burst data transfer, DQS changes logic low into from Hi-Z high impedance status.This logic low state is known as data strobe preamble (preamble).After data strobe preamble, DQS changes for synchronous transmitted data.Half clock place before completing data transmission, DQS keeps logic low state.This state is known as synchronous (postamble) after data strobe.After synchronous after completing, DQS data strobe signal enters Hi-Z high impedance status again.Because DQS gating signal was not driven before data strobe preamble starts and stop in the time that rear processing in synchronous finishes, so for the timing sequence generating DQS gating signal with correct, importantly data strobe receiver will open and close at correct time place.Otherwise can produce uncertain control signal value or DQS gating signal can vibrate, and cause thus the incorrect latch of information.
Well-known, be DDR3 specification, JESD79-3 for the JEDEC specification of dynamic RAM (DRAM).Described smooth (write leveling) sequence of writing of this specification allows the initiation time of DDR controller calibration DQS gating signal and the data bit being associated, and makes them in required sequential window, to arrive DRAM from Memory Controller.In JEDEC tDQSS specification, further this sequential window is described as adding or deducting memory clock rising edge 25 percent in.This calibrating sequence is especially used in the upper DDR3 that uses leap (fly-by) layout of DDR3 dual inline memory modules (DIMMS).But before starting to write smooth sequence, controller must be able to be initiated (, start time point) each DQS gating signal, makes it arrive DRAM in predetermined sequential window.For slower DDR3 frequency, may there is a starting point for all DQS gating signals.But for higher DDR3 frequency, each gating can need independent starting point.In order to realize this starting point, need to programme separately to each gating, this need to be about the physical characteristics of accumulator system and the relevant information of each assembly thereof.In addition, need programming time and labour and need to be used for the storage of each starting point.
Summary of the invention
The invention discloses a kind of method for operational store, comprise: carry out and read test for the each storage component part in multiple storage component parts, to produce the read latency time of the each storage component part in multiple storage component parts, wherein, multiple storage component parts comprise primary memory device and do not comprise the subset of the storage component part of primary memory device, wherein, this subset comprises at least one storage component part, wherein, the read latency time is to obtain by command signal being provided to each storage component part and measuring the time receiving before signal from each storage component part in response to command signal, for the each storage component part in subset, the read latency time of each storage component part of the subset of the read latency time for primary memory device and storage component part is compared, to produce the differential delay for each storage component part of subset, for the each storage component part in subset, by the differential delay addition of writing test initial time and each storage component part of primary memory device, write test initial time with what produce each storage component part in subset, for the each storage component part in subset, test initial time with writing of the each storage component part in subset and carry out the test of writing for described each storage component part, to produce the initiation time of writing for each storage component part of subset.
The invention also discloses a kind of Memory Controller, comprising: I/O circuit, this I/O circuit comprises the multiple terminals with multiple storage component part exchange signals; Read calibration circuit, this is read calibration circuit and is coupled to described I/O circuit, for according to the read latency of reading signal that test period receives from multiple storage component parts and be identified for each storage component part of multiple storage component parts, multiple storage component parts comprise primary memory device and do not comprise the set of at least one storage component part of primary memory device, wherein, read latency is to obtain by command signal being provided to each storage component part and measuring the time receiving before signal from each storage component part in response to command signal; Counting circuit, this counting circuit is coupled to reads calibration circuit, for calculate at least one storage component part set write test initial time, wherein, for the each storage component part in set, counting circuit is by the each storage component part in set and definite read latency and the read latency of primary memory device compare to determine delay difference, and the test initial time of writing being associated by delay difference with primary memory device is added, with produce with gather in each storage component part be associated write test initial time; And write test circuit, write test circuit and be coupled to described I/O circuit, for the initiation time of writing writing test period and determine multiple storage component parts, wherein, for the each storage component part in described multiple storage component parts, what be associated with the each storage component part in multiple storage component parts writes test initial time for providing signal writing test period, to be identified for the initiation time of writing of the each storage component part in multiple storage component parts.
Brief description of the drawings
The present invention illustrates by way of example and not limited by accompanying drawing, in the accompanying drawings, and similarly element like Reference numeral representation class.Element in accompanying drawing be for easy and clearly object and illustrate and not necessarily in proportion draw.
Fig. 1 illustrates the example memory system according to a form of the present invention with block diagram form;
Fig. 2 illustrates according to rising for calibration storage system of the present invention with process flow diagram form
The illustrative methods of initial value;
Fig. 3 illustrates and the exemplary signal that calibration operation is associated of reading in the example memory system of Fig. 1 with schematic form; And
Fig. 4 illustrates and the exemplary signal that smooth operation is associated of writing in the example memory system of Fig. 1 with schematic form.
Embodiment
Shown in Fig. 1, according to example memory system 10 of the present invention, this example memory system 10 has Memory Controller 12, and described Memory Controller 12 is for controlling and communicating by letter that multiple storage component parts of system storage 15 carry out.Memory Controller 12 has control/counting circuit 16, and described control/counting circuit 16 has the first input being coupled with the output of register 14, and described register 14 is that storage component part 0 is write test initial time register.The first input/output terminal of control/counting circuit 16 is connected to the first input/output terminal of reading calibration circuit 18.Sequential circuit 20 provides internal clocking (IC) signal.The second input of control/counting circuit 16 is connected to the first output of sequential circuit 20, for receive internal clocking (IC) signal from sequential circuit 20.Internal clocking (IC) signal is also connected to reads calibration circuit 18.The second output of sequential circuit 20 is connected to the input of writing smooth circuit 22, for providing IC signal to writing smooth circuit 22.The second I/O of control/counting circuit 16 is connected to the first input/output terminal of writing smooth circuit 22.The second input/output terminal of writing smooth circuit 22 is connected to the first input/output terminal of input/output circuitry 25.Write smooth circuit 22 and be and write test circuit and for carrying out various any of test write.Should be appreciated that, in alternative form, control/counting circuit 16 can be directly connected to I/O circuit 25, for communicating with I/O circuit 25, instead of communicates with I/O circuit 25 via reading calibration circuit 18 and write smooth circuit 22 as shown in fig. 1.Sequential circuit 20 provides memory clock signal MCK and complement code thereof to each clock input of input/output circuitry 25.Should be appreciated that, in alternative form, can provide memory clock signal MCK and complement code thereof to each clock input of input/output circuitry 25 by control/counting circuit 16.The second input/output terminal of input/output circuitry 25 is connected to the second input/output terminal of reading calibration circuit 18.Input/output circuitry 25 has multiple input/output terminals of being coupled with system storage 15 and for the clock signal terminal of memory clock MCK and complement code thereof is provided respectively.System storage 15 has multiple storage component parts, and described multiple storage component parts are marked as 0,1,2 ..., to N, such as storage component part 24, storage component part 26, storage component part 28 and storage component part 30.The number of storage component part is any arbitrary number of storage component part as represented in the point in Fig. 1.Should be appreciated that, can realize only two storage component parts, although figure 1 illustrates more devices.In addition, each storage component part can be storer or their difference aspect structure or data-bus width of same type.4,8 and 16 data-bus width is traditional, but can use other data-bus widths.
As used herein, term " storage component part " is the memory circuitry with groups of memory cells and access circuit.Each storage component part may be implemented as discrete DRAM integrated circuit, receives and provide a data strobe signal (adding its complement code) in this DRAM integrated circuit.In alternative form, each storage component part can be a part with memory chip or the integrated circuit of two or more data strobe signals.In the embodiment realizing in same integrated circuit at multiple storage component parts, each storage component part is associated with a data strobe signal.
Each storage component part has for two-way transfer of data gating signal DQSx(wherein, and x changes to N from 0) input/output terminal or data strobe terminal and for the input/output terminal of the data strobe signal of two-way transmission complement code.Each one or more two-way and/or unidirectional conductor also having for transmitting command information, address information and data message in storage component part 24,26,28 and 30.Each input/output terminal of system storage 15 is connected to each input/output terminal of input/output circuitry 25.Input/output circuitry 25 locates to provide memory clock MCK, the first lead-out terminal to be connected to the first each clock input in storage component part 24,26,28 and 30 at the first lead-out terminal (clock signal terminal).Input/output circuitry 25 also locates to provide the complement code of memory clock MCK at the second lead-out terminal (second clock signal terminal), the second lead-out terminal is connected to the each second clock input in storage component part 24,26,28 and 30.In Fig. 1, those conductors wide as multidigit are shown with the oblique line on conductor.
In operation, start most, utilize the test starting point of writing in register 14 to programme to Memory Controller 12, for calibrating the first data byte, described the first data byte is the data that are associated with storage component part 24.Be data byte transmission although discussed below, can use various other data-bus widths for calibrating sequence.Below, under the context of the primary memory device in system storage 15 using storage component part 24, storage component part 24 is described.Should be appreciated that, any storage component part in the multiple storage component parts in can selective system storer 15 is as primary memory device.Other storage component parts form the subset of the storage component part that does not comprise primary memory device.This writes test starting point is initiate DQS gating signal from Memory Controller 12 to storage component part 24 to allow that the data strobe that sends to storage component part 24 is successfully write to smooth time point.After Memory Controller 12 is carried out to initialization, such as carry out guiding ROM(not shown) in storage initialization routine after, Memory Controller 12 according to the requirement in JEDEC specification by the each storage component part initialization in system storage 15.Can also carry out other operations according to JEDEC specification.Send order to DRAM, and as response, storage component part 24,26,28 and 30 will send to Memory Controller 12 DQS and complement code thereof.Also send relevant data bit.By read calibration circuit 18 carry out read calibration, will turn back to the data strobe of Memory Controller 12 and/or the total delay of related data to determine.Control/counting circuit 16 will use from the result of reading calibration circuit 18, to be created on calibration storage device 26,28 and to write the starting point that smooth circuit 22 is used at 30 o'clock.Below, if provided about definite starting point further illustrating with calibration storage device 26,26 and 30 in connection with Fig. 2.Then, write smooth circuit 22 and will proceed to write smooth sequence for all data bytes in system storage 15.Writing smooth is that one is write test, the ability of its testing memory system 10 accurate writing informations.Control/the counting circuit 16 of Memory Controller 12 gives an order to exit calibration mode.Then, acquiescence enters the normal mode of the operation of accumulator system 10.Control/counting circuit 16 is not only as control circuit but also as counting circuit, for calculating the starting point calibration storage device 26,28 and at 30 o'clock.The implementation that is noted that control/counting circuit 16 can be different, and can use the circuit of realizing separately these functions or sharing the implementation of these functions.
Shown in Fig. 2 according to the further details of the calibration mode of Memory Controller 12 of the present invention.The object of calibration mode is, for any following write order in storage component part 24,26,28 and 30, determines the initiation time of the each byte that meets JEDEC tDQSS specification.Be noted that and can realize system storage 15 by the memory-aided multiple blocks of profit (rank), wherein, block is defined by being subject to the set of the independent optional storage component part of chip of controlling.In other words,, if the storage component part of another block is realized in system storage 15, block will be controlled discretely with storage component part 24,26,28 and 30 in addition.The other block of storer must circulate independently or use the result of first memory block in whole independently calibration process.In step 32, enter calibration mode.In step 34, read test to comprising that all storage component parts of primary memory device are carried out.Primary memory device is the device of the programming with storage in register 14 being write to test initial time.In a form, primary memory device is the interior unique device that has programming and write test initial time of system storage 15, and every other device has by writing test initial time and reading their the test initial time that the result of calibration is determined according to primary memory device.In a form, primary memory device is selected as storage component part 24.Should be appreciated that, any storage component part in can selective system storer 15 is as primary memory device.In step 34, that reads that test determines each storage component part reads loop delay or read latency.Loop as herein described is arbitrary single path that exist and that turn back to Memory Controller 12 between Memory Controller 12 and each storage component part of system storage 15.Although use be term " loop ", desired or needs be not specific geometric configuration or structure.In step 36, for the each storage component part except primary memory device, the loop delay of reading of reading loop delay and main device of this storage component part is made comparisons, to produce the differential delay of each storage component part.In step 38, for the each storage component part except primary memory device, the programming of adding primary memory device for the differential delay of this storage component part to is write to test initial time.Differential delay and programming write test initial time this storage component part of combination results write test initial time.Should be appreciated that, for the each storage component part except primary memory device, differential delay can be positive length of delay or the negative length of delay as variable in processing, and temperature and voltage will produce different impacts to each storage component part.In step 40, test initial time with writing of this storage component part each storage component part is carried out and write smooth processing.Write smooth processing and produce the initiation time of writing for this storage component part.Write the initiation time and be the time on first edge that assert DQS gating signal for following write order.Side by side initiate the complement code signal of DQS with DQS.Although this instructions has been described rising edge and the negative edge of DQS, the complement code signal of DQS changes in the opposite direction.For example, if there is the rising edge of DQS, there is the negative edge of the complement code signal of corresponding DQS.Should also be noted that the while with MCK, also initiate the complement code of MCK, and it will have contrary transformation with MCK.In step 42, exit the calibration mode of operation, and start step 44.In step 44, with the write order of making any storage component part to the storage component part 24,26,28 and 30 in system storage 15 for the initiation time of writing of this storage component part.Therefore, should be appreciated that, Fig. 2 instructed for following write order, for calibrating the initial value of each byte (, each storage component part) and the method for the initiation time of each byte.
Shown in Fig. 3 is the sequential chart of explanation for a part of reading calibration process for accumulator system 10.Memory clock MCK is shown as free-running operation clock.In any period of memory clock, assert read command.Should be noted that the address signal based on to storage component part 24,26,28 and 30 and the combination of control signal produce read command by Memory Controller 12.On first rising edge of memory clock, all address signals of the interface between Memory Controller 12 and system storage 15 and control signal are stored device device 24,26,28 and 30 and catch.In a form, in the time that storage component part 24,26,28 and 30 is asserted to read command, read loop delay and start.In another form, as shown in Figure 3, read loop delay and start from the rising edge of the MCK clock signal that captures read command.There is the traveling time being associated with the each storage component part in the storage component part 24,26,28 and 30 of MCK clock signal and read command arrival system storage 15.After capturing read command, after reading reaction time and the MCK being associated and DQS skew generation, storage component part is urged to Memory Controller 12 by DQS with the data bit being associated.Also exist DQS and data bit to get back to the input/output circuitry 25 and the traveling time of reading calibration circuit 18 of Memory Controller 12.The first rising edge being driven by the each storage component part in storage component part 24,26,28 and 30 determines when read loop delay finishes.As shown in Figure 3, reading loop delay can be different, wherein, and for example, compare for the loop delay of reading of primary memory device (, storage component part 24), storage component part 30 read loop delay roughly late one-period finish.Should be noted that the cycle differentiation of reading loop delay is arbitrarily.Between storage component part to read loop delay poor can be amount any time.Generally speaking, Fig. 3 illustrates with returning of the reaction time of asserting and the response of read command is associated and DQS data strobe signal and may how between the each storage component part in system storage 15, change.
Shown in Fig. 4 is the sequential chart of explanation for a part of writing formation process for the JEDEC definition of the accumulator system such as accumulator system 10.The storage component part 24,26,28 and 30 of this sequential chart hypothesis accumulator system 10 smooth pattern of writing in operation at present.Shown memory clock MCK or free-running operation clock.First, must in the sequential window limiting, assert DQS data strobe, to start to write formation process.After first of DQS asserts, storage component part X will respond with the state on DQ signal.This state representation as shown in the arrow in Fig. 4 in the time asserting DQS the value of MCK.In this example, in the time asserting DQS, MCK is low.Therefore, assert for DQS subsequently, Memory Controller 12 shifts out DQS signal when further.The sequence of DQS signal will continue always, until storage component part X asserts DQ signal, it will signal the rising edge of time shift of DQS through MCK signal.Now, result is in the desired tolerance limit of the rising edge of MCK signal.In addition, also known just at least one in the DQS initiation time current or that follow subsequently in desired tolerance limit.Any (or multiple) in these two continuous DQS initiation times can initiate the time with acting on definite DQS of write operation subsequently.Complete write smooth after, should calibrate DQS initiate the time, make it will meet JEDEC tDQSS specification.Should be appreciated that, can with there is toto caelo as shown in Figure 4 this process.In other words, an it can be asserted that DQS signal after MCK signal has been converted to high level, and before MCK signal changes, a DQS signal sequence ground time shift is gone back, until DQS signal changes.
Till now, should be appreciated that, a kind of accumulator system and method are provided, it calibrates taking every byte or every storage component part the particular initial value of writing formation process as basis.Only require a programming initial value is stored in accumulator system.By only storing an initial value, provide a kind of programming model of simplification.Only must a value be calculated and be programmed, reduce like this final user's of accumulator system 10 time and complicacy.Before, multiple initial values have to be stored in the permanent storage device for higher-frequency operation.Require this class value is stored in guiding ROM or other nonvolatile memories or requires to use programmable fuse.Except determining that the required time of desired value, sort circuit also needs final user's programming time.Sort circuit also needs additional space and limits the size of other available circuits.In addition, the use of this predetermined a lot of initial values is limited to the particular memory device in accumulator system.If carry out storer upgrading or substitute with new memory device in accumulator system, the initial value before can be no longer valid.Therefore, the non-volatile memories of all initial values stops alternative storage component part to be used.Current disclosed method can only be determined or initial value of precomputation for selected storage component part or primary memory device user.Therefore, final user does not need to determine or have any knowledge of the signal skew existing between multiple storage component parts in accumulator system.Internal circuit uses the method for calculating for the every other initial value of other (non-master) storage component parts.Therefore, final user need not calculate the multiple storer initial values that are exclusively used in given storage component part.In addition, final user is provided the dirigibility that can in use change subsequently storage component part, and can not emit and have not exercisable risk due to the fixing incorrect initial value in the permanent or nonvolatile memory being programmed in system.Therefore, utilize accumulator system described here and method, come the final user's of simple implementation high speed Double Data Rate DRAM interface programming and plate designing requirement.
In a form, a kind of Memory Controller is provided herein, wherein, for storage stack device, proofread and correct and make the effective starting point of information for all devices except a storage component part.This storage component part is known as primary memory device, and it has makes effectively its starting point of information by what calculate before design on board level person.Based on read the calibrating sequence knowledge of the skew between storage component part afterwards in execution, calibrate the effective starting point of information that is used in other storage component parts.The clock signal skew existing between various storage component parts for measuring system, in the time that read message turns back to Memory Controller 12, determines and during read operation, between each storage component part, has delay how long.Should be appreciated that, can realize during read operation for determining the circuit of clock skew with various types of circuit.By applying deviation between each storage component part to the predetermined starting point of writing path (, clock skew), all starting points except one of starting point can be by Memory Controller instant computing (, generating) during the storer control calibration mode of operation.In method described herein, can use software program so that the starting point of primary memory device is programmed, and need to be about the knowledge of the clock skew existing between other storage component parts of system.Therefore, for design on board level teacher provides very large dirigibility.Conventionally, need to the type of all storage component parts and the specific knowledge of the specification of accumulator system, to calculate the starting point of each storage component part.Therefore, by the starting point of calculating for all storage component parts before using, final user is locked onto to very specific memory specifications, and in the situation that not recalculating and again store new initial point value, almost cannot change storage component part or layout.In addition, method described herein allows the physical layout of accumulator system plate to modify, and the ability of compensating clock skew is not had to negative effect, and clock skew is the route in accumulator system or layout owing to storage component part directly.
In alternative form, can use various types of DRAM devices.In alternative form, the value that is provided to register 14 can be stored in accumulator system 10 or in the outside of accumulator system 10, on disc driver, in nonvolatile memory (comprise and use fuse, anti-fuse or ROM) or use resistor coding.In addition, can realize disclosed circuit with various types of logical circuits.
In a form, provide a kind of by the each execution in multiple storage component parts being read to test the method for the read latency time operational store to produce the each storage component part in multiple storage component parts.Multiple storage component parts comprise primary memory device and do not comprise the storage component part subset of primary memory device, and wherein, described subset comprises at least one storage component part.For the each storage component part in described subset, the read latency time of each storage component part of the read latency time for primary memory device and described storage component part subset is compared, to produce the differential delay for each storage component part of described subset.For the each storage component part in described subset, the differential delay of writing test initial time and each storage component part of primary memory device is combined, write test initial time to produce for each storage component part.For the each storage component part in described subset, carry out the test of writing for each storage component part with testing initial time for writing of each storage component part, to produce the initiation time of writing for each storage component part of described subset.In another form, with the initiation time of writing that test initial time produces described primary memory device of writing for primary memory device, to carry out the test of writing for primary memory device.Carry out the write operation of the each storage component part in described subset with the initiation time of writing of the each storage component part for described subset.In a form, for storage component part write initiate persond eixis during storage component part is carried out to write operation by Memory Controller the sequential to the data strobe signal of storage component part.In another form, for writing the sequential of initiating the memory clock signal that data strobe signal receives about described storage component part described in persond eixis described in storage component part.In another form, the each execution in described multiple storage component parts is read to test and comprise: Memory Controller provides command signal and measures in response to described command signal to each storage component part and receives the signal time before from each storage component part.In another form, for the each storage component part in described subset, described in write test initial time instruction with respect to being provided to the memory clock signal of each storage component part, be provided to the sequential of the signal of the each storage component part in described subset by Memory Controller.In another form, each storer in described subset is carried out to write to test and comprise: Memory Controller provides a series of at least one pulse to each storage component part, wherein, for writing test initial time instruction described in each storage component part with respect to the sequential of the first pulse of the described series of the clock signal that is provided to each storage component part.In another form, write test described in execution and comprise: each storage component part provides about the instruction that receives pulse in the particular phases of described memory clock signal from described Memory Controller.In another form, the each storage component part in described multiple storage component parts is characterized as being DRAM storage component part.In another form, poor between the length in the clock signal path between the length that at least depends on the clock signal path between Memory Controller and each storage component part described time delay and described Memory Controller and the described primary memory device of each storage component part of described subset.In another form, by read described in carrying out in the storer of calibration mode test, described comparison, described combination execution and described in write the execution of test.
In another form, a kind of Memory Controller is provided, it has I/O circuit, and described I/O circuit comprises the multiple terminals with storage component part exchange signal.Provide and read calibration circuit, it is for according to the read latency of reading signal that test period receives from storage component part and determine the each storage component part described multiple storage component part, and described multiple storage component parts comprise primary memory device and do not comprise the set of at least one storage component part of described primary memory device.Counting circuit calculates writes test initial time for the set of at least one storage component part, wherein, for the each storage component part in described set, described counting circuit will compare to determine delay difference for the read latency of the definite read latency of each storage component part and described primary memory device, and what be associated by described delay difference with described primary memory device writes test initial time combination, with produce be associated with each storage component part write test initial time.Write smooth circuit in the initiation time of writing of writing test period and be identified for described multiple storage component parts, wherein, for the each storage component part in described multiple storage component parts, what be associated with described each storage component part writes test initial time for providing signal writing test period, to be identified for the initiation time of writing of described each storage component part.In a form, Memory Controller also has clock signal terminal, and it is for providing memory clock signal to described multiple storage component parts.At the test period of writing of the initiation time of writing of the storage component part for determining described multiple storage component parts, what described Memory Controller use was associated with described storage component part writes test initial time, with the memory clock signal with respect to be provided to described storage component part at described clock signal terminal, being arranged in terminal in described multiple terminal provides the sequential of signal to described storage component part.In another form, be differential signal at the described signal of writing test period generation.In another form, Memory Controller has clock signal terminal, and it is for providing memory clock signal to described multiple storage component parts.At the test period of writing of the initiation time of writing of the storage component part for determining described multiple storage component parts, described Memory Controller use be associated with described storage component part described in write test initial time, with the described memory clock signal with respect to be provided to described storage component part at described clock signal terminal place, be arranged in the sequential of the first pulse in a series of at least one pulse that the terminal in described multiple terminal provides to described storage component part.In another form, Memory Controller has clock signal terminal, and it is for providing memory clock signal to described multiple storage component parts.Described Memory Controller uses the initiation time of writing for the storage component part of described multiple storage component parts, with the described memory clock signal with respect to be provided to described storage component part at described clock signal terminal place, be arranged in terminal place in described multiple terminal and be provided for to described storage component part the sequential of the data strobe signal of data writing.In another form, the storage component part in described multiple storage component parts being read to test with during determining read latency, described Memory Controller sends command signal and measures in the time delay receiving in the response that represents to receive by described storage component part described command signal.In another form, described Memory Controller also comprises the non volatile register of writing test initial time being associated with described primary memory device for storing.In another form, described multiple terminals comprise multiple data strobe terminals, and each data strobe terminal is for being coupled to the storage component part of described multiple storage component parts.In response to the command signal of reading test period, described Memory Controller receives instruction via described multiple data strobe terminals from described multiple storage component parts.Described Memory Controller provides signal for writing test on data strobe terminal, to determine the initiation time of writing, and during writing data into described multiple storage component part, described Memory Controller provides data strobe signal to described multiple storage component parts.
Term as used herein " coupling " is not intended to be limited to direct-coupling or mechanical couplings.Although herein described the present invention with reference to specific embodiment, can carry out various modifications and variations in the case of not departing from the scope of the present invention that appended claims sets forth.For example, can realize with various types of transistors the circuit of Memory Controller and storage component part, such as MOS(metal-oxide semiconductor (MOS)), bipolarity, GaAs, silicon-on-insulator (SOI) or other.Can carry out according to the requirement of application-specific the reducing amount of regulating power source voltage.Therefore, instructions and accompanying drawing will be considered to be illustrative rather than restrictive meaning, and all this class amendments are intended to be included within the scope of the invention.Any benefit, advantage of describing for the specific embodiment herein or solution of problem is not intended to be understood to be key, essential or necessary feature or the element that any claim or all authority require.
Term as used herein " one " is restricted to one or be greater than one.In addition, in claims, use should not be understood as that to infer such as the speech of " at least one " and " one or more " and introduce another claim element by indefinite article " " any specific rights requirement that comprises the claim element that this class is introduced into is limited to the invention that only contains such element, even comprise speech " one or more " or " at least one " and during such as the indefinite article of " " when same claim.For the use of definite article, like this equally.
Unless specialize, such as the term of " first " and " second " at random distinguishing the element of this term description.Therefore, these terms are not necessarily intended to represent that this element is aspect the time or otherwise priority ranking.
Claims (20)
1. for a method for operational store, comprising:
Carry out and read test for the each storage component part in multiple storage component parts, to produce the read latency time of the each storage component part in described multiple storage component part, wherein, described multiple storage component part comprises primary memory device and does not comprise the subset of the storage component part of described primary memory device, wherein, described subset comprises at least one storage component part, wherein, the described read latency time is to obtain by command signal being provided to described each storage component part and measuring the time receiving before signal from described each storage component part in response to described command signal,
For the each storage component part in described subset, the read latency time of each storage component part of the subset of the read latency time for described primary memory device and described storage component part is compared, to produce the differential delay for each storage component part of described subset;
For the each storage component part in described subset, by the differential delay addition of writing test initial time and described each storage component part of described primary memory device, write test initial time with what produce each storage component part in described subset;
For the each storage component part in described subset, test initial time with writing of the each storage component part in described subset and carry out the test of writing for described each storage component part, to produce the initiation time of writing for each storage component part of described subset.
2. method according to claim 1, also comprises:
With carrying out the test of writing for described primary memory device for writing test initial time described in described primary memory device, to produce the initiation time of writing of described primary memory device.
3. method according to claim 1, also comprises:
With writing the initiation time described in the each storage component part for described subset, the each storage component part in described subset is carried out to write operation.
4. method according to claim 1, wherein,
Initiate persond eixis the sequential of data strobe signal is provided by Memory Controller during described predetermined memory device is carried out to write operation for writing described in the predetermined memory device of described multiple storage component parts.
5. method according to claim 4, wherein,
Provide the sequential of described data strobe signal with respect to the memory clock signal being received by described predetermined memory device for writing initiation persond eixis described in described predetermined memory device.
6. method according to claim 1, wherein,
Each storage component part in described multiple storage component parts is carried out and read test and comprise: Memory Controller provides command signal to the each storage component part in described subset, and the each storage component part of test response in described command signal and from described subset receives the time before signal.
7. method according to claim 1, wherein,
For the each storage component part in described subset, the described test initial time of writing is indicated with respect to the memory clock signal that is provided to the each storage component part in described subset, is provided to the sequential of the signal of the each storage component part in described subset by Memory Controller.
8. method according to claim 1, wherein,
Each storer in described subset is carried out to write to test and comprise: Memory Controller provides a series of at least one pulse to the each storage component part in described subset, wherein, for writing the instruction of test initial time described in each storage component part of described subset with respect to the sequential of the first pulse in the described series of the memory clock signal that is provided to the each storage component part in described subset.
9. method according to claim 8, wherein,
Execution is write test and is comprised: the each storage component part in described subset provides about the instruction that receives pulse in the particular phases of described memory clock signal from described Memory Controller.
10. method according to claim 1, wherein,
Each storage component part in described multiple storage component part is characterized as being DRAM storage component part.
11. methods according to claim 1, wherein,
At least depend on poor between the length in the clock signal path between length and described Memory Controller and the described primary memory device in the clock signal path between the each storage component part in Memory Controller and described subset for the described read latency time of each storage component part of described subset.
12. methods according to claim 1, wherein,
By read described in carrying out in the storer of calibration mode test, described comparison, described addition execution and described in write the execution of test.
13. 1 kinds of Memory Controllers, comprising:
I/O circuit, described I/O circuit comprises the multiple terminals with multiple storage component part exchange signals;
Read calibration circuit, the described calibration circuit of reading is coupled to described I/O circuit, for according to the read latency of reading signal that test period receives from described multiple storage component parts and be identified for each storage component part of described multiple storage component parts, described multiple storage component part comprises primary memory device and does not comprise the set of at least one storage component part of described primary memory device, wherein, described read latency is to obtain by command signal being provided to described each storage component part and measuring the time receiving before signal from described each storage component part in response to described command signal,
Counting circuit, described in being coupled to, described counting circuit reads calibration circuit, for calculate described at least one storage component part set write test initial time, wherein, for the each storage component part in described set, described counting circuit is by the each storage component part in described set and definite read latency and the read latency of described primary memory device compare to determine delay difference, and the test initial time of writing being associated by described delay difference with described primary memory device is added, with produce be associated with the each storage component part in described set write test initial time, and
Write test circuit, the described test circuit of writing is coupled to described I/O circuit, for the initiation time of writing writing test period and determine described multiple storage component parts, wherein, for the each storage component part in described multiple storage component parts, what be associated with the each storage component part in described multiple storage component parts writes test initial time for providing signal writing test period, to be identified for the initiation time of writing of the each storage component part in described multiple storage component part.
14. Memory Controllers according to claim 13, also comprise:
Clock signal terminal, described clock signal terminal is used for providing memory clock signal to described multiple storage component parts,
Wherein, at the test period of writing of the initiation time of writing of the storage component part for determining described multiple storage component parts, described Memory Controller use be associated with described storage component part described in write test initial time, with the described memory clock signal with respect to be provided to described storage component part at described clock signal terminal place, being arranged in terminal place in described multiple terminal provides the sequential of signal to described storage component part.
15. Memory Controllers according to claim 13, wherein,
Differential signal at the described signal of writing test period generation.
16. Memory Controllers according to claim 13, also comprise:
Clock signal terminal, described clock signal terminal is used for providing memory clock signal to described multiple storage component parts,
Wherein, at the test period of writing of the initiation time of writing of the storage component part for determining described multiple storage component parts, described Memory Controller use be associated with described storage component part described in write test initial time, with the described memory clock signal with respect to be provided to described storage component part at described clock signal terminal place, being arranged in terminal place in described multiple terminal provides the sequential of the first pulse in a series of at least one pulse to described storage component part.
17. Memory Controllers according to claim 13, also comprise:
Clock signal terminal, described clock signal terminal is used for providing memory clock signal to described multiple storage component parts,
Wherein, described Memory Controller uses the initiation time of writing for the storage component part of described multiple storage component parts, with the described memory clock signal with respect to be provided to described storage component part at described clock signal terminal place, be arranged in terminal place in described multiple terminal and be provided for to described storage component part the sequential of the data strobe signal of data writing.
18. Memory Controllers according to claim 13, wherein,
The storage component part in described multiple storage component parts being read to test with during determining read latency, described Memory Controller sends command signal and measures the time delay in the response that receives the described storage component part of instruction and receive described command signal.
19. Memory Controllers according to claim 13, also comprise:
Non volatile register, described non volatile register for store be associated with described primary memory device write test initial time.
20. Memory Controllers according to claim 13, wherein,
Described multiple terminal comprises multiple data strobe terminals, each data strobe terminal is for being coupled to the storage component part of described multiple storage component parts, wherein, in response to the command signal of reading test period, described Memory Controller receives instruction via described multiple data strobe terminals from described multiple storage component parts, wherein, described Memory Controller provides signal for writing test on described multiple data strobe terminals, to determine the initiation time of writing, wherein, during writing data into described multiple storage component part, described Memory Controller provides data strobe signal to described multiple storage component parts.
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