CN102420931B - Full-frame-rate image processing method based on FPGA (Field Programmable Gate Array) - Google Patents
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Abstract
The invention discloses a full-frame-rate image processing method based on an FPGA (Field Programmable Gate Array), and the method is used for solving problems of poor real-time image processing capability and the like of the existing built-in system. The technical scheme of the method disclosed by the invention comprises the following steps of: firstly dividing an image processing procedure into multi-level process in sequence according to a specific application background; then designing a hardware logic circuit corresponding to each-level process in the FPGA by a convolution kernel processing technique based on pixel flow buffering and an image parameter extracting technique based on adjacent image frame correlation; and taking an effective pixel clock as a synchronous signal to simultaneously work by all levels of hardware logic circuits, when the newly generated pixels are subjected to first-step operation in a hardware logic circuit corresponding to the first-step process, simultaneously carrying out corresponding processes in logic circuits corresponding to other steps by pixels, and simultaneously carrying out a parallel piping processing structure forming a pixel flow by the multi-level image processing operations, thereby realizing the full-frame-rate process on image sequences.
Description
Technical field
The present invention relates to a kind of digital video image processing method, particularly a kind of full frame rate image processing method based on FPGA.
Background technology
Image technique is extensive application in various fields, but picture signal dimension height is handled needed computation complexity height to it.Therefore, at some the system handles real-time is required harsh Embedded Application occasion, image processing velocity often becomes the bottleneck that influences system accuracy and practicality.Field programmable gate array (FPGA) has field-programmable and reconfigurability, has stronger parallel processing capability.In the document of publishing, with FPGA as the image processing system of core, the speed that its image is handled, the flexibility of processing mode and can be improved greatly to the adaptability of different images algorithm.
Document " based on realtime graphic filtering and the edge detection method of FPGA; sensing technology journal; 2007; Vol.20 (3); p623-627 " discloses a kind of realtime graphic LoG template filtering and edge detection method based on FPGA, this method has taken full advantage of parallel mechanism and the interior abundant RAM resource of sheet of FPGA, adopt distributed algorithm, replace multiplying with look-up table, satisfied the pretreated requirement of image in the vision navigation system, but article does not provide and carries out image with its method and handle the actual treatment speed reach; And the method that the document proposes is at the realization of the specific image algorithm of specific system research in FPGA, not systematic proposition general or can be used for a class image processing algorithm based on image processing hardware logical design the realizations technology of FPGA and can guarantee the real-time of image processing simultaneously.
Summary of the invention
Poor to the processing capability in real time of image for overcoming existing embedded system, image processing algorithm is in the deficiency of FPGA is inner when realizing ununified design considerations that can be for reference, the invention provides a kind of full frame rate image processing method based on FPGA, at first according to specific application background specific image processing process is divided into the multistep treatment of sequencing; Then adopt based on the convolution kernel treatment technology of pixel stream buffering with based on the image parameter extractive technique of adjacent image frame correlation and in FPGA, design processing corresponding hardware logical circuits at different levels; The hardware logic electric circuit of all grades is that synchronizing signal is worked simultaneously with the valid pixel clock, when the pixel of new generation is handled when carrying out first step operation in the corresponding hardware logic electric circuit in the first step, there is pixel in the corresponding logical circuit of other steps, to handle accordingly simultaneously, multi-level images is handled the parallel flow water treatment structure that operation forms pixel stream simultaneously, realizes the full frame rate of image sequence is handled.
The technical solution adopted for the present invention to solve the technical problems: a kind of full frame rate image processing method based on FPGA is characterized in may further comprise the steps:
(a) image processing process is divided into a plurality of steps of sequencing, each step is called to be handled the one-level of image, the division of step is satisfied: a step process to all pixels can realize in the once traversal to image, and each grade image handle should computation complexity low, guarantee can finish and export in the finite time interval before next pixel input a step process of a pixel;
(b) according to the multistep treatment of being divided by step (a), design processing corresponding hardware logical circuits at different levels in FPGA, all application of logic circuit module are worked down synchronously simultaneously the valid pixel clock, each level logic circuit module is output as input with the upper level processing module, finishes respective stages and the result is outputed to the next stage module after to the processing of pixel; A pixel is finished under current valid pixel clock when the image of prime and is handled, and finishes next stage at next clock and handles until finishing all processing procedures; In image processor logic modular design, the difference of the task that processing will be finished according to each grade selects to adopt different treatment technologies;
Handle for the image that input picture and n * n neighborhood window need be done convolution, adopt the convolution kernel treatment technology based on the pixel stream buffering; Pixel buffer Buffer of design in application of logic circuit module, in order to store the needed neighborhood territory pixel of convolutional calculation, the Buffer degree of depth is (n-1) * W+n, wherein W is the horizontal resolution of image; When a pixel of previous stage processing module output enters when front module under the valid pixel clock is synchronous, at first it is buffered into Buffer, original pixel moves a position successively backward in the Buffer, and the pixel of rearmost position shifts out Buffer; Divide exactly with " | " expression, then will be by (n|2) * W+ (n+1) | the n * n neighborhood centered by 2 pixels is finished convolution algorithm one time according to convolution kernel, and operation result outputs to the next stage processing module; In descending synchronously of valid pixel clock, repeat said process, can realize the continuous convolution of pixel stream is handled;
Come the image of extracting parameter P to handle for needs according to the statistical property of whole two field picture, adopt the image parameter extractive technique based on the adjacent image frame correlation; And character that its time interval short strong according to correlation between the live video stream adjacent image frame, the parameter of utilizing the statistical law by former frame or former two field pictures to obtain estimates to be applicable to the algorithm parameter P of current frame image
c, to avoid the repeatedly traversal to image, it is mobile between image processing modules at different levels to guarantee that the continuous nothing of pixel stream stops; Order
Satisfy α
1+ α
2+ ...+α
n=1 and α
1＞a
2＞...＞α
n, wherein
Be this parameter of extracting according to preceding i two field picture statistical law, α
iIt is the image parameter of extracting according to preceding i two field picture statistical law
Associated weight coefficient to the present frame parameter; The synchronous parameter P that uses down at the valid pixel clock
cIn the time of to current input processes pixel, the input pixel of handling when prime is added up according to the required requirement of calculating parameter P, after two field picture input is finished, calculate and produce
The parameter Estimation that is used for the next frame image;
(c) with the input of original image as first order processing module, the input and output of other application of logic circuit module connect successively, and the output of afterbody processing module is as the output of entire image processing process; The image processor logic of all grades is worked down synchronously simultaneously global clock, formation is to the parallel flow water treatment structure of input pixel stream, make in the finite time interval that the pixel of a two field picture is imported fully, finish all images processing procedure to current frame image, thereby realize the full frame rate of image sequence is handled.
The invention has the beneficial effects as follows: under the situation that guarantees higher global clock frequency, can reach identical with the frame per second of image input to the processing speed of image sequence; Employing can conveniently design the hardware logic electric circuit of a class image processing algorithm or its combination in any and can guarantee that it is applicable to based on the convolution kernel treatment technology of pixel stream buffering with based on the image parameter extractive technique of adjacent image frame correlation the full frame rate of image sequence is handled.
Below in conjunction with drawings and Examples the present invention is elaborated.
Description of drawings
Fig. 1 is that multi-level images of the present invention is handled the parallel and pipeline structure schematic diagram;
Fig. 2 is the convolution kernel treatment technology schematic diagram that the present invention is based on the pixel stream buffering;
Fig. 3 is the image parameter extractive technique parameter generating schematic block diagram that the present invention is based on the adjacent image frame correlation;
Fig. 4 is that the full frame rate of Canny operator of the present invention is handled implementation structure figure;
Fig. 5 is the hardware realization figure that the Canny operator first order of the present invention is handled;
Fig. 6 is the hardware realization figure that handle the Canny operator of the present invention second level;
Fig. 7 is the hardware realization figure that the Canny operator third level of the present invention is handled;
Fig. 8 is the hardware realization figure of Canny operator dual threshold parameter generation module of the present invention;
Fig. 9 is the hardware realization figure that the Canny operator fourth stage of the present invention is handled.
Embodiment
With reference to Fig. 1～9, present embodiment is at certain type gray scale array image sensor, and image resolution ratio 720*576, pixel precision are 8, and frame per second 25 frames are handled realization to the full frame rate of Canny edge detection algorithm in FPGA of its image sequence, describe the present invention in detail.Concrete steps are as follows:
The first step according to the algorithmic procedure of Canny rim detection, is divided into the level Four processing procedure with algorithm; The first order is carried out the gaussian filtering operation to the input pixel stream; The second level adopts a kind of gradient operator that the rim detection operation is carried out in the output of gaussian filtering, the amplitude of compute gradient and direction, and present embodiment is selected the Sobel operator; The non-maximum that the third level carries out neighborhood according to the power of pixel gradient suppresses, and eliminates pseudo-edge; The fourth stage adopts the dual threshold method to detect and is connected the edge;
In second step, the design level Four is handled the corresponding hardware logical circuit in FPGA;
Handle for first order gaussian filtering, by Gauss's mask convolution of input picture and one 3 * 3 is realized; Kernel function K
1Be expressed as:
K
1＝1/16[1?2?1；2?4?2；1?2?1]
Employing is based on the convolution kernel treatment technology of pixel stream buffering, design a degree of depth and be 1443 Buffer, when a new pixel is imported when front module, original pixel in the Buffer is moved a position successively backward, the address is that the pixel of 1442 positions shifts out Buffer, and the address that then current pixel is deposited in Buffer is 0 position; The address is that 3 * 3 neighborhoods centered by 721 the pixel are with Gaussian kernel K in buffering area
1Do convolution, according to the characteristics of this convolution kernel, convolution algorithm can be by carrying out the pixel of 0,1,2,720,721,722,1440,1441,1442 positions among the Buffer corresponding displacement and the realization that adds up; Convolution results outputs to next stage, and repeats aforesaid operations when next efficient clock arrives; Hardware in its FPGA is realized as shown in Figure 5;
For second level Sobel rim detection, by the result images of previous stage output and two 3 * 3Sobel operators of level and vertical direction are done the convolution realization respectively; Convolution kernel is respectively:
K
h＝[-1?-2?-1；0?0?0；1?2?1]；K
v＝[-1?0?1；-2?0?2；-1?0?1]
Employing is based on the convolution kernel treatment technology of pixel stream buffering, design a degree of depth and be 1443 Buffer, when a new pixel is imported when front module, original pixel in the Buffer is moved a position successively backward, the address is that the pixel of 1442 positions shifts out Buffer, and the address that then current pixel is deposited in Buffer is 0 position; The address is the same K of 3 * 3 neighborhoods centered by 721 the pixel in buffering area
hAnd K
vDo convolution respectively, convolution results represents that with 9 binary digits highest order represents the subtraction direction, and 0 is that forward is poor, and 1 is reverse poor; The convolution results of both direction outputs to next stage simultaneously; When arriving, repeats next efficient clock aforesaid operations; The hardware of this module is realized as shown in Figure 6;
Suppress operation for the non-maximum of the third level, the both direction Grad of same pixel according to previous stage output need be compared, find out prevailing gradient direction, and judge along leading gradient direction whether current Grad is maximum in its 3 * 3 neighborhood; When the design of this level logic circuit, the same convolution kernel treatment technology that adopts based on the pixel stream buffering design two degree of depth and is 1443 Buffer, distinguishes Grad and the direction of buffer memory both direction; When a new valid pixel clock arrives, original pixel in two Buffer is moved a position successively backward, the address is that the pixel of 1442 positions shifts out Buffer, and the address that then the both direction gradient of current arrival is deposited in corresponding Buffer respectively is 0 position; The excursion of gradient angle is reduced into { 0-45 °, 180 °-225 ° }, { 45 °-90 °, 225 °-270 ° }, { 90 °-135 °, 270 °-315 ° }, { 135 °-180 °, 315 °-360 ° } one of four sectors, relatively the value of 721 positions is determined leading differential direction among two Buffer, finally determines sector under the gradient direction in conjunction with its sign bit; Judge that at gradient direction whether this center pixel Grad is maximum for the part in 3 * 3 neighborhoods, if then this Grad is outputed to next stage, otherwise exports 0; At next valid pixel clock along repeating aforesaid operations; The hardware of this module is realized as shown in Figure 7;
Determine the edge for fourth stage dual threshold method, need obtain two threshold values according to the statistics accumulation histogram of filtered image, if the response of picture signal greater than high threshold, it is the edge so; If be lower than low threshold value, it is the edge scarcely so; If fall between, judge whether it has by being higher than low threshold value to link the path that is higher than high threshold point that the words that have are the edge, otherwise are not the edge in 3 * 3 neighborhoods; When the design of this level logic circuit, to combine based on the convolution kernel treatment technology of pixel stream buffering with based on the image parameter extractive technique of adjacent image frame correlation, adopt back one Technology design, one threshold value generation module, accumulation histogram statistics according to the former frame image, the gray scale of getting its 70% correspondence is high threshold Hth, low threshold value Lth is decided to be half of high threshold, and these two threshold values are determined as the edge that parameter is used for present frame; Simultaneously the pixel stream of present frame input is carried out the accumulation histogram statistics, design a degree of depth and be 256 memory block, preserve the number of pixels counting of corresponding grey scale level respectively, the statistics with present frame after the current frame image input is finished recomputates Hth and the Lth that generation is applicable to the next frame image; Repeating this process just can the real-time update segmentation threshold and do not influence the full frame rate of image is handled; The hardware structure of threshold value generation module as shown in Figure 8;
Adopting degree of depth of last Technology design is 1443 Buffer, when a new pixel is imported, original pixel in the Buffer is moved a position successively backward, and the address is that the pixel of 1442 positions shifts out Buffer, and the address that then current pixel is deposited in Buffer is 0 position; When determining the edge, if in the current buffering area address be 721 Grad greater than the Hth of present frame, then export 255 (8 complete 1), if less than the Lth of present frame, then export 0; If between between the two, judge that then the address is 0,1,2,720 in the buffering area, whether 8 its Grad of position of 722,1440,1441,1442 have greater than Hth's, if have, illustrating in current center pixel 8 neighborhoods has the point that is defined as the edge, and then putting its value is 255, otherwise is set to 0; The hardware structure of this processing module as shown in Figure 9; When each valid pixel clock changes, repeat aforesaid operations, when a two field picture end of output, just finished the Canny rim detection to it simultaneously, and can realize the full frame rate of input image sequence is handled.
Claims (1)
1. full frame rate image processing method based on FPGA is characterized in that may further comprise the steps:
(a) image processing process is divided into a plurality of steps of sequencing, each step is called to be handled the one-level of image, the division of step is satisfied: a step process to all pixels can realize in the once traversal to image, and each grade image handle should computation complexity low, guarantee can finish and export in the finite time interval before next pixel input a step process of a pixel;
(b) according to the multistep treatment of being divided by step (a), design processing corresponding hardware logical circuits at different levels in FPGA, all application of logic circuit module are worked down synchronously simultaneously the valid pixel clock, each level logic circuit module is output as input with the upper level processing module, finishes respective stages and the result is outputed to the next stage module after to the processing of pixel; A pixel is finished under current valid pixel clock when the image of prime and is handled, and finishes next stage at next clock and handles until finishing all processing procedures; In image processor logic modular design, the difference of the task that processing will be finished according to each grade selects to adopt different treatment technologies;
Handle for the image that input picture and n * n neighborhood window need be done convolution, adopt the convolution kernel treatment technology based on the pixel stream buffering; Pixel buffer Buffer of design in application of logic circuit module, in order to store the needed neighborhood territory pixel of convolutional calculation, the Buffer degree of depth is (n-1) * W+n, wherein W is the horizontal resolution of image; When a pixel of previous stage processing module output enters when front module under the valid pixel clock is synchronous, at first it is buffered into Buffer, original pixel moves a position successively backward in the Buffer, and the pixel of rearmost position shifts out Buffer; Divide exactly with " | " expression, then will be by (n|2) * W+ (n+1) | the n * n neighborhood centered by 2 pixels is finished convolution algorithm one time according to convolution kernel, and operation result outputs to the next stage processing module; In descending synchronously of valid pixel clock, repeat said process, can realize the continuous convolution of pixel stream is handled;
Come the image of extracting parameter P to handle for needs according to the statistical property of whole two field picture, adopt the image parameter extractive technique based on the adjacent image frame correlation; And character that its time interval short strong according to correlation between the live video stream adjacent image frame, the parameter of utilizing the statistical law by former frame or former two field pictures to obtain estimates to be applicable to the algorithm parameter P of current frame image
c, to avoid the repeatedly traversal to image, it is mobile between image processing modules at different levels to guarantee that the continuous nothing of pixel stream stops; Order
Satisfy a
1+ a
2+ ...+a
n=1 and a
1A
2... a
n, wherein
Be this parameter of extracting according to preceding i two field picture statistical law, a
iIt is the image parameter of extracting according to preceding i two field picture statistical law
Associated weight coefficient to the present frame parameter; The synchronous parameter P that uses down at the valid pixel clock
cIn the time of to current input processes pixel, the input pixel of handling when prime is added up according to the required requirement of calculating parameter P, after two field picture input is finished, calculate and produce
The parameter Estimation that is used for the next frame image;
(c) with the input of original image as first order processing module, the input and output of other application of logic circuit module connect successively, and the output of afterbody processing module is as the output of entire image processing process; The image processor logic of all grades is worked down synchronously simultaneously global clock, formation is to the parallel flow water treatment structure of input pixel stream, make in the finite time interval that the pixel of a two field picture is imported fully, finish all images processing procedure to current frame image, thereby realize the full frame rate of image sequence is handled.
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| US9749548B2 (en) | 2015-01-22 | 2017-08-29 | Google Inc. | Virtual linebuffers for image signal processors |
| GB201607713D0 (en) * | 2016-05-03 | 2016-06-15 | Imagination Tech Ltd | Convolutional neural network |
| CN106447596A (en) * | 2016-09-30 | 2017-02-22 | 深圳云天励飞技术有限公司 | Data stream control method in image processing |
| CN107507125B (en) * | 2017-08-31 | 2021-06-29 | 郑州云海信息技术有限公司 | Method and system for generating Alpha channel palette in WebP image compression and host |
| CN108154229B (en) * | 2018-01-10 | 2022-04-08 | 西安电子科技大学 | Image processing method based on FPGA (field programmable Gate array) accelerated convolutional neural network framework |
| CN108932129A (en) * | 2018-06-26 | 2018-12-04 | 郑州云海信息技术有限公司 | A kind of acceleration system and method for WebP cataloged procedure medium entropy encryption algorithm |
| CN110070557A (en) * | 2019-04-07 | 2019-07-30 | 西北工业大学 | A kind of target identification and localization method based on edge feature detection |
| CN113365101B (en) * | 2020-03-05 | 2023-06-30 | 腾讯科技（深圳）有限公司 | Method for multitasking video and related equipment |
| CN112529763B (en) * | 2020-12-16 | 2024-06-21 | 航天科工微电子系统研究院有限公司 | Image processing system and tracking system based on soft and hard coupling |
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