CN102412312A - MOS transistor capacitor - Google Patents

Abstract

The invention discloses an MOS transistor capacitor, belonging to the integrated circuit technology field. The capacitor comprises a P type body region, an n+ source region, an n+ drain region, a thin gate oxide layer which is attached to the P type body region, and a polysilicon gate which is attached to the thin gate oxide layer. The n+ source region and the n+ drain region are respectively connected to the P type body region. According to the capacitor, a capacitance value of the MOS transistor capacitor on unit area is increased. Simultaneously, the invention also discloses a memory cell applying the MOS transistor capacitor. The memory cell can decrease influence of a single event upset effect.

Description

A kind of MOS transistor electric capacity

Technical field

The present invention relates to technical field of integrated circuits, particularly a kind of based on the MOS transistor electric capacity under the partial depletion SOI CMOS technology.

Background technology

In the prior art, the redundancy that relates to when stored information is carried out redundant the preservation can be based on feedback mechanism, also can be based on the upset time-delay that increases node.

Can adopt the multitube monotechnics that comprises ten pipe units, ten two transistor cells etc. that stored information is carried out redundancy preserves.Its advantage is; When employing is carried out the redundancy preservation based on the multitube monotechnics of feedback mechanism to stored information; If the information of one of them memory node is overturned, can carry out fast quick-recovery to the information that this quilt is overturned based on the memory node of the multitube monotechnics of feedback mechanism; When employing is carried out the redundancy preservation based on the upset delay technique that increases node to stored information; If the information of one of them memory node is overturned; Because the increase of node and the time-delay of upset recover the stored information of having overturn the information of carrying out based on the upset delay technique that increases node if having time.Its shortcoming is that memory cell area is big, and the write time is long.

Can also be employed in the method that adds coupling capacitance between complementary storage node stored information is carried out the redundancy preservation.Its advantage is; After the information flip of one of them memory node, under the effect of this coupling capacitance, with the corresponding anti-phase memory node of the memory node information after this upset can take place with this upset after the equidirectional saltus step of memory node; Thereby, can weaken the single-particle inversion effect.Its shortcoming is, produces because this coupling capacitance need be produced or inserted the finger metal by multilayer by parasitic capacitance.Produced by parasitic capacitance in the method for this coupling capacitance, processing step is complicated, and the unit-area capacitance value is little; Inserted in the method that refers to this coupling capacitance of metal generation by multilayer, mim structure unit of capacity area capacitance value is little, and the coupling capacitance of generation is little.These factors have all restricted the effect of the anti-single particle overturn effect of the method that between complementary storage node, adds coupling capacitance.

Summary of the invention

In order to address the above problem, the present invention proposes a kind of MOS transistor electric capacity that can increase the unit-area capacitance value.

And, the invention allows for a kind of memory cell of using this MOS transistor electric capacity.

MOS transistor electric capacity provided by the invention comprises P type tagma, n ⁺The source region, n ⁺The drain region is attached to the thin grid oxygen on the said P type tagma, and, be attached to the polysilicon gate above the said thin grid oxygen, said n ⁺Source region and n ⁺The drain region is connected to said P type tagma.

As preferably, the sidewall in said P type tagma is wrapped up by STI, and the bottom in said P type tagma is attached with oxide layer, and said oxide layer bottom is attached with substrate, makes that the P type tagma of each MOS transistor all is independently.

The application that the present invention proposes the memory cell of above-mentioned MOS transistor electric capacity comprise 4 nmos pass transistor N ₁, N ₂, N ₃, N ₄, 2 PMOS transistor P ₁, P ₂With 1 said electric capacity,

Said transistor N ₁With N ₂Cross-couplings connects, said transistor P ₁With P ₂Cross-couplings connects, said transistor P ₁Drain electrode and said transistor N ₁Drain electrode link to each other, constitute the I memory node, said transistor P ₂Drain electrode and said transistor N ₂Drain electrode link to each other, constitute the II memory node, said I memory node and said II memory node constitute the memory node of complementation, said transistor N ₁Source electrode and N ₂Source electrode ground connection respectively, said transistor P ₁Source electrode and P ₂Source electrode connect power supply respectively,

The grid of said electric capacity is connected in said transistor P ₁Grid and said transistor N ₁Grid between, the source region of said electric capacity, drain region, tagma link to each other, the source region of said electric capacity, drain region, tagma all are connected in said transistor P ₂Grid and said transistor N ₂Grid between,

Said transistor N ₃Source electrode be connected in said transistor P ₁Drain electrode and said transistor N ₁Drain electrode between, said transistor N ₃Drain electrode be connected in bit line BL, said transistor N ₄Source electrode be connected in said P ₂Drain electrode and said transistor N ₂Drain electrode between, said transistor N ₄Drain electrode be connected in bit line BLB,

Control signal WL is respectively from said transistor N ₃And N ₄Grid input.

The beneficial effect of MOS transistor electric capacity provided by the invention is:

Because P type tagma, the n of MOS transistor electric capacity provided by the invention ⁺Source region and n ⁺The drain region is the both-end BTS structure of under partial depletion SOI CMOS process conditions, processing, n ⁺Source region and n ⁺The drain region is connected to P type tagma, no matter is in cut-off region, depletion region or inversion regime, and the capacitance of this MOS transistor electric capacity all is slightly larger than WLC _OxThereby,, increased the capacitance of MOS transistor electric capacity on unit are.

Use the memory cell of above-mentioned MOS transistor electric capacity, I memory node and said II memory node constitute complementary memory node, and the grid of MOS transistor electric capacity provided by the invention is connected in transistor P ₁Grid and transistor N ₁Grid between, the source region of electric capacity, drain region, tagma link to each other, the source region of electric capacity, drain region, tagma all are connected in transistor P ₂Grid and transistor N ₂Grid between; Thereby; Electric capacity constitutes a coupling capacitance between the memory node of above-mentioned complementation, when one of them memory node because single particle effect generation saltus step the time, because the effect of this electric capacity; Equidirectional saltus step also takes place in another complementary memory node, thereby can weaken the influence of single-particle inversion effect.

Description of drawings

The stereogram of the MOS transistor electric capacity that Fig. 1 provides for the embodiment of the invention;

The sectional arrangement drawing of the MOS transistor electric capacity that Fig. 2 provides for the embodiment of the invention;

The domain of the MOS transistor electric capacity that Fig. 3 provides for the embodiment of the invention;

The application that Fig. 4 provides for the embodiment of the invention memory cell of this MOS transistor electric capacity;

Fig. 5 for the application that provides in the embodiment of the invention oscillogram of the exciting current that produces of the I memory node simulation single-particle inversion of memory cell of this MOS transistor electric capacity;

The application that Fig. 6 provides for the embodiment of the invention memory cell of this MOS transistor electric capacity behind the exciting current that I memory node simulation single-particle inversion produces, the voltage oscillogram of I memory node and II memory node.

Embodiment

In order to understand the present invention in depth, the present invention is elaborated below in conjunction with accompanying drawing and specific embodiment.

Referring to accompanying drawing 1 and accompanying drawing 2, MOS transistor electric capacity provided by the invention comprises P type tagma 6, n ⁺Source region 1, n ⁺Drain region 2 is attached to the thin grid oxygen 4 on the P type tagma, and, be attached to the polysilicon gate 3 above the thin grid oxygen 4, P type tagma 6, n ⁺Source region 1 and n ⁺Drain region 2 is both-end BTS structures of under partial depletion SOI CMOS process conditions, processing, makes n ⁺Source region 1 and n ⁺Drain region 2 is connected to P type tagma 6.

Wherein, be used to realize that a kind of mode of technique scheme is, the sidewall in P type tagma 6 is wrapped up by STI5, and the bottom in P type tagma 6 is attached with oxide layer 7, and oxide layer 7 bottoms are attached with substrate 8, make that the P type tagma 6 of each MOS transistor all is independently.

Because P type tagma 6, the n of MOS transistor electric capacity provided by the invention ⁺Source region 1 and n ⁺Drain region 2 is both-end BTS structures of under partial depletion SOI CMOS process conditions, processing, n ⁺Source region 1 and n ⁺Drain region 2 is connected to P type tagma 6, no matter is in cut-off region, depletion region or inversion regime, and the capacitance of this MOS transistor electric capacity all is slightly larger than WLC _OxThereby,, increased the capacitance of MOS transistor electric capacity on unit are.

Referring to accompanying drawing 1 and accompanying drawing 3, the n of the MOS transistor that provides at present embodiment ⁺Source region 1 and n ⁺Be respectively equipped with two contact holes 9 on the drain region 2, in accompanying drawing 3, frame of broken lines 10 expression n ⁺Inject frame, dot-dash wire frame 11 expression p ⁺Inject frame.

Referring to accompanying drawing 4, the application that the present invention proposes the memory cell of above-mentioned MOS transistor electric capacity comprise 4 nmos pass transistor N ₁, N ₂, N ₃, N ₄, 2 PMOS transistor P ₁, P ₂The MOS transistor electric capacity 12 that provides with 1 present embodiment,

Transistor N ₁With N ₂Cross-couplings connects, transistor P ₁With P ₂Cross-couplings connects, transistor P ₁Drain electrode and transistor N ₁Drain electrode link to each other, constitute the I memory node, transistor P ₂Drain electrode and transistor N ₂Drain electrode link to each other, constitute the II memory node, I memory node and II memory node constitute the memory node of complementation, transistor N ₁Source electrode and N ₂Source electrode ground connection respectively, transistor P ₁Source electrode and P ₂Source electrode connect power supply respectively,

The grid of electric capacity 12 is connected in transistor P ₁Grid and transistor N ₁Grid between, the source region of electric capacity 12, drain region, tagma link to each other, the source region of electric capacity 12, drain region, tagma all are connected in transistor P ₂Grid and transistor N ₂Grid between,

Transistor N ₃Source electrode be connected in transistor P ₁Drain electrode and transistor N ₁Drain electrode between, transistor N ₃Drain electrode be connected in bit line BL, transistor N ₄Source electrode be connected in P ₂Drain electrode and transistor N ₂Drain electrode between, transistor N ₄Drain electrode be connected in bit line BLB,

Control signal WL is respectively from transistor N ₃And N ₄Grid input.

In this memory cell, I memory node and said II memory node constitute complementary memory node, and the grid of MOS transistor electric capacity 12 provided by the invention is connected in transistor P ₁Grid and transistor N ₁Grid between, the source region of electric capacity 12, drain region, tagma link to each other, the source region of electric capacity 12, drain region, tagma all are connected in transistor P ₂Grid and transistor N ₂Grid between, thereby electric capacity 12 constitutes a coupling capacitance 12 between the memory node of above-mentioned complementation; When one of them memory node because single particle effect generation saltus step the time; Because the effect of this electric capacity 12, when exciting current that the single-particle inversion at I memory node simulation waveform shown in accompanying drawing 5 of this memory cell produces, the voltage oscillogram of this I memory node and this II memory node is shown in accompanying drawing 6; Can find out from accompanying drawing 6; Equidirectional saltus step also takes place in the II memory node complementary with this I memory node, thereby, can weaken the influence of single-particle inversion effect.

Above embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, the above embodiment of the present invention that is merely that it should be understood that; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (3)

1. a MOS transistor electric capacity comprises P type tagma, n ⁺The source region, n ⁺The drain region is attached to the thin grid oxygen on the said P type tagma, and, be attached to the polysilicon gate above the said thin grid oxygen, it is characterized in that said n ⁺Source region and n ⁺The drain region is connected to said P type tagma.

2. electric capacity according to claim 1 is characterized in that, the sidewall in said P type tagma is wrapped up by STI, and the bottom in said P type tagma is attached with oxide layer, and said oxide layer bottom is attached with substrate, makes that the P type tagma of each MOS transistor all is independently.

3. the memory cell based on claim 1 or 2 described MOS transistor electric capacity is characterized in that, comprises 4 nmos pass transistor N ₁, N ₂, N ₃, N ₄, 2 PMOS transistor P ₁, P ₂With 1 claim 1 or 2 described electric capacity,

Said transistor N ₁With N ₂Cross-couplings connects, said transistor P ₁With P ₂Cross-couplings connects, said transistor P ₁Drain electrode and said transistor N ₁Drain electrode link to each other, constitute the I memory node, said transistor P ₂Drain electrode and said transistor N ₂Drain electrode link to each other, constitute the II memory node, said I memory node and said II memory node constitute the memory node of complementation, said transistor N ₁Source electrode and N ₂Source electrode ground connection respectively, said transistor P ₁Source electrode and P ₂Source electrode connect power supply respectively,

The grid of said electric capacity is connected in said transistor P ₁Grid and said transistor N ₁Grid between, the source region of said electric capacity, drain region, tagma link to each other, the source region of said electric capacity, drain region, tagma all are connected in said transistor P ₂Grid and said transistor N ₂Grid between,

Said transistor N ₃Source electrode be connected in said transistor P ₁Drain electrode and said transistor N ₁Drain electrode between, said transistor N ₃Drain electrode be connected in bit line BL, said transistor N ₄Source electrode be connected in said P ₂Drain electrode and said transistor N ₂Drain electrode between, said transistor N ₄Drain electrode be connected in bit line BLB,

Control signal WL is respectively from said transistor N ₃And N ₄Grid input.

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