CN102411987B - Memory device and from deinterleaving method - Google Patents

Abstract

A kind of memory device includes: memory cell array；From interleaver, it is configured so that data are interweaved and are loaded in buffer circuits by interleaving scheme immediately；And control logic, it is configured to control the programming of interleaving data in memory cell array.

Description

Memory device and from deinterleaving method

Technical field

The disclosure refers here to semiconductor memory, and more particularly, to using the storage of interleaving scheme Device.

Background technology

Generally, semiconductor storage unit is categorized as such as dynamic random access memory (DRAM) and quiet The volatile memory of state random access memory (SRAM) and such as electrically erasable Read memorizer (EEPROM), ferroelectric RAM (FRAM), phase-change random access storage Device (PRAM), magnetoresistive RAM (MRAM) and the non-volatile of flash memory are deposited Reservoir.Volatile memory loses the data of storage when the power is stopped, but nonvolatile memory is i.e. Also the data of storage are maintained when making to stop power supply.Specifically, flash memory has high program speed, low Power consumption and the advantage of mass data storage.Therefore, including flash memory flash memory system just It is widely used as data storage medium.

Flash memory can store 1 Bit data or 2 bits or more bit in a memory element Data.Generally, the memory element storing 1 Bit data is called single level-cell (SLC), and stores 2 The memory element of bit or more multi-bit data is called multi-level-cell (MLC).SLC has according to threshold The erasing state of voltage and programming state.MLC has the erasing state according to starting voltage and multiple programming State.

In the flash memory (hereinafter referred to as MLC flash memory) with multi-level-cell, Multiple logical page (LPAGE)s can be stored in the memory element (hereinafter referred to as Physical Page) of a shared wordline. Here, each logical page (LPAGE) can have different bit error rates (BER).If it is assumed that failure bit Quantity identical in each reading level, then N-bit MLC flash memory can in each logical page (LPAGE) To have 1: 2: 2²∶...∶2^N-1BER.

Summary of the invention

Example embodiment provides memory device.Described memory device may include that memory cell array；From Interleaver, is configured so that data are interweaved and are loaded in buffer circuits by interleaving scheme immediately；And Control logic, be configured to control the programming of interleaving data in memory cell array.

In certain embodiments, control logic can include from interleaver.

In certain embodiments, data can be from memory device external reception.

In certain embodiments, memory cell array can include multiple Physical Page, and each Physical Page can Store multiple logical page (LPAGE)；Can be configured to each logical page (LPAGE) is divided into multiple sector from interleaver, and And perform interleaving scheme by mixing the sector of each Different Logic page；And control logic and can control The programming of the logical page (LPAGE) of the multiple mixing in the Physical Page of memory cell array.

In certain embodiments, buffer circuits can store data by sector.

In certain embodiments, buffer circuits can include multiple page buffer, and it is in response to from selfing Knit the enable signal of device output and select signal to store each sector.

In certain embodiments, each page buffer can include multiple latch, each responsive In from corresponding selection signal one bit of storage enabling signal and correspondence exported from interleaver.

In certain embodiments, can be configured to data interlacing and adding in units of sector from interleaver It is downloaded in buffer circuits.

In certain embodiments, this memory device may further include: column select circuit, selects buffering The page buffer of device circuit；And data buffer, provide to column select circuit and connect outside memory device The data received.

In certain embodiments, can be configured to control buffer circuits and column select circuit from interleaver Interweave and loading data.

In certain embodiments, data can come from the source page of memory cell array, and control logic can To be configured with the programming controlling interleaving data to the page object in memory cell array that interweaves.

In certain embodiments, can be configured to sequentially by the n-bit number from source page from interleaver According in the page 1 buffer being stored in buffer circuits, transmission source page data to data buffer, and Source page data is interweaved immediately from page 1 buffer and is loaded into n latch.

In certain embodiments, can be configured to will be stored in buffering from the data of source page from interleaver In device circuit, the external circuit of transmission source page data to memory device, this circuit processes source number of pages further According to, and source page data is interweaved immediately from this external circuit and is loaded into buffer circuits, and control Interleaving data processed is to the programming of the page object of memory cell array.

In certain embodiments, can be configured to by the data from source page with from storage from interleaver The data of device exterior are stored in buffer circuits, and the data by source page data with from outside are Time interweave and be loaded in buffer circuits, and control interleaving data to the page object of memory cell array Programming.

In certain embodiments, the multiple logical page (LPAGE)s being stored in buffer circuits can be same by total state Time programming scheme program.

In certain embodiments, the size of each sector can be configured to determine that from interleaver.

In certain embodiments, interleaving data can have the average bit error rate equal to multiple sectors Bit error rate.

In certain embodiments, each Physical Page can be divided into main region and spare area.

In certain embodiments, memory cell array can have three dimensional structure.

In certain embodiments, memory cell array can be flash memory storage unit array.

Example embodiment provides storage system.Described storage system may include that the storage according to embodiment Device；And storage control, control the operation of this memory device.

In certain embodiments, storage system can be SOC(system on a chip).

In certain embodiments, storage system can include error-correcting code circuit.

In certain embodiments, error-correcting code circuit can be a part for storage control.

In certain embodiments, error-correcting code circuit can separate with storage control.

In certain embodiments, error-correcting code circuit can be designed for will being stored in memory cell array The average bit error rate of logical page (LPAGE).

In certain embodiments, storage system may include that main frame；And communication equipment, it is configured to Main frame and the swapping data of memory device.

In certain embodiments, storage system can include multiple memory device.

In certain embodiments, memory device can be a part for storage card.

In certain embodiments, memory device can be a part for solid-state drive.

In certain embodiments, memory device can be flash memory.

Example embodiment provides the electronic equipment including the storage system according to embodiment.

Example embodiment provides the method for operation memory device.Described method may include that reception data； Interleaving scheme is used the data of reception immediately to be interweaved and be loaded in buffer circuits；And at memorizer The memory cell array of part programs interleaving data.

In certain embodiments, receive data can include from memory device external reception data.

In certain embodiments, receive data can include from memory device internal receipt data.

In certain embodiments, receive data and can include that the source page from memory cell array receives data, And program the page object that can include being programmed in memory cell array interleaving data.

In certain embodiments, receive data can include from the source page of memory cell array receive data with And from memory device external reception data, wherein, interweave and load include mix from source page data and From outside data, wherein programming includes the target being programmed in memory cell array by interleaving data Page.

In certain embodiments, interweave and load and may include that the data ruler determining the sector that will interweave Very little, the logical page (LPAGE) will being stored in memory cell array is divided into multiple sector, and mixes difference The sector of logical page (LPAGE).

In certain embodiments, the bit error rate of interleaving data can be equal to the average bit of multiple sectors Error rate.

In certain embodiments, described method can include, before programming, it is determined whether total data Already loaded into buffer circuits.

In certain embodiments, when total data is already loaded into buffer circuits, programming can be wrapped Include use total state programming scheme simultaneously.

In certain embodiments, when total data is not yet loaded into buffer circuits, the method is permissible Including repeating to receive and interweave and load step.

In certain embodiments, the method can utilize flash memory storage unit array to use.

Accompanying drawing explanation

By being described in detail with reference to the attached drawings example embodiment, above and other feature and advantage will be to this area Those of ordinary skill become more apparent upon, wherein:

Fig. 1 explanation is according to the block diagram of the storage system of embodiment；

The block diagram of the flash memory of Fig. 2 explanatory diagram 1；

The circuit diagram of memory block BLK1 of Fig. 3 explanatory diagram 1；

The distribution of threshold voltages of the memory element of Fig. 4 to 7 explanatory diagram 3；

Fig. 8 illustrates the block diagram from the operation that interweaves of 2 bit MLC flash memory；

Certainly the operation that interweaves of 2 bit MLC flash memory of Fig. 9 explanatory diagram 8；

The block diagram from the operation that interweaves of Figure 10 and 11 explanation 4 bit MLC flash memory；

The flow chart from the operation that interweaves of the storage system of Figure 12 explanatory diagram 1；

The block diagram returning copy (copyback) intertexture operation certainly of the flash memory of Figure 13 explanatory diagram 1；

Figure 14 illustrates the flow chart returning copy intertexture operation certainly of the flash memory of Figure 13；

Figure 15 illustrates the block diagram performing back copy from the storage system of the operation that interweaves；

Figure 16 illustrates the flow chart returning copy intertexture operation certainly of the storage system of Figure 15；

Figure 17 explanation is according to the block diagram when being applied to three-dimensional flash memory from deinterleaving method of embodiment；

Figure 18 illustrates the perspective view of the three dimensional structure of memory block BLK1 of Figure 17；

Figure 19 illustrates the equivalent circuit figure of memory block BLK1 of Figure 17；

Figure 20 illustrates the concept map of the planar structure of the equivalent circuit figure of Figure 19；

Figure 21 explanation is according to the figure of the flash memory system being applied to storage card of embodiment；

Figure 22 explanation is according to the block diagram when storage system applications to SSD of embodiment；

Figure 23 illustrates the block diagram of the configuration of the SSD controller 4210 of Figure 22；And

Figure 24 explanation is according to the block diagram when utilizing electronic equipment to realize flash memory system of embodiment.

Detailed description of the invention

It is described more fully below example embodiment below in reference to accompanying drawing, but, they can be with different shapes Formula realizes, and is not to be read as being limited to embodiments set forth here.On the contrary, it is provided that these embodiments So that the disclosure is clear complete for a person skilled in the art, and pass on the scope of the present invention comprehensively.

I. the flash memory system from interleaver is included

Fig. 1 explanation is according to the block diagram of the storage system of embodiment.With reference to Fig. 1, storage system 1000 is permissible Including flash memory 1100 and storage control 1200.

Flash memory 1100 and storage control 1200 can be included in a storage device.This is deposited Storage equipment can include USB storage, storage card, solid-state drive (SSD) etc..Additionally, this is deposited Storage equipment may be coupled to main frame (not shown), e.g., computer, notebook, digital camera, Mobile phone, MP3 player, PMP, game console etc., then can be used.

Flash memory 1100 can perform erasing according to the control of storage control 1200, writes or read Operation.With reference to Fig. 1, flash memory 1100 can include from interleaver 1141.Flash memory 1100 Can use and perform, from interleaver 1141 oneself, the operation that interweaves.Quick flashing will be more fully described with reference to Fig. 2 The inside configuration of memorizer 1100 and operation.

Again referring to Fig. 1, storage control 1200 can include flash interface 1210, HPI 1220, Error correcting code (ECC) circuit 1230, CPU (CPU) 1240 and buffer storage 1250. The data inputted from main frame (not shown) can be stored flash memory by storage control 1200 1100, and the data read from flash memory 1100 can be supplied to main frame.

Flash interface 1210 may be used for and flash memory 1100 exchange command, address and data. That is, flash interface 1210 can provide read command and address during read operation, and can write behaviour Write order, address and data are provided during work.HPI 1220 can be used to receive from main frame ask Asking, as write or reading, and the request in response to main frame provides data.

ECC circuit 1230 can use the data will being stored in flash memory 1100 to produce school Test position.In addition to data, during check bit is also stored on flash memory 1100.ECC circuit 1230 The limited amount system of the bit-errors that use ECC can correct.Such as, 1 bit ECC Engine is permissible Only correcting 1 bit-errors, 2 bit ECC Engine can only correct 2 bit-errors, and so on.One As, along with the quantity of repairable bit-errors increases, the expense of ECC circuit increases.

ECC circuit 1230 can use the check bit being stored in flash memory 1100 detect and entangle The error in data just read from flash memory 1100.This error detection and correction technology allows effectively Recover the data destroyed by various factors.Multiple method is used for error detection and correction technology, such as, inner Moral-Saloman (RS) code, Hamming code, Bose-Chaudhuri-Hocquenghem (BCH) code, follow Ring redundant code (CRC) etc..Additionally, according to the structure of storage system 1000, ECC circuit 1230 May be located at storage control 1200 interiorly or exteriorly.

ECC circuit 1230 can use ECC encoder (not shown) to produce check bit, and uses ECC decoder (not shown) is corrected mistake and recovers data.ECC circuit 1230 can be according to predetermined Data unit (hereafter, referred to as code word) perform check code or decoding operation.

CPU 1240 can control the reading and writing of flash memory 1100 in response to the request of main frame and wipe Division operation.

Buffer storage 1250 can store the data read from flash memory 1100 or from main frame temporarily The data provided.It addition, buffer storage 1250 can be used to drive firmware, such as, quick flashing conversion Layer (FTL).

Additionally, buffer storage 1250 can store for managing table information necessary to read error information. This table information can be stored as metadata in the unit of flash memory 1100 under the control of CPU 1240 In region.This table information is powering up period from this yuan of region duplication to buffer storage 1250.Although in figure Not shown, but storage system 1000 may further include for storage for being connected with HPI The ROM of code data.

The block diagram of the flash memory 1100 of Fig. 2 explanatory diagram 1.With reference to Fig. 2, flash memory 1100 Including memory cell array 1110, data input/output circuit 1120, address decoder 1130 and control Logic 1140 processed.

Memory cell array 1110 can include multiple memory block BLK1 to BLKn.Each memory block by Multiple pages of compositions.Each page (e.g., 1111) is made up of multiple memory element.Flash memory 1100 Erasing operation can be performed, it is possible to perform to write or read operation in units of page in units of memory block.

Data input/output circuit 1120 is connected to memory cell array 1110 by multiple bit lines BL. Data input/output circuit 1120 is for receiving programming data and passing them to the page selected or defeated Go out the data read from the page 1111 selected.

Address decoder 1130 is connected to memory cell array 1110 by a plurality of wordline WL.Address is translated Code device 1130 receives address AD DR and selects memory block or page.Here, for selecting memory block Address is represented as block address, and for selecting the address of page to be represented as page address.

Control logic 1140 to perform according to control signal CTRL provided from storage control 1200 Programming, reading and erasing operation.With reference to Fig. 2, control logic 1140 and can include from interleaver 1141. Can perform, with oneself, the operation that interweaves from interleaver 1141, and separate with the storage control 1200 of Fig. 1. The hardware of such as module and/or the software of such as algorithm can be utilized to realize from interleaver 1141.Additionally, The outside controlling logic 1140 is may be located at from interleaver 1141.

The circuit diagram of memory block BLK1 of Fig. 3 explanatory diagram 2.With reference to Fig. 3, memory block BLK1 has Unit string structure.One unit string includes that string select transistor, multiple memory element and ground select crystal Pipe.

String select transistor is connected to string and selects line SSL, and multiple memory element are connected to a plurality of wordline WL0 To WL31, and ground selects transistor to select line GSL with being connected to.String select transistor is connected to bit line BL1 to BLm, and ground selects transistor to be connected to common source polar curve CSL.

Multiple memory element may be coupled to a wordline (e.g., WLi).It is connected to depositing of a wordline The set of storage unit is referred to as Physical Page.One Physical Page can be divided into the master for storing master data Region and for storing the spare area of excessive data of such as check bit.

Single bit data can be stored in a memory element or multi-bit data is (that is, two or more The data of bit).The memory element of storage single bit data is called single level-cell (SLC), and stores The memory element of multi-bit data is called multi-level-cell (MLC) or multiple bit unit.

SLC has the erasing state according to starting voltage and programming state.MLC has according to starting voltage Erasing state and multiple programming state.Flash memory 1100 can have single level-cell with many simultaneously Level-cell.

2 bit MLC flash memory can store two logical page (LPAGE)s in a Physical Page.Here, Logical page (LPAGE) represents the set of the data that can simultaneously program in a Physical Page.3 bit MLC flash memory Memory device can store three logical page (LPAGE)s in a Physical Page, and 4 bit MLC flash memory can To store four logical page (LPAGE)s in a Physical Page.

The distribution of threshold voltages of the memory element of Fig. 4 to 7 explanatory diagram 3.More specifically, Figure 4 and 5 demonstration Property ground explanation in a memory element, wherein store the distribution of threshold voltages of memory element of 2 Bit datas. In Fig. 4, trunnion axis represents starting voltage Vth, and vertical axis represents the quantity of memory element.Memory element One in four states E, P1, P2 and P3 can be had according to distribution of threshold voltages.Here, E Represent erasing state, and P1, P2 and P3 represent programming state.

When storing 2 Bit data, memory element has four states.With reference to Fig. 5, the first logical page (LPAGE) (or LSB) and the second logical page (LPAGE) (or MSB) can be stored in a Physical Page 1111 of Fig. 3. There is memory element storage (11) of E-state, there is memory element storage (10) of P1, there is P2 Memory element storage (00), and have P3 memory element storage (01).

Flash memory 1100 can have different bit error rates (BER) in each logical page (LPAGE). Along with logical page (LPAGE) increases, BER increases with two for the factor.Such as, if the failed ratio in each reading level Special quantity is identical, then the BER of the first logical page (LPAGE) LSB is 1, and the BER of the second logical page (LPAGE) MSB It is 2.If storing N-bit data, then each about N number of logical page (LPAGE) in a memory element BER is 1: 2: 2²∶...∶2^N-1。

Fig. 6 and 7 explanation wherein stores the threshold electricity of the memory element of 4 Bit datas in a memory element Pressure distribution.With reference to Fig. 6, memory element can according to distribution of threshold voltages have 16 states E, P1, In P2 ..., P15 one.Here, E represents erasing state, and P1 to P15 represents programming shape State.In Fig. 6, R1 to R15 is the read voltage level for reading each state.

With reference to Fig. 7, the first to the 4th logical page (LPAGE) can be stored in a Physical Page 1111 of Fig. 3.Tool The memory element having E-state can store (1111), and the memory element with P1 state can store (1110), the memory element with P2 state can store (1100), and has depositing of P15 state Storage unit can store (0111).

Additionally, if it is assumed that the quantity of failed bit in each reading level is identical, then the first logical page (LPAGE) BER is 1, and the BER of the second logical page (LPAGE) is 2, and the BER of the 3rd logical page (LPAGE) is 4, and the 4th logic The BER of page is 8.

Referring again to Fig. 1, storage system 1000 can include the bit for correcting flash memory 1100 The ECC circuit 1230 of mistake.ECC circuit 1230 can be improved by detection and correction bit-errors The reliability of flash memory 1100.If flash memory 1100 stores N in a memory element Bit data, then the corrected scope of ECC circuit 1230 is arranged to the N with worst BER Logical page (LPAGE).Such as, if storing 4 Bit datas, then ECC circuit 1230 in a memory element Corrected scope be arranged to the 4th logical page (LPAGE).

The factor of the disproportionate expense that can be to increase ECC circuit 1230 of BER of each logical page (LPAGE). Along with the quantity that can correct bit increases, the area that ECC circuit 1230 occupies increases.By performing certainly Interweave operation, can average each logical page (LPAGE) according to the flash memory 1100 of Fig. 2 of embodiment BER, and the expense of ECC circuit 1230 can be reduced.Hereinafter, flash memory 1100 will be described From deinterleaving method as example embodiment.

II. from the embodiment of deinterleaving method

1.2 bit MLC flash memory from deinterleaving method

Fig. 8 illustrates the block diagram from the operation that interweaves of 2 bit MLC flash memory.With reference to Fig. 8, Fig. 2 Data input/output circuit 1120 include page buffer circuit 1121, column select circuit 1122 and data Buffer 1123.Data input/output circuit 1120 can perform according to from the control of interleaver 1141 From the operation that interweaves.

Again referring to Fig. 8, page buffer circuit 1121 can include multiple page buffer PB1 to PB2048. Each page buffer is connected to every bit lines, and includes at least two latch LATa and LATb.The One logical page (LPAGE) (page 1) is stored in LATa, and the second logical page (LPAGE) (page 2) is stored in LATb. LATa and LATb activates respectively responsive to signal ENa and ENb.

Column select circuit 1122 can select bit line in response to selecting signal SEL.Here, signal is selected SEL can be starting column address and Address count signal.Starting column address represents the page starting to store data Buffer, and Address count represents the number of the page buffer that will store data.Such as, if data Be stored in first to the 1024th page buffer PB1 to PB1024, then starting column address represents One page buffer PB1, and Address count represents the number of page, i.e. 1024.

Data buffer 1123 can be by byte unit or word unit recipient data.The data received are passed through Column select circuit 1122 is stored in page buffer circuit 1121.Data buffer 1123 can be according to certainly The control of interleaver 1141 receives or output data DATA.Additionally, the flash memory 1100 of Fig. 2 Can equip for performing the data buffer from the operation that interweaves, itself and the data buffering for input/output Device 1123 separates.

Can be by controlling page buffer circuit 1121, column select circuit 1122, sum from interleaver 1141 Perform from interweaving operation according to buffer 1123.Friendship can be performed by interleave unit from interleaver 1141 Knit operation.With reference to Fig. 8, the first and second logical page (LPAGE)s are made up of 2048 bits.Each logical page (LPAGE) can be drawn It is divided into multiple interleave unit (IU).Here, sector is defined as so as to performing the minimum single of operation that interweave Unit.Sector can be many from 1 bit to n-bit (e.g., 8 bits, 512 bits and 1024 bits) Sample ground adjusts.

The operation that interweaves refers to draw multiple logical page (LPAGE)s of storage in Fig. 3 Physical Page 1111 by IU Divide and mix their operation.Can alleviate by mixing multiple logical page (LPAGE)s by IU from interleaver 1141 BER between logical page (LPAGE) is unbalanced.That is, between interleaver 1141 can be by average logical page BER reduces the expense of the ECC circuit 1230 of Fig. 1.

Certainly the operation that interweaves of 2 bit MLC flash memory of Fig. 9 explanatory diagram 8.With reference to Fig. 8 and 9, First logical page (LPAGE) (page 1) can be divided into multiple IU, and an IU (IU1) is by two sectors A1 and A2 forms.Such as, if the first logical page (LPAGE) is 2048 bits, and the first interleave unit is 512 bits, the most each sector is 256 bits.Similarly, the second logical page (LPAGE) (page 2) can divide For multiple IU, and the 2nd IU (IU2) is made up of two sector B1 and B2.

First, inspection is not carried out the code word configuration interweaved when operating.Oneth IU (IU1) includes fan District A1 and A2, and the 2nd IU (IU2) includes sector B1 and B2.Now, due to an IU (IU1) Being included in the first logical page (LPAGE) (page 1), it has BER is 1, and due to the 2nd IU (IU2) Being included in the second logical page (LPAGE) (page 2), it has BER is 2.In Fig. 9, BER is by each sector One or more points represent.In the case of Gai, owing to ECC circuit 1230 is designed to meet the 2nd IU (IU2) BER, when not interweaving, it is 2 corresponding direct capacitance that ECC circuit 1230 has with BER Amount.

It follows that code word configuration when performing to interweave operation will be checked.By the first logical page (LPAGE) (page 1) The sector B1 mixing of sector A1 and the second logical page (LPAGE), thus form an IU (IU1).Oneth IU (IU1) It is included in the first logical page (LPAGE) and includes sector A1 and sector B1.Similarly, by sector A2 and fan District B2 mixes, thus finally composition the 2nd IU (IU2).2nd IU (IU2) is included in the second logic Form in Ye and by sector A2 and sector B2.Now, the first and second IU (IU1, IU2) Each BER is 1.5 (meansigma methodss of 1 and 2).In the case of Gai, ECC circuit 1230 has and subtracts The static capacity that few BER (e.g., BER meansigma methods, i.e. 1.5) is corresponding.

As it is shown in figure 9, once intertexture operation starts, owing to ECC circuit 1230 has the electrostatic of 1.5 Capacity, the static capacity of ECC circuit 1230 can reduce 0.5.The flash memory 1100 of Fig. 8 can The first and second logical page (LPAGE)s are divided into multiple IU and mix them by sector location, such that it is able to Perform from interweaving operation.According to embodiment, it is possible to reduce the expense of ECC circuit 1230.

2.4 bit MLC flash memory from deinterleaving method

Figure 10 illustrates the block diagram from the operation that interweaves of 4 bit MLC flash memory.With reference to Figure 10, The data input/output circuit 1120 of Fig. 2 includes page buffer circuit 1121, column select circuit 1122 and Data buffer 1123.Data input/output circuit 1120 can be according to the control from interleaver 1141 Perform from interweaving operation.

With reference to Figure 10, page buffer circuit 1121 includes multiple page buffer PB1 to PB2048.Each Page buffer includes at least four latch LATa to LATd.First to the 4th logical page (LPAGE) is respectively stored in In LATa to LATd.LATa to LATd activates respectively responsive to signal ENa to ENd.

Column select circuit 1122 can select bit line in response to selecting signal SEL.Here, signal is selected SEL can be starting column address and Address count signal.Data buffer 1123 can by byte unit, Word units etc. receive data.

Can be by controlling page buffer circuit 1121, column select circuit 1122, sum from interleaver 1141 Perform from interweaving operation according to buffer 1123.Activation signal ENa can be passed through from interleaver 1141 In LATa to LATd, data are stored to ENd.Additionally, can be by carrying from interleaver 1141 IU or sector size is determined for starting column address and Address count.

With reference to Figure 10 and 11, the first logical page (LPAGE) (page 1) can be divided into multiple IU, and an IU (IU1) it is made up of four sector A1 to A4.Similarly, the 2nd IU (IU2) by sector B1 to B4 forms, and the 3rd IU (IU3) is made up of sector C1 to C4, and the 4th IU (IU4) is by sector D1 to D4 forms.Now, the BER that the first to the 4th IU:IU1 to IU4 is respectively provided with is 1,2, 4 and 8.In Figure 11, BER is represented by the one or more points in each sector.In the case of Gai, by It is designed to meet the highest BER of sector, the BER of the i.e. the 4th IU (IU4) in ECC circuit 1230, It is 8 corresponding static capacities that ECC circuit 1230 has with BER.

In interleaver 1141, sector A1, B1, C1 and D1 are mixed, thus forms first IU(IU1).That is, the oneth IU (IU1) is made up of sector A1, B1, C1 and D1.Similarly, Sector A2, B2, C2 and D2 are mixed, thus forms the 2nd IU (IU2)；By sector A3, B3, C3 and D3 mix, thus form the 3rd IU (IU3)；And by sector A4, B4, C4 and D4 mixes, thus forms the 4th IU (IU4).Now, first to the 4th IU (IU1 to IU4) Each BER is 3.75, i.e. the meansigma methods between original sector before intertexture.

In the case of Gai, ECC circuit 1230 needs the BER value having with reducing (here for meansigma methods 3.75) corresponding static capacity.As shown in figure 11, once intertexture operation starts, due to ECC circuit 1230 require that the static capacity of 3.75, the static capacity of ECC circuit 1230 can reduce 4.25.

The flow chart from the operation that interweaves of the storage system 1000 of Figure 12 explanatory diagram 1.With reference to Fig. 1, root Can reduce between logical page (LPAGE) by performing intertexture operation certainly according to the storage system 1000 of embodiment BER is uneven.Hereinafter, the operation that certainly interweaves of the storage system 1000 shown in Fig. 1 will be described.

Storage system 1000 at operation S110, Fig. 1 determines the size of the data performing intertexture operation. The flash memory 1100 of Fig. 2 self performs the operation that interweaves, and can control from the storage of Fig. 1 Device 1200 provides the size of IU.

At operation S120, from storage control 1200 to the data buffering of Fig. 8 of flash memory 1100 Device 1123 transmits data.At operation S130, by column select circuit 1122 by data from data buffer 1123 are loaded into page buffer circuit 1121.Now, flash memory 1100 uses intertexture described here Mix the data of each IU.At operation S140, it is determined whether total data is all loaded into page buffer. If not yet loading total data, then repetitive operation S120 and S130.If having loaded total data, Then total state programming scheme simultaneously is used simultaneously to program the number of loading in memory element at operation S150 According to.According to Figure 12 from deinterleaving method, reduce the BER between logical page (LPAGE) uneven.Once alleviate BER is uneven, it is possible to reduce the static capacity of ECC circuit.

3. return copy from deinterleaving method what flash memory performed

The block diagram returning copy intertexture operation certainly of the flash memory of Figure 13 explanatory diagram 1.According to embodiment Flash memory 1100 can by from deinterleaving method perform copy-back operation.Copy-back operation represents The data of storage in the source page of flash memory are delivered to the operation of page object.

With reference to Figure 13, flash memory 1100 include memory cell array 1110, page buffer circuit 1121, Column select circuit 1122, data buffer 1123 and from interleaver 1141.Flash memory shown in Fig. 3 Reservoir 1100 can by from deinterleaving method perform copy-back operation and without the ECC circuit 1230 of Fig. 1 Overhead.

In Figure 13, it is assumed that the first and second logical page (LPAGE)s being stored in the source page of flash memory 1100 MSB and LSB is copied back page object.In order to perform copy function, every in page buffer circuit 1121 Individual page buffer (not shown) can include at least three latch, such as LATa, LATb and LATc. Latch LATa, LATb and LATc activate respectively responsive to signal ENa, ENb and ENc. It is used for controlling page buffer circuit 1121, column select circuit 1122 and data from interleaver 1141 generation slow Rush signal ENa, ENb, ENc, SEL and DBC of device 1123.

Figure 14 illustrates the flow chart returning copy intertexture operation certainly of the flash memory of Figure 13.With reference to Figure 13 With 14, copy describing returning of flash memory 1100 from interweaving operation.

At operation S210, flash memory 1100 reads the MSB data of source page and stores it in In latch LATc.From interleaver 1141 activation signal Enc so that MSB data is stored in latch In LATc.

At operation S220, the MSB data being stored in latch LATc is delivered to data buffer 1123.Now, MSB data can divide according to sector location and use interleaving scheme to be stored in lock In storage LATa and LATb.This intertexture can be performed with describing such as Fig. 8 and 9.From interleaver 1141 Can be by using control signal ENa, ENb, Enc, SEL and DBC by column select circuit 1122 In latch LATa and LATb, MSB data is stored with data buffer 1123.

At operation S230, the LSB data of reading source page also store it in latch LATc.? Operation S240, the LSB data being stored in latch LATc be passed to data buffer 1123, Divide according to sector location and use interleaving scheme to be stored in latch LATa and LATb.Now, According to from interleaver 1141, in response to control signal ENa, ENb, Enc, SEL and DBC, deposit Storage LSB data in latch LATc are by column select circuit 1122 and data buffer 1123 quilt Divide and be stored in latch LATa and LATb.At operation S250, use total state to program simultaneously The scheme program storage the most in the memory unit data in latch LATa and LATb.

4. use buffer storage returns copy from deinterleaving method

Figure 15 illustrates the block diagram performing back copy from the storage system of the operation that interweaves.With reference to Figure 15, storage System 1000 includes flash memory 1100, ECC circuit 1230 and buffer storage 1250.Hurry up Flash memory 1100 includes memory cell array 1110, page buffer circuit 1121 and from interleaver 1141. Buffer storage 1250 can be used to perform the copy-back operation of flash memory 1100.

At Figure 15, it is assumed that the first and second logical page (LPAGE)s being stored in the source page of flash memory 1100 MSB and LSB is copied back page object.In order to perform copy function, every in page buffer circuit 1121 Individual page buffer (not shown) needs at least two latch LATa and LATb.Latch LATa and LATb activates respectively responsive to signal ENa and ENb.Produce from interleaver 1141 and be used for controlling page Signal ENa and ENb of buffer circuit 1121.

Figure 16 illustrates the flow chart returning copy intertexture operation certainly of the storage system of Figure 15.With reference to Figure 15 With 16, copy describing the returning of storage system according to embodiment in order from interweaving operation.

At operation S310, flash memory 1100 reads MSB and the LSB data of source page and by it It is stored in latch LATa and LATb.At operation S320, will be stored in latch LATa and LATb In MSB and LSB data export buffer storage 1250.At operation S330, by MSB and LSB data divide according to sector location and use interleaving scheme to be stored in latch LATa and LATb. As set forth above, it is possible to obtain each sector by dividing the IU of each logical page (LPAGE) by scheduled unit.

At operation S330, the operation described with reference to Fig. 8 and 9 can be performed.That is, by produce about The check bit sum of the data being stored in buffer storage 1250 uses interleaving scheme, by data and check bit It is stored in latch LATa and LATb.At operation S340, latch LATa can be will be stored in It is simultaneously programmed into page object with the data in LATb.

III. from the application example of deinterleaving method

Figure 17 explanation is according to the block diagram when being applied to three-dimensional flash memory from deinterleaving method of embodiment. With reference to Figure 17, flash memory 2100 includes three-dimensional cell arrays 2110, data input/output circuit 2120, address decoder 2130 and control logic 2140.

Three-dimensional cell arrays 2110 includes multiple memory block BLK1 to BLKz.Each memory block has three Dimension structure (or vertical stratification).In the memory block with three dimensional structure, along the direction with substrate transverse Form memory element.Each memory block constitutes the erasing unit of flash memory 2100.

Data input/output circuit 2120 is connected to three-dimensional cell arrays by multiple bit lines BL.Data Input/output circuitry 2120 can be from external reception data DATA, maybe can be by from three-dimensional cell arrays 2110 data DATA read export outside.Address decoder 2130 by a plurality of wordline WL and Line GSL and SSL is selected to be connected to three-dimensional cell arrays 2110.Address decoder 2130 can receive Address AD DR and select wordline.

Control logic 2140 to include from interleaver 2141.Can perform, with self, the behaviour that interweaves from interleaver 2141 Make, separate with the storage control 1200 of Fig. 1.

Figure 18 illustrates the perspective view of the three dimensional structure of memory block BLK1 of Figure 17.With reference to Figure 18, along with Direction formation memory block BLK1 that substrate S UB is vertical.N+ doped region is formed in substrate S UB. Substrate S UB is alternately arranged gate electrode layer and insulating barrier.Can gate electrode layer and insulating barrier it Between formed charge storage layer.

By gate electrode layer and insulating barrier vertically cover half (pattern) are formed V-strut.This Post is connected to substrate S UB by gate electrode layer and insulating barrier.Exterior portion O of pillar can be by raceway groove Quasiconductor is constituted, and interior section I can be made up of the insulant of such as silicon dioxide.

Again referring to Figure 18, the gate electrode layer of memory block BLK1 selects line GSL, many with may be coupled to Bar wordline WL1 to WL8 and string select line SSL.The pillar of memory block BLK1 may be coupled to Multiple bit lines BL1 to BL3.In Figure 17, although illustrate that memory block BLK1 includes two selections Line GSL and SSL, 8 wordline WL1 to WL8 and three bit lines BL1 to BL3, but line Actual number can change.

Figure 19 illustrates the equivalent circuit figure of memory block BLK1 of Figure 17.Go here and there with reference to Figure 19, NAND NS11 to NS33 is connected between bit line BL1 to BL3 and common source polar curve CSL.Each NAND String (e.g., NS11) include string select transistor SST, multiple memory element MC1 to MC8 and Ground selects transistor GST.

String select transistor SST is connected to string and selects line SSL1 to SSL3.Multiple memory element MC1 Wordline WL1 to the WL8 of correspondence it is connected respectively to MC8.Ground selects transistor GST to be connected to ground Select line GSL1 to GSL3.String select transistor SST is connected to bit line BL, and ground selects transistor GST is connected to common source polar curve CSL.

Again referring to Figure 19, there is mutually level wordline (such as WL1) and jointly connected, and by ground Line GSL1 to GSL3 is selected to select line SSL1 to SSL3 to separate with string.If connected to the first wordline WL1 and be included in NAND string NS11, NS12 and NS13 in memory element (hereinafter referred to as Page) be programmed, then select the first wordline WL1 and first to select line SSL and GSL1.

Figure 20 illustrates the concept map of the planar structure of the equivalent circuit figure of Figure 19.With reference to Figure 20, Figure 19 Memory block BLK1 be made up of three planes.In Figure 20, NAND goes here and there NS11, NS12 and NS13 Composition plane PLANEa, NAND string NS21, NS22 and NS23 composition plane PLANEb, And NAND string NS31, NS32 and NS33 form plane PLANEc.WL1 be divided into WLa1, WLb1 and WLc1, and WL2 is divided into WLa2, WLb2 and WLc2.In the same way, WLn is divided into WLan, WLbn and WLcn.

Programmed order can change.For example, it is possible to perform programming from PLANEa to PLANEc order Operation.In each plane, programming operation can perform from WL1 to WL8 order.Additionally, such as figure Shown in 20, at least one plane can be farther included between PLANEb and PLANEc.

With reference to Figure 17, flash memory 2100 can use and perform, from interleaver 2141 oneself, the operation that interweaves. The operation that interweaves is performed by said method.

Storage system according to embodiment can apply to various product.Storage system can utilize electronics to set Standby (such as personal computer, digital camera, video camera, mobile phone, MP3, PMP, PSP, And PDA) and storage device (such as storage card, USB storage and solid-state drive (SSD)) Realize.

Figure 21 explanation is according to the figure of the flash memory system being applied to storage card of embodiment.Storage card system System 3000 includes main frame 3100 and storage card 3200.Main frame 3100 includes console controller 3110 and master Machine connects unit 3120.Storage card 3200 includes linking order unit 3210, card controller 3220 and fast Flash memory 3230.

Main frame 3100 can write data in storage card 3200, and can read and be stored in storage card Data in 3200.Console controller 3110 can connect unit 3120 to storage card 3200 by main frame Send order (e.g., write order), by main frame 3100 clock generator (not shown) produce time Clock signal CLK and data DATA.

The clock signal synchronization produced with the clock generator (not shown) of card controller 3220, control Device 3220 processed in response to by link order unit 3210 receive write order in flash memory 3230 Storage data.Flash memory 3230 stores the data sent from main frame 3100.Such as, if main frame 3100 is digital camera, then flash memory 3230 stores view data.

The storage card 3200 of Figure 21 can be by reducing the logic of flash memory 3230 from deinterleaving method BER between Ye is uneven.Executed as described above should from deinterleaving method.

Figure 22 explanation is according to the block diagram when storage system applications to SSD of embodiment.With reference to Figure 22, SSD system 4000 includes main frame 4100 and SSD 4200.

SSD 4200 exchanges signal by signal connector 4211 and main frame 4100, and is connected by power supply Connect device 4211 and receive power supply.SSD 4200 can include that multiple flash memory 4201 arrives 420n, SSD Controller 4210 and auxiliary power unit 4220.

Multiple flash memories 4201 are used as storage medium to 420n.SSD 4200 can use soon The non-volatile memories of such as PRAM, MRAM, ReRAM and FRAM outside flash memory Equipment.Multiple flash memories 4201 can be connected to by multiple channel C H1 to CHn to 420n SSD controller 4210.At least one flash memory may be coupled to a passage.It is connected to one The flash memory of passage may be coupled to identical data/address bus.

SSD controller 4210 exchanges signal SGL by signal connector 4211 and main frame 4100.This In, SGL can include order, address and data.SSD controller 4210 is according to main frame 4100 Order in corresponding flash memory, write data, or read data from corresponding flash memory.Will The inside configuration of SSD controller 4210 it is more fully described with reference to Figure 23.

Auxiliary power unit 4220 is connected to main frame 4100 by power connector 4221.Accessory power supply sets Standby 4220 receive power supply PWR from main frame 4100 and are charged.Additionally, auxiliary power unit 4220 Can be placed in SSD 4200 or outside SSD 4200.Such as, auxiliary power unit 4220 can be placed in In mainboard and accessory power supply can be provided to SSD 4200.

Figure 23 illustrates the block diagram of the configuration of the SSD controller 4210 of Figure 22.Control with reference to Figure 23, SSD Device 4210 processed includes that NVM interface 4211, HPI 4212, ECC circuit 4213, central authorities process Unit (CPU) 4214 and buffer storage 4215.

The data transmitted from buffer storage 4215 are distributed to each channel C H1 by NVM interface 4211 To CHn.Additionally, the data read from flash memory 4201 to 420n are passed by NVM interface 4211 It is delivered in buffer storage 4215.Here, NVM interface 4211 can use connecing of flash memory Mouth method.That is, SSD controller 4210 can according to flash memory interface method perform programming, reading, Or erasing operation.

HPI 4212 provides the interface with SSD 4200 according to the agreement of main frame 4100.Main frame connects Mouth 4212 can pass through USB (universal serial bus) (USB), small computer system interface (SCSI), PCI Quickly, ATA, Parallel ATA (PATA), serial ATA (SATA) and serial attachment SCSI (SAS) Communicate with main frame 4100.Emulate additionally, HPI 4212 can perform dish to support main frame 4100 SSD is identified as hard disk drive (HDD).

ECC circuit 4213 uses and is sent to the flash memory 4201 data to 420n by code word unit Produce the check bit of error correcting code (ECC).The check bit produced is stored in flash memory 4201 and arrives In the spare area of 420n.ECC circuit 4213 detects and reads from flash memory 4201 to 420n The mistake of data.If the mistake of detection is can be in correction scope, then ECC circuit 4213 corrects detection Mistake.

CPU 4214 analyzes and processes the signal SGL of the main frame 4100 from Fig. 2.CPU 4214 leads to Cross HPI 4212 or NVM interface 4211 controls main frame 4100 or flash memory 4201 arrives 420n.CPU 4214 is according to the firmware control flash memory 4201 to 420n for driving SSD 4200 Operation.

Buffer storage 4215 stores temporarily and writes data or from flash memory from what main frame 4100 provided The data read.Additionally, buffer storage 4215 can store will be stored in flash memory 4201 Metadata or cached data to 420n.During unexpected power-down operation, it is stored in buffer-stored Metadata in device 4215 or cached data are stored in flash memory 4201 in 420n. Buffer storage 4215 can include DRAM or SRAM.SSD 4000 shown in Figure 21 and 22 Can use and alleviate BER imbalance from deinterleaving method as above.

Figure 24 explanation is according to the block diagram when utilizing electronic equipment to realize flash memory system of embodiment. Here, electronic equipment 5000 can be implemented as personal computer (PC) or mancarried electronic aid, such as Notebook, mobile phone, personal digital assistant (PDA) and camera.

With reference to Figure 24, electronic equipment 5000 includes storage system 5100, power-supply device 5200, auxiliary electricity Source device 5250, CPU 5300, RAM 5400 and user interface 5500.Storage system 5100 is wrapped Include flash memory 5110 and storage control 5120.Storage system 5100 can use as above BER is alleviated uneven from deinterleaving method.

As summing up and looking back, according to embodiment, can be used to reduce BER between each sector from interweaving Difference.Such as, the page in different sectors can redistribute (that is, mixing) between sectors so that The BER obtaining each sector is identical, e.g., and the meansigma methods of BER between sector.Therefore, according to reality Execute example, BER can be alleviated uneven, it is possible to reduce the load of ECC circuit, and can reduce slow Rush the size of memorizer.

As it has been described above, from hardware or the software of such as algorithm or firmware that can utilize such as module that interweaves Realize.Algorithm or firmware can be implemented as computer-readable code in computer readable recording medium storing program for performing and / or program.The programmed method of the nonvolatile semiconductor memory member using interleaving technology according to some embodiments can To be realized by execution computer program, this computer program is for performing computer-readable record Jie The programmed method of the nonvolatile semiconductor memory member of storage in matter.

Computer readable recording medium storing program for performing is can store the data that read subsequently by computer system any Data storage device.More specifically, computer readable recording medium storing program for performing can be as tangible, non-of short duration Record medium.The example of computer readable recording medium storing program for performing includes read only memory (ROM), random access Memorizer (RAM), CD-ROM, tape, floppy disk and optical data storage devices.Rfid system In can transmit in the form of a carrier (such as performing the program code of method of the upgrading of operation sequence Transmitted by the data of the Internet).

Computer readable recording medium storing program for performing can also be distributed in network coupling computer system on so that with Distribution mode storage and/or computer readable code executed.Equally, can by the programmer executing example art To be readily derived for realizing the function program of embodiment, code and/or code segment.

Being already disclosed herein example embodiment, although use particular term, they are only according to general and retouch The implication of the property stated uses and explains rather than restrictive purpose.In some instances, this area is common Technical staff it is apparent that submit to the application time, in conjunction with specific embodiment describe feature, feature and / element can be used alone or in combination with the feature described with reference to other embodiments, feature and/or Element is used together, unless otherwise indicated outside.Therefore, it will be apparent to those skilled in the art that permissible Carry out the essence of the present invention that various change illustrates without departing from appended claims in form and details God and scope.

To Cross-Reference to Related Applications

This application claims in the korean patent application No. of JIUYUE in 2010 submission on the 20th The priority of 10-2010-0092583, entire contents by referring to and be incorporated in this.

Claims (39)

1. a memory device, including:

Memory cell array；

From interleaver, it is configured so that data are interweaved and are loaded into buffer circuits by interleaving scheme immediately In；And

Control logical block, be configured to control the programming of interleaving data in memory cell array,

Wherein:

This memory cell array includes that multiple Physical Page, each Physical Page can store multiple logical page (LPAGE)；

Should be configured to be divided into each logical page (LPAGE) multiple sector from interleaver, and by mixing each The sector of Different Logic page performs interleaving scheme；And

The volume of the logical page (LPAGE) of multiple mixing in the Physical Page of this control logical block control memory cell array Journey.

2. memory device as claimed in claim 1, wherein this control logical block includes that this is from interweaving Device.

3. memory device as claimed in claim 1, wherein from these memory device external reception data.

4. memory device as claimed in claim 1, wherein this buffer circuits stores data by sector.

5. memory device as claimed in claim 4, wherein this buffer circuits includes multiple pages of bufferings Device, it stores each sector in response to from the enable signal exported from interleaver and selection signal.

6. memory device as claimed in claim 5, the most each page buffer includes multiple latch, Each responsive is in depositing from the corresponding selection signal enabling signal and correspondence exported from interleaver Store up a bit.

7. memory device as claimed in claim 6, wherein should be configured to from interleaver with sector be Unit is by data interlacing and is loaded in buffer circuits.

8. memory device as claimed in claim 5, farther includes:

Column select circuit, selects the page buffer of this buffer circuits；And

Data buffer, provides the data from memory device external reception to column select circuit.

9. memory device as claimed in claim 8, wherein should be configured to control this from interleaver and delay Rush device circuit and this column select circuit interweaves and loading data.

10. memory device as claimed in claim 5, wherein data are from the source of this memory cell array Page, and wherein this control logical block is configured with interweaving control interleaving data to memory element battle array The programming of the page object in row.

11. memory device as claimed in claim 10, wherein should be configured to sequentially from interleaver N-bit data from source page are stored in the page 1 buffer of buffer circuits, transmission source number of pages According to data buffer, and source page data is interweaved immediately from page 1 buffer and is loaded into n lock In storage.

12. memory devices as claimed in claim 10, wherein should from interleaver be configured to by from The data of source page are stored in buffer circuits, the external circuit of transmission source page data to memory device, should Circuit processes source page data further, and is immediately interweaved from this external circuit by source page data and be loaded into In buffer circuits, and control the interleaving data programming to the page object of memory cell array.

13. memory devices as claimed in claim 10, wherein should from interleaver be configured to by from The data of source page and being stored in buffer circuits from the data outside memory device, and by source number of pages Immediately interweave according to from outside data and be loaded in buffer circuits, and control interleaving data arrives The programming of the page object of memory cell array.

14. memory devices as claimed in claim 1, wherein should be configured to determine that each from interleaver The size of sector.

15. memory devices as claimed in claim 1, wherein interleaving data has equal to multiple sectors The bit error rate of average bit error rate.

16. memory devices as claimed in claim 1, the most each Physical Page be divided into main region and Spare area.

17. memory devices as claimed in claim 1, wherein this memory cell array has three dimensional structure.

18. memory devices as claimed in claim 1, wherein this memory cell array is flash list Element array.

19. 1 kinds of storage systems, including:

Memory device as claimed in claim 1；And

Storage control, is configured to control the operation of this memory device.

20. store system as claimed in claim 19, wherein this storage system is SOC(system on a chip).

21. store system as claimed in claim 19, farther include error-correcting code circuit.

22. store system as claimed in claim 21, and wherein this error-correcting code circuit is that this storage controls A part for device.

23. store system as claimed in claim 21, wherein this error-correcting code circuit controls with this storage Device separates.

24. store system as claimed in claim 21, wherein be designed for will for this error-correcting code circuit The average bit error rate of the logical page (LPAGE) being stored in memory cell array.

25. store system as claimed in claim 19, farther include:

Main frame；And

Communication equipment, is configured to the swapping data at main frame Yu memory device.

26. store system as claimed in claim 19, farther include multiple such as claim 1 institute The memory device stated.

27. store system as claimed in claim 19, and wherein this memory device is of storage card Point.

28. store system as claimed in claim 19, and wherein this memory device is solid-state drive A part.

29. store system as claimed in claim 19, and wherein this memory device is flash memory.

30. 1 kinds of electronic equipments including storing system as claimed in claim 19.

31. the method operating memory device, including:

Receive data；

Interleaving scheme is used the data of reception immediately to be interweaved and be loaded in buffer circuits；And

Interleaving data is programmed in the memory cell array of memory device,

Wherein this memory cell array includes that multiple Physical Page, each Physical Page can store multiple logic Page,

Wherein interweave and load the data size comprising determining that sector to be interweaved, will be stored in and deposit Logical page (LPAGE) in storage unit array is divided into multiple sector, and mixes the sector of different logical page (LPAGE)s.

32. methods as claimed in claim 31, wherein receive data and include outside this memory device Receive data.

33. methods as claimed in claim 31, wherein receive data and farther include from this memorizer Part internal receipt data.

34. methods as claimed in claim 31, wherein receive data and include from memory cell array Source page receives data, and wherein programming includes the target being programmed in memory cell array by interleaving data Page.

35. methods as claimed in claim 31, wherein receive data and include from memory cell array Source page receives data and from receiving from the data outside memory device, wherein interweaves and loading includes mixing The incompatible data from source page and the data from outside, wherein programming includes interleaving data is programmed into storage Page object in cell array.

36. method as claimed in claim 31, wherein the bit error rate of interleaving data is equal to multiple The average bit error rate of sector.

37. methods as claimed in claim 31, farther include, before programming, it is determined whether Total data is already loaded in buffer circuits.

38. methods as claimed in claim 37, wherein, when total data is not yet loaded into buffering Time in device circuit, repeat to receive and interweave and load step.

39. methods as claimed in claim 31, wherein this memory cell array is flash memory cell Array.