CN102394249B - Mim capacitor - Google Patents
Mim capacitor Download PDFInfo
- Publication number
- CN102394249B CN102394249B CN201110176520.4A CN201110176520A CN102394249B CN 102394249 B CN102394249 B CN 102394249B CN 201110176520 A CN201110176520 A CN 201110176520A CN 102394249 B CN102394249 B CN 102394249B
- Authority
- CN
- China
- Prior art keywords
- metal
- mim capacitor
- layer
- insulating medium
- sealing coat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- 238000007789 sealing Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 24
- 239000004065 semiconductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Disclosure one MIM capacitor, this MIM capacitor includes: substrate; It is formed at the metal screen layer of this substrate surface; It is formed at the first metal layer on this metal screen layer; Around the first sealing coat that this first metal layer is formed; It is formed at the insulating medium layer on this first metal layer; And it is formed at the second metal level on this insulating medium layer, this second metal level is connected with this insulating medium layer by contact hole, pass through the present invention, not only make between cell capacitance influence each other very little, and substantially reduce parasitic capacitance, thus reduce the impact of the parasitic capacitance ADC performance on using this capacitor.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to the MIM capacitor of a kind of semiconductor applications.
Background technology
Capacitor is passive element conventional in super large-scale integration, it mainly includes polycrystalline silicon-on-insulator-polysilicon (PIP, Polysilicon-Insulator-Polysilicon), metal-insulator-silicon (MIS, and metal-insulator-metal type (MIM, Metal-Insulator-Metal) etc. Metal-Insulator-Silicon). Wherein, interference transistor caused due to MIM capacitor is minimum, and the good linearity (Linearity) and symmetry (Symmetry) can be provided, therefore obtain and be more widely applied, particularly mixed signal (Mixed-signal) and radio frequency (RF, RadioFrequency) field.
Fig. 1 is the cross-sectional view of existing a kind of MIM capacitor, and with reference to Fig. 1, the structure of this MIM capacitor 100 specifically includes that metal screen layer 101; It is formed at the bottom crown layer 102 on metal screen layer 101; It is formed at the insulating medium layer 103 on bottom crown layer 102; It is formed at the top crown layer 104 on insulating medium layer 103; And it being formed at the contact hole 105 in insulating medium layer 103, contact hole 105 is used for connecting top crown layer 104 and insulating medium layer 103, and bottom crown layer 102 is connected to junction point 106 by contact hole 105.
For this capacitor 100, electric capacity Ca is the electric capacity that design is wanted, but, capacitor 100 there is also following parasitic capacitance: CFm is the top crown edge edge capacitance to bottom crown, CFct is the dielectric edge edge capacitance to bottom crown, and parasitic capacitance CF=CFm+CFct then affects the electric capacity Ca accuracy calculated; CPm be top crown edge arrive the edge capacitance of (chip substrates of metal screen layer or ground connection), CPct be dielectric edge arrive the edge capacitance of (chip substrates of metal screen layer or ground connection), parasitic capacitance CP=CPm+CPct then can affect the performance of the ADC (Analog-to-DigitalConverter, analog-digital converter) using this capacitor.
In sum, the problem that the MIM capacitor of known prior art exists the performance owing to there is the accuracy that effect of parasitic capacitance capacitance calculates and the analog-digital converter using this capacitor, therefore, it is necessary the technological means proposing to improve in fact, solves this problem.
Summary of the invention
For overcoming the MIM capacitor of above-mentioned prior art to exist owing to there is the accuracy that effect of parasitic capacitance capacitance calculates and the problem of performance of the analog-digital converter using this capacitor; the present invention one of purpose be in that to provide a kind of MIM capacitor; by arranging protection bonding jumper around the first metal layer; make between cell capacitance influence each other fully little, it is possible to avoid mutual Rhizoma Nelumbinis problem.
Another object of the present invention is in that to provide a kind of MIM capacitor, by arranging Isolated Shield bar around the second metal level, substantially reduces second metal level parasitic capacitance to ground, thus reducing the impact of the performance of the parasitic capacitance ADC on using this capacitor.
A further object of the present invention is in that to provide a kind of MIM capacitor, by arranging a circle isolated insulation bar around insulating medium layer, insulating medium layer is made to be reduced to greatest extent to the parasitic capacitance on ground, thus reducing the impact of the performance of the parasitic capacitance ADC on using this capacitor further.
For reaching above-mentioned and other purpose, one MIM capacitor of the present invention, at least include:
Substrate;
It is formed at the metal screen layer of this substrate surface;
It is formed at the first metal layer on this metal screen layer;
Around the first sealing coat that this first metal layer is formed;
It is formed at the insulating medium layer on this first metal layer; And
Being formed at the second metal level on this insulating medium layer, this second metal level is connected with this insulating medium layer by contact hole.
Further, this first sealing coat at least includes the 4 block protection bonding jumpers that arrange around this first metal layer.
Further, the spacing that this protection bonding jumper requires with this first metal layer spacer process.
Further, this MIM capacitor also includes the second sealing coat, and this second sealing coat is arranged around this second metal level, and is connected to this first metal layer by contact hole.
Further, this second sealing coat is square Isolated Shield bar.
Further, this capacitor MIM capacitor also includes dielectric isolating bar, and this dielectric isolating bar is arranged in this dielectric, and is connected with this second sealing coat by contact hole.
Further, this first metal layer can be tantalum, tantalum nitride, titanium, titanium nitride or aluminum with the material of this second metal level.
Compared with prior art, the present invention provides a kind of MIM capacitor, it is by arranging protection bonding jumper around the first metal layer, make between cell capacitance influence each other fully little, avoiding the mutual Rhizoma Nelumbinis problem between cell capacitance, meanwhile, the present invention arranges Isolated Shield bar also by around the second metal level, substantially reduce second metal level parasitic capacitance to ground, thus reducing the impact of the performance of the parasitic capacitance ADC on using this capacitor; It addition, the present invention is by arranging a circle isolated insulation bar around insulating medium layer, insulating medium layer is made to be reduced to greatest extent to the parasitic capacitance on ground, thus reducing the impact of the performance of the parasitic capacitance ADC on using this capacitor further.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of existing a kind of MIM capacitor;
Fig. 2 is the top view of a kind of MIM capacitor preferred embodiment of the present invention;
Fig. 3 is the present invention generalized section along the AA ' direction of Fig. 2;
Fig. 4 is the present invention generalized section along the BB ' direction of Fig. 2
Fig. 5 is the present invention generalized section along the CC ' direction of Fig. 2.
Detailed description of the invention
Below by way of specific instantiation accompanying drawings embodiments of the present invention, those skilled in the art can be understood further advantage and effect of the present invention easily by content disclosed in the present specification. The present invention also can pass through other different instantiation and be implemented or apply, and the every details in this specification also based on different viewpoints and application, can carry out various modification and change under the spirit without departing substantially from the present invention.
Fig. 2 is the top view of a kind of MIM capacitor preferred embodiment of the present invention, Fig. 3 is the present invention generalized section along the AA ' direction of Fig. 2, Fig. 4 is the present invention generalized section along the BB ' direction of Fig. 2, Fig. 5 is the present invention generalized section along the CC ' direction of Fig. 2, and the MIM capacitor structure below in conjunction with-5 couples of present invention of Fig. 2 describes in detail.
In conjunction with Fig. 2-5, the MIM capacitor of the present invention is a kind of stereochemical structure, is similar to a kind of Miniature double-pole plate electric capacity, and its technique uses 5 layers of metal altogether, this MIM capacitor at least includes: Semiconductor substrate 210, and this Semiconductor substrate 210 can be the substrate of the semiconductor element already formed with other; The metal screen layer 211 formed on the surface of this Semiconductor substrate 210; The first metal layer 212 formed on this metal screen layer 211; Around the first sealing coat 213 that the first metal layer 212 is formed, this first sealing coat 213 at least includes the 4 block protection bonding jumpers arranged around this first metal layer 212, the spacing that this protection bonding jumper and this first metal layer 212 spacer process require, influencing each other between such cell capacitance is fully little, it is possible to avoid mutual Rhizoma Nelumbinis problem; It is formed at the insulating medium layer 214 on this first metal layer 212; It is formed at the second metal level 215 on this insulating medium layer 214; And contact hole 216, it is formed in insulating medium layer 214, is used for connecting the second metal level 215 and insulating medium layer 214, meanwhile, is additionally operable to connect each contact point 217. The wherein optional tantalum of the material of the first metal layer 212 and the second metal level 215, tantalum nitride, titanium, titanium nitride or aluminum.
Preferably, metal level at the second metal level 215 place, the spacing required around the second metal level 215 spacer process arranges the second sealing coat (not shown), and the second sealing coat is connected to the first metal layer 212 by contact hole 216, this second sealing coat is square Isolated Shield bar, such second metal level 215 is just surrounded by the first metal layer 212, second metal level 215 is blocked on the second sealing coat (square Isolated Shield bar) to the electric lines of force of ground wire with regard to the overwhelming majority, actual is exactly on the first metal layer 212, thus substantially reduce second metal level 215 parasitic capacitance (i.e. CPm in background technology) to ground, thus reducing the impact of the performance of the parasitic capacitance ADC on using MIM capacitor of the present invention.
Please continue to refer to Fig. 4, in order to reduce the parasitic capacitance impact on ADC performance, preferably, the present invention is in the insulating medium layer 214 at dielectric place, around the spacing that the dielectric spacer process of this cell capacitance requires, a circle dielectric isolating bar is set up around dielectric, and the second sealing coat 218 on this dielectric isolating bar and the second metal level 215 is coupled together by contact hole 216, the electric lines of force of such MIM capacitor of the present invention insulating medium layer edge is just blocked on this dielectric isolating bar, insulating medium layer 214 is reduced (i.e. CPct described in background technology) to greatest extent to the parasitic capacitance on ground, thus reducing the parasitic capacitance impact on ADC performance further.
Visible, the invention provides a kind of MIM capacitor, it is by arranging protection bonding jumper around the first metal layer, make between cell capacitance influence each other fully little, avoiding the mutual Rhizoma Nelumbinis problem between cell capacitance, meanwhile, the present invention arranges Isolated Shield bar also by around the second metal level, substantially reduce second metal level parasitic capacitance to ground, thus reducing the impact of the performance of the parasitic capacitance ADC on using this capacitor; It addition, the present invention is by arranging a circle isolated insulation bar around insulating medium layer, insulating medium layer is made to be reduced to greatest extent to the parasitic capacitance on ground, thus reducing the impact of the performance of the parasitic capacitance ADC on using this capacitor further.
Above-described embodiment is illustrative principles of the invention and effect thereof only, not for the restriction present invention. Above-described embodiment all under the spirit and category of the present invention, can carried out modifying and change by any those skilled in the art. Therefore, the scope of the present invention, should as listed by claims.
Claims (7)
1. a MIM capacitor, described MIM capacitor includes: substrate and be formed at the metal screen layer of this substrate surface, it is characterised in that at least include:
It is formed at the first metal layer on this metal screen layer;
Around the first sealing coat that this first metal layer is formed;
It is formed at the insulating medium layer on this first metal layer; And
Being formed at the second metal level on this insulating medium layer, this second metal level is connected with this insulating medium layer by contact hole.
2. MIM capacitor as claimed in claim 1, it is characterised in that: this first sealing coat at least includes the 4 block protection bonding jumpers arranged around this first metal layer.
3. MIM capacitor as claimed in claim 2, it is characterised in that: the spacing that this protection bonding jumper requires with this first metal layer spacer process.
4. MIM capacitor as claimed in claim 1, it is characterised in that: this MIM capacitor also includes the second sealing coat, and this second sealing coat is arranged around this second metal level, and is connected to this first metal layer by contact hole.
5. MIM capacitor as claimed in claim 4, it is characterised in that: this second sealing coat is square Isolated Shield bar.
6. MIM capacitor as claimed in claim 5, it is characterised in that: this capacitor MIM capacitor also includes dielectric isolating bar, and this dielectric isolating bar is arranged in this dielectric, and is connected with this second sealing coat by contact hole.
7. MIM capacitor as claimed in claim 1, it is characterised in that: the material of this first metal layer and this second metal level can be tantalum, tantalum nitride, titanium, titanium nitride or aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110176520.4A CN102394249B (en) | 2011-06-28 | 2011-06-28 | Mim capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110176520.4A CN102394249B (en) | 2011-06-28 | 2011-06-28 | Mim capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102394249A CN102394249A (en) | 2012-03-28 |
| CN102394249B true CN102394249B (en) | 2016-06-01 |
Family
ID=45861506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110176520.4A Active CN102394249B (en) | 2011-06-28 | 2011-06-28 | Mim capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102394249B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579222B (en) * | 2013-01-29 | 2016-03-23 | 中国科学院高能物理研究所 | Capacitor topological structure and integrated circuit |
| CN104425442A (en) * | 2013-09-09 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN105304620B (en) * | 2015-10-30 | 2018-06-26 | 上海华虹宏力半导体制造有限公司 | Capacitance connection circuit and digital analog converter |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101461060A (en) * | 2006-06-02 | 2009-06-17 | 肯奈特公司 | Improved metal-insulator-metal capacitors |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100640065B1 (en) * | 2005-03-02 | 2006-10-31 | 삼성전자주식회사 | MIM capacitor comprising ground shield layer |
| US7994609B2 (en) * | 2008-11-21 | 2011-08-09 | Xilinx, Inc. | Shielding for integrated capacitors |
| JP2010225880A (en) * | 2009-03-24 | 2010-10-07 | Nec Corp | Semiconductor device and method of manufacturing the same |
-
2011
- 2011-06-28 CN CN201110176520.4A patent/CN102394249B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101461060A (en) * | 2006-06-02 | 2009-06-17 | 肯奈特公司 | Improved metal-insulator-metal capacitors |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102394249A (en) | 2012-03-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7518850B2 (en) | High yield, high density on-chip capacitor design | |
| US11862834B2 (en) | Distributed LC filter structure | |
| US9564484B2 (en) | Metal-insulator-metal back end of line capacitor structures | |
| CN102394249B (en) | Mim capacitor | |
| CN107251215A (en) | Stack device | |
| CN105390480A (en) | Three-dimensional high-value integrated capacitor based on through-silicon-via array, and manufacturing method thereof | |
| US8476687B2 (en) | Low impedance transmisson line | |
| JP3549499B2 (en) | Semiconductor integrated circuit device, D / A converter, and A / D converter | |
| US9356137B2 (en) | Power MOS device structure | |
| US9385246B2 (en) | Differential MOSCAP device | |
| US9224685B1 (en) | Shielded metal-oxide-metal (MOM) capacitor structure | |
| KR20180033504A (en) | Conductive seal ring for power distribution | |
| CN103730450A (en) | Organic electric excitation light-emitting diode storage capacitor structure and manufacturing method thereof | |
| CN101378057B (en) | Metal-insulator-metal capacitor and method for manufacturing the same | |
| CN104425442A (en) | Semiconductor device and preparation method thereof | |
| US8154847B2 (en) | Capacitor structure | |
| CN103021956A (en) | PIP (poly-insulator-poly) capacitor of split gate type flash memory and manufacturing method of PIP capacitor | |
| US10714419B2 (en) | Non-planar metal-insulator-metal capacitor formation | |
| CN103956326A (en) | Manufacturing method for integrated passive interposer and corresponding integrated passive interposer | |
| CN106409809B (en) | A kind of semiconductor devices with capacitor | |
| CN106469716A (en) | A kind of vertical-type capacitor arrangement | |
| CN102446915B (en) | Novel metal-insulator-metal (MIM) capacitor structure and manufacturing method thereof | |
| WO2019128911A1 (en) | Chip and electronic device | |
| CN104392897A (en) | Production method of MIM capacitor | |
| CN106340509B (en) | A kind of manufacturing method of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140425 |
|
| C10 | Entry into substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140425 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Grace Semiconductor Manufacturing Corp. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |