CN102394042A

CN102394042A - Gate scanning circuit

Info

Publication number: CN102394042A
Application number: CN2011103683514A
Authority: CN
Inventors: 罗红磊; 邱勇; 黄秀颀; 高孝裕
Original assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Current assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Priority date: 2011-11-19
Filing date: 2011-11-19
Publication date: 2012-03-28
Anticipated expiration: 2031-11-19
Also published as: CN102394042B

Abstract

The invention discloses a gate scanning circuit that comprises a plurality of shift registers that are connected in series. Setting terminals of a first row of shift registers are connected with a time schedule controller to receive a STV; setting terminals of other shift registers are connected with output terminals of a previous row of shift registers; clock input terminals of all rows of the shift registers are connected with the time schedule controller to receive a CPV and a XCPV; and the output terminals are connected with a gate line of the current row. Besides, the gate scanning circuit also comprises a gate repairing signal modulation module and a gate scanning repairing line; output terminals of level resetting units are connected with the setting terminals of the shift registers so as to output a VGH level signal. According to the provided gate scanning circuit in the invention, repairing of a bad gate scanning circuit is realized by adding level resetting units; an adverse phenomenon of frequent occurrences of screen interruption can be improved; and reliability and a yield rate of a gate scanning module can be improved.

Description

The gated sweep circuit

Technical field

The present invention relates to a kind of driving circuit, relate in particular to a kind of gated sweep circuit.

Background technology

Organic light emitting display (OLED) is the active illuminating device.Compare present main flow flat panel display Thin Film Transistor-LCD (TFT-LCD); OLED has high-contrast; Wide viewing angle, low-power consumption, advantage such as volume is thinner; Being expected to become the flat panel display of future generation after LCD, is one of the maximum technology that receives publicity in the present flat panel display.

Fig. 1 is the Organization Chart commonly used of active matrix light-emitting circuit of display driving, and the signal of coming in from interface connector 10 (Interface Connector) has power vd D, data-signal and control signal.Power vd D is through DC-to-dc converter 101, and step-down is digital signal power supply DVDD, gives data driver 30 (Source block), gate drivers 40 (Gate block) and time schedule controller 20 (T/CON) power supply; Boosting is analog power AVDD, supplies gamma to correct circuit 102 and does reference voltage source.

After data-signal and control signal got into time schedule controller 20, time schedule controller 20 produced control timing, is sent to data on the Source IC.The STV (frame scan start signal) that provides in response to T/CON of Gate IC then, CPV (line-scanning frequency signal) opens the switching TFT of every row; Source IC is in response to the STH that provides of T/CON, and control signals such as LOAD are converted into simulating signal to the digital signal that receives from T/CON; Cooperate STV; Signals such as CPV are loaded into storing on the electric capacity of AMOLED sub-pixel to aanalogvoltage, according to this potential value height, the conducting degree of control TFT; Reach control OLED brightness, show the purpose of different GTGs.

Because each producer is for saving the manufacturing cost of gated sweep chip, with the gated sweep circuit production to glass substrate.Its circuit framework mainly is made up of shift register; Time schedule controller sends STV (frame scan start signal) signal to GOA (gate on array) unit through WOA (wire on array) cabling; Then, shifting deposit unit is according to CPV, the signal frequency of XCPV; Hand on step by step, as shown in Figure 2.

For example gate driver circuit has the n level, and n is a number of lines of pixels on the panel, and n is natural number, and is as shown in Figure 3.During operate as normal, time schedule controller sends STV (frame scan start signal) signal to GOA (gate on array) unit through WOA (wire on array) array upward wiring.Then, shifting deposit unit is according to CPV, and the signal frequency of XCPV hands on step by step, gives gate lines G 1, G2, G3 ... The output line scan signals is controlled in each row image element circuit and controlled opening and closing of TFT, and is as shown in Figure 4.Wherein any one-level malfunction all will make its all circuit of back to work, so, require the gated sweep circuit to have high reliability.But because the otherness and the instability of TFT characteristic cause the output waveform distortion easily, the gated sweep signal is distorted and decays.Make that the gated sweep signal can't normal delivery, as shown in Figure 5, the high level of gate lines G 1 line scan signals is VGH; Low level is VGL, and the high level of the capable gate lines G i line scan signals of i is VGiH, and low level is VGiL; After the gated sweep signal is distorted and decays; VGH>VGiH 0 or VGL VGiL 0, thus cause later each of this row row all can not normally show, i.e. " disconnected screen " phenomenon.

Summary of the invention

Technical matters to be solved by this invention provides a kind of gated sweep circuit, can effectively solve panel " disconnected screen " phenomenon, and simple in structure, is easy to control.

The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of gated sweep circuit, comprises n shift register; Each shift register comprises clock input terminal, set terminal and lead-out terminal; Said a plurality of shift register is chained together successively; Wherein, The set terminal of first line shift register links to each other with time schedule controller and receives frame scan start signal STV; The set terminal of all the other shift registers links to each other with the lead-out terminal of previous row shift register, and the clock input terminal of each line shift register links to each other with time schedule controller and receives line-scanning frequency signal CPV and XCPV, and lead-out terminal links to each other with the current line gate line and exports line scan signals; The standard high level of said line scan signals is VGH, and the standard low level is VGL; Wherein, Said gated sweep circuit also comprises the level reset unit; The input end of said level reset unit links to each other with the capable shift register output terminal of i and receives line scan signals VGi, and the output terminal of said level reset unit links to each other with the shift register input end of next line and exports line scan signals VGi+1; The high level of said line scan signals VGi is VGiH, and low level is VGiL; The high level of said line scan signals VGi+1 is VGH, and low level is VGL, VGiH ≤VGH, VGiL >=VGL, i=n, and i, n are natural number, n is a number of lines of pixels on the panel.

Above-mentioned gated sweep circuit, wherein, said level reset unit is connected between the shift register.

Above-mentioned gated sweep circuit, wherein, the number of said level reset unit is 2～4, said level reset unit uniformly-spaced is connected between the shift register.

Above-mentioned gated sweep circuit; Wherein, Said level reset unit comprises the first transistor T1 and transistor seconds T2, and the grid of said the first transistor T1 links to each other with transistor seconds T2 grid and forms input end, and the source electrode of said the first transistor T1 drains to link to each other with transistor seconds T2 and forms output terminal; The drain electrode of said the first transistor T1 links to each other with VGL level signal line, and the source electrode of said transistor seconds T2 links to each other with VGH level signal line.

Above-mentioned gated sweep circuit, wherein, said level reset unit is a voltage comparator, when input voltage greater than reference voltage Vref time output VGH level signal, when input voltage output VGL level signal during less than reference voltage Vref; Said voltage comparator is integrated in the chip for driving of gated sweep circuit.

The present invention contrasts prior art has following beneficial effect: gated sweep circuit provided by the invention; Realized the reparation of bad gated sweep circuit through increasing the level reset unit; Realized the reparation of bad gated sweep circuit; Improve the bad phenomenon occurred frequently of disconnected screen, improve the reliability and the yield of gated sweep module.

Description of drawings

Fig. 1 is a kind of driving framework synoptic diagram of active matrix/organic light emitting display;

Fig. 2 is existing gated sweep circuit diagram;

Fig. 3 is a gated sweep circuit module equivalent schematic;

Fig. 4 is each element output signal waveform synoptic diagram of gated sweep circuit;

Fig. 5 is the bad signal output waveform synoptic diagram of gated sweep circuit;

Fig. 6 is the bad output signal level of the gated sweep circuit synoptic diagram that resets;

Fig. 7 has the gated sweep circuit embodiment one of level reset unit for the present invention;

Fig. 8 is the circuit module synoptic diagram of level reset unit among Fig. 7;

Fig. 9 has the gated sweep circuit embodiment two of level reset unit for the present invention;

Figure 10 is the circuit module synoptic diagram of level reset unit among Fig. 9.

Among the figure:

10 interface connectors, 20 time schedule controllers, 30 data drivers

40 gate drivers, 101 DC-to-dc converters, 102 gammas are corrected circuit

103 level reset units, 104 shift registers

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is done further description.

Gated sweep circuit provided by the invention comprises n shift register 104, like SR1, SR2 among Fig. 3 ..., SRn-1, SRn; Each shift register 104 comprises clock input terminal, set terminal and lead-out terminal; Said a plurality of shift register is chained together successively; Wherein, The set terminal of the first line shift register SR1 links to each other with time schedule controller 20 and receives frame scan start signal STV; The set terminal of all the other shift registers links to each other with the lead-out terminal of previous row shift register, and the clock input terminal of each line shift register links to each other with time schedule controller and receives line-scanning frequency signal CPV and XCPV, and lead-out terminal links to each other with the current line gate line and exports line scan signals; The standard high level of said line scan signals is VGH, and the standard low level is VGL; Wherein, Said gated sweep circuit also comprises level reset unit 103; The input end of said level reset unit 103 links to each other with the capable shift register SRi output terminal of i and receives line scan signals VGi, and the output terminal of said level reset unit links to each other with the shift register input end of next line and exports line scan signals VGi+1; The high level of said line scan signals VGi is VGiH, and low level is VGiL; The high level of said line scan signals VGi+1 is VGH, and low level is VGL, VGiH ≤VGH, VGiL >=VGL, i=n, and i, n are natural number, n is a number of lines of pixels on the panel.

Embodiment one, as shown in Figure 7, at every level reset unit that behind the several rows shifting deposit unit, increases; STV is the frame scan start signal, and CPV and XCPV are for the signal of control grid sweep circuit sweep frequency, in present GOA unit; XCPV is and the CPV frequency; Amplitude is all identical, but the opposite reverse signal of phase place needs CPV and XCPV to cooperate shift register displacement outputs at different levels are handed on step by step.

Level reset unit circuit structure canonical schema is as shown in Figure 8.When VGi is output as high level, the T2 conducting, VGi output high level VGH, when VGn is output as low level, T1 conducting, VGnout output low level VGL.At this moment, the level value of VGnout output no longer is the level value of upper level sweep circuit, but by the reset level value that VGH and VGL determine, reaches the purpose that the output signal level value is reset with this.

Embodiment two, as shown in Figure 9, at every level reset unit that behind the several rows shift register, increases.Through inner to chip for driving, carry out resetting of level value the gated sweep signal feedback of this row.

This level reset unit circuit structure canonical schema is shown in figure 10, does contrast through certain reference potential VGn signal and comparer, and when the VGn signal was higher than reference potential Vref, output was height.When the VGn signal was lower than reference potential Vref, output was low.With the 10th line shift register SR10 is example, after the line scan signals G10 of its output feeds back to the AMOLED chip for driving, behind the level reseting module that is integrated in the AMOLED chip for driving; Obtain G10out; Pass to the 11st line shift register, the high level of G10out is VGH, low level VGL.

Embodiment two is that with the difference of scheme one level reset unit 103 is arranged on chip for driving inside; And the level reset unit of scheme one is arranged on the glass substrate, occurs with shifting deposit unit is staggered, and the frequency of appearance is by the degree of stability and the degree of ripeness decision of technology; Consider no matter level reset unit 103 is produced on the panel or is integrated in the chip; All will take certain space and increase manufacturing cost, for the purpose of the compromise, be good with 2-4 level buanch unit.Under the extreme case, can be level translator of each shift register configuration, but lose the raising yield, cost-effective value.

Though the present invention discloses as above with preferred embodiment; Right its is not that any those skilled in the art are not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little modification and perfect, so protection scope of the present invention is when being as the criterion with what claims defined.

Claims

1. gated sweep circuit comprises:

N shift register;

Each shift register comprises clock input terminal, set terminal and lead-out terminal;

Said a plurality of shift register is chained together successively; Wherein, The set terminal of first line shift register links to each other with time schedule controller and receives frame scan start signal STV; The set terminal of all the other shift registers links to each other with the lead-out terminal of previous row shift register, and the clock input terminal of each line shift register links to each other with time schedule controller and receives line-scanning frequency signal CPV and XCPV, and lead-out terminal links to each other with the current line gate line and exports line scan signals; The standard high level of said line scan signals is VGH, and the standard low level is VGL;

It is characterized in that; Said gated sweep circuit also comprises the level reset unit; The input end of said level reset unit links to each other with the capable shift register output terminal of i and receives line scan signals VGi, and the output terminal of said level reset unit links to each other with the shift register input end of next line and exports line scan signals VGi+1; The high level of said line scan signals VGi is VGiH, and low level is VGiL; The high level of said line scan signals VGi+1 is VGH, and low level is VGL, VGiH ≤VGH, VGiL >=VGL, i=n, and i, n are natural number, n is a number of lines of pixels on the panel.

2. gated sweep circuit as claimed in claim 1 is characterized in that, said level reset unit is connected between the shift register.

3. gated sweep circuit as claimed in claim 2 is characterized in that, the number of said level reset unit is 2～4, and said level reset unit uniformly-spaced is connected between the shift register.

4. like each described gated sweep circuit of claim 1～3; It is characterized in that; Said level reset unit comprises the first transistor T1 and transistor seconds T2; The grid of said the first transistor T1 links to each other with transistor seconds T2 grid and forms input end; The source electrode of said the first transistor T1 drains to link to each other with transistor seconds T2 and forms output terminal, and the drain electrode of said the first transistor T1 links to each other with VGL level signal line, and the source electrode of said transistor seconds T2 links to each other with VGH level signal line.

5. gated sweep circuit as claimed in claim 1; It is characterized in that; Said level reset unit is a voltage comparator, when input voltage greater than reference voltage Vref time output VGH level signal, when input voltage output VGL level signal during less than reference voltage Vref; Said voltage comparator is integrated in the chip for driving of gated sweep circuit.