CN102386285A - Low-cost solar cells and methods for fabricating low cost substrates for solar cells - Google Patents
Low-cost solar cells and methods for fabricating low cost substrates for solar cells Download PDFInfo
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Abstract
The invention discloses low-cost solar cells and methods for fabricating low cost substrates for solar cells. Substrates for solar cells are prepared by etching a plurality of metallurgical grade wafers; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride without disturbing the aluminum layer. A solar cell is then fabricated on the front surface of the wafer while the aluminum remains to serve as the back contact of the cell.
Description
Technical field
The present invention relates to solar-energy photo-voltaic cell, relate more specifically to be used to supply the manufacturing approach of the low-cost basis material that such battery uses and be used to make the method for low-cost battery and the battery device structure that is obtained.
Background technology
Conventional had been played the part of since glacial epoch last time the peaceful biggest threat of the earth by the fossil fuel generation energy.In all alternative energy sources, except that energy-conservation, compare with other approach such as ethanol, water power and wind energy, can to prove solar-energy photo-voltaic cell be the cleanest, ubiquitous and possibly be to select the most reliably.Principle is the simple solid-state p-n junction that light is converted into little direct voltage.Can be with battery stack to import electrical network to the Vehicular battery charging or through the DC/AC conversion.In can be used for the various semi-conducting materials of this purpose, silicon occupies 99% of photovoltaic solar cell output.Compare with the solar cell of other based compound semiconductor; Although it has high conversion rate; Particularly in the small size battery, but silicon is much abundant in the earth's crust, and the reliability that obtains proving up to 30 years is provided on weather-beaten roof under the various weathers in the whole world.In addition, utilize the large-scale commercial applications manufacturing technology of silicon to use many decades and development well to understand with being convenient to.Therefore, silicon remains the dominant basis material that is used for solar cell probably.
Yet although the development in 30 years of warp, silica-based solar cell has not also been given play to its potential that is used for extensive generating.Major obstacle to its approval is and manufacturing solar cell cost related, in particular for the raw material of making solar cell, the cost of basis material (substrate).With only about 10% compare under the situation of semiconductor microactuator chip, it is half that material accounts for surpassing of solar cell total manufacturing cost.Be that because huge demand and high production cost, in fact the price that is used for the silicon materials of solar cell increases with oil price synchronously sarcastically.For example, in the past few years in, the cost that is used to produce the every kg of polycrystalline silicon material of solar energy silicon crystal chip significantly increases, for thin film solar cell, be used to deposit this film silane gas cost and after deposition the NF of cleaning reaction device
3The cost of gas likewise increases.On the contrary, in the past 30 years of semiconductor chip price (that is, storage of every unit or logic function) reduce according to Moore's Law index ground.This difference of learning curve possibly relate to the technical and material main difference with respect to the proportion (than the technology and the design of the per unit area device density that improves day by day) of cost.
According to the current state of this area, undertaken by three Main Stage based on the manufacture of solar cells of polysilicon.The first, be used for a large amount of silicon wafers of substrate for more moderate 25MW capacity plant produced---every month 1,000,000 wafers typically.The second, through forming p-n junction and metallizing these wafer process are become solar cell.The 3rd, then these wafers " encapsulation " are become to supply the module of installing and using in the user facility.
The hazardous gas that contains Si-H-Cl such as dichlorosilane and trichlorosilane through thermal decomposition is produced ultra-pure polysilicon, is often referred to nine nine, and promptly 99.9999999% purity is made the basic silicon wafer that is used for solar cell.These gases are very easily to fire and poisonous.Yet, owing in the gasification of silicon, endanger environment and health, only have factory seldom turning round in the world, thereby cause the bottleneck of semiconductor and solar cell industry.The silicon gasification factory of new plan faces from local community based on environment and safety resistance deeply concerned.These factories also need a large amount of capital inputs and long construction period.Therefore, between the demand and supply of naked silicon wafer, there is imbalance all the time.
Usually by the graininess that is fit to semiconductor and solar cell application pure silicon (being called polysilicon, after the gasification and decomposition of silane-based compound) is provided.Make particle fusion then and utilize crystal seed pulling single crystal rod or the polycrystalline band.Perhaps, polysilicon is cast column.With the cylinder sawing, the moulding that lift and be polished to 5～6 inches circular wafer, can be cut to square wafer thereafter.For example carry out wet chemical etching with texture among the KOH at alkaline chemical then.Utilize POCl
3Furnace diffusion forms p-n junction.Utilize PECVD SiON to carry out the anti-reflective film passivation then.The silver-colored muddle of silk screen printing is layed onto the n-profile and the aluminium muddle is layed onto the p-profile.This paste of sintering electrically contacts with formation then.At last, test battery and classify according to their characteristic such as their I-V curve.
Above-mentioned technology is well-known in the industry and has implemented for many years.Yet; Though most of cost (promptly in semiconductor; Be worth) be that the silicon wafer with polishing converts the process of functional integrated circuit into, but in solar cell was made, the process that the wafer after the polishing is changed into functional solar cell was lower than the process cost of producing polished wafer self.That is to say that on commercial significance, the process that silicon wafer is transformed into solar cell is not the step of high additive value in whole solar panel manufacturing chain.Therefore, opposite with the battery manufacturing technology-in any improvement aspect the cost of making initial wafer or reduce the price of final solar panel will be reduced significantly.
In order to overcome the problem of the silicon raw material that is used for solar cell, be devoted to reduce the silicon amount of every watt of consumption of solar cell energetically along two main approach.These are:
With wafer thickness from 500 μ m of standard be reduced to～below the 200 μ m.This approach receives the restriction of die strength, and the wafer trend is broken during high speed is through process equipment.
2. adopt the for example film of silicon, CdTe, CuInGaSe of various solar cell materials, typically on glass and on other more cheap substrate.In order to make rayed on solar cell, electrode it-by the transparent oxide (CTO) of conduction InSnO for example
xPerhaps ZnO
2Constitute.
In various thin film solar cell materials, silicon is the material of most cost effective equally.In this solar structure body, wafer thickness is reduced to about 1～10 μ m from 300～500 μ m.In this 1～10 μ m, the thickness of the film of most of deposition typically is made up of unadulterated Si-H polymer intrinsic amorphous layer, is abbreviated as the ia-Si:H layer.Being clipped in this i aSi:H layer between doped n-type a-Si:H and the p-type a-Si:H film provides and is absorbed into the required volume of shining sun light, thereby produces electron hole pair therein.These charge carriers n-and p-electrode of being diffused into solar cell produces the photovoltaic voltage and current that is used to generate electricity then.Yet, because the IR wavelength of solar spectrum has the long transmission depth through silicon, thus a large amount of solar radiations lost, thus reduced the efficient of photovoltaic conversion.That is to say, lost the quantum efficiency of conversion, special in the longer wavelength in infra-red range.Another inherent limitation of membrane structure is that the thickness limits of the diffusion length tunicle of minority carrier arrives much smaller than 10 μ m.This is the quality factor of the solar battery efficiency of prediction finished product.For pure crystalline silicon based solar battery, diffusion length typically is about 80 μ m.
There is the limitation of other essence in thin-film solar cell structure, surpass 80% of total solar panel market with solar cell and compare based on silicon wafer, so far these limitation with the thin film solar cell production restriction about 5%.Part is as follows in these limitation:
1. because identical, promptly be used to deposit silane gas underproduce of a-Si:H film, the cost fast rise of the gas that this very easily fires with the price of polysilicon.Except that silane, be used to produce a large amount of special NF of plasma-enhanced CVD reactor needs of solar energy film
3The original position plasma that gas is carried out the PECVD reactor purifies long with the normal operating time of guaranteeing production equipment.
2. the photovoltaic conversion efficiency of thin film silicon solar cell is low, sometimes half the less than based on the solar cell of silicon wafer.
3. set up the required permanent plant of thin film solar cell factory and be used for energy output suitable based on nearly 10 times of the solar cell factory of silicon wafer.Basic charge mainly by be used to deposit a-Si:H and SiN passivating film based on the plasma CVD reactor of vacuum and the PVD reactor that is used to deposit the CTO film based on vacuum promote.
As can be by the above-mentioned that kind of understanding; Line of solar cells is already through being divided into two camps: to manage to utilize the HIGH-PURITY SILICON wafer to obtain the solar cell camp based on silicon wafer of high battery efficiency, and to avoid using the film camp of silicon wafer in order reducing cost.Therefore, receive the restriction of pure silicon wafer availability based on the camp of silicon wafer, and the film camp receives the restriction mainly due to the conversion efficiency that incomplete absorption caused of light in the glass substrate, and receive the thicker required SiH of intrinsic silicon hydride absorbed layer of production
4The restriction of the cost of gas.
Summary of the invention
Basic comprehension and characteristic for aspects more of the present invention are provided comprise following summary of the invention.This general introduction is not an extensive overview of the present invention, because of rather than intention is special distinguishes key of the present invention or important key element or describe scope of the present invention.Its unique purpose is to provide principles more of the present invention with the form of simplifying, as prelude in greater detail given below.
Various execution mode of the present invention provides the gasification that need not to carry out silicon to make the method for silicon substrate.Therefore, avoided the cost and health and the environmental hazard that in making the silicon of nine nine grades, relate to.This substrate can be used to make the solar cell that efficient is suitable with thin film solar cell even surpass.
Characteristic of the present invention has solved the following major issue more than that the solar cell industry faces:
A) be used for the availability and the cost of " (solar capable) with solar energy ability " silicon materials of wafer and film
B) be used for the investment cost of solar cell factory
C) every watt of following solar cell required cost.
D) be used for the scale property of the production technology of big volume
E) reliability of environmental suitability and 25 years
Characteristic of the present invention makes it possible to obtain the productive solution to the problems referred to above, especially makes an investment in the solar battery structure of benefit of conversion efficiency and the hull cell structure of body silicon wafer through manufacturing.According to aspects of the present invention, make thin film solar cell as substrate and on this substrate, make solar cell through utilizing the silicon wafer of processing by the extremely low metallurgical grade silicon of cost.According to characteristic of the present invention, much thin that (for example, 10%) film is made battery through the conventional thin film solar cell of deposition rate.Except that the cost that reduces substrate and membrane material, the structure of suggestion allows the conversion efficiency above the raising of conventional thin film solar cell.That is to say that through utilizing the metallurgical grade silicon wafer, the manufacturing of substrate becomes and endangers less and more environmental protection, also reduces the cost of substrate simultaneously.In addition, utilize the metallurgical grade silicon wafer, improved conversion efficiency with comparing at the membrane structure of formation on glass as substrate, because said silicon wafer has formed light absorbing medium, rather than the thin i-Si layer of conventional hull cell.
The invention discloses a kind of method of utilizing metallurgical grade silicon to prepare substrate, this method comprises: make metallurgical grade silicon fusion in smelting furnace; Make the metallurgical grade silicon after the fusion be solidified as ingot casting; Ingot casting is cut into slices to obtain a plurality of wafers; Two surfaces of each wafer of etching; On the back side of each wafer, deposit aluminium lamination; Depositing hydrogenated silicon nitride layer on the front of each wafer; At high temperature said wafer is annealed; Remove the silicon nitride of hydrogenation and do not disturb said aluminium lamination; And on the front of wafer the deposit film structure.In the deposition process of the silicon nitride layer of hydrogenation, when hydrogen got in the substrate, back side aluminium lamination had formed sealing.In annealing process, aluminium lamination has formed the good Ohmic contact with said chip back surface, and thus, in case form device in the front of this wafer, aluminium lamination just can be used as back side contact layer.
A kind of method of utilizing metallurgical grade silicon to prepare substrate comprises: the wafer that acquisition is made up of levels of metal silicon; On said wafer, carry out preparatory etching (conditioning etch); Deposition of sacrificial layer on the front of said wafer; Plated metal layer on the back side of said wafer; At high temperature said wafer is annealed; And remove sacrifice layer and do not disturb said metal layer.
A kind of method of utilizing metallurgical grade silicon to prepare the used for solar batteries substrate comprises: the wafer that acquisition is made up of levels of metal silicon; On said wafer, cut damage and remove etching (saw damage removal etch); On said wafer, clean etching; Depositing hydrogenated sacrifice layer on the front of said wafer; Plated metal layer on the back side at said wafer under first high temperature; Said wafer is annealed being higher than under second high temperature of first high temperature; And remove the sacrifice layer of hydrogenation and do not disturb said metal layer.
According to a further aspect of the present invention, a kind of method of utilizing metallurgical grade silicon to prepare solar cell is provided, this method comprises: the polycrystalline grain wafer that forms metallurgical grade silicon; Make the crystal boundary passivation on the front of each wafer, and collect impurity (getter impurity) from the back side of said wafer; And on the front of each wafer, form solar battery structure.Suppressing crystal boundary can comprise with collection impurity: the surface of the said wafer of etching; Sputtered aluminum layer on the back side of said wafer; On the front of said wafer, deposit Si
3N
4Make said wafer annealing; And peel off the Si that has deposited
3N
4Layer and do not disturb this aluminium lamination.Before sputtered aluminum layer, can deposit p-type layer overleaf.In addition, at deposition Si
3N
4Before the layer, can also be on the front n-type layer of deposited amorphous.The formation solar cell may further include: deposit the n-doped layer at deposition intrinsic amorphous silicon layer on the front of said wafer with on this intrinsic amorphous silicon layer.Said intrinsic amorphous silicon layer and n-doped layer can be hydrogenation.
According to a further aspect of the present invention, a kind of solar cell is provided, comprises: have the positive metallurgical grade silicon substrate of the back side and texturing; Be formed at the contact layer of back layer; Be formed at the intrinsic amorphous silicon layer on the front; Be formed at the n-type silicon layer on the intrinsic amorphous layer; With the ITO that is formed on the n type layer; And be formed at the preceding contact layer on the ITO.
Description of drawings
According to the detailed description with reference to attached drawings, it is clear that others of the present invention and characteristic will become.Should be understood that detailed description and accompanying drawing provide the various non-restrictive example of the various execution modes of the present invention that are defined by the following claims.
Be attached in this specification and constitute its a part of accompanying drawing and for example understand execution mode of the present invention, and play the effect of explaining and principle of the present invention being described together with describing.The accompanying drawing intention is with the characteristic of the execution mode of illustrated mode illustrated example property.Accompanying drawing is not that intention is described each characteristic of actual execution mode or the relative size of the element described, and not drawn on scale.
Fig. 1 is the flow chart of explanation according to the technology of one embodiment of the present invention.
Fig. 2 explanation is according to the technology of one embodiment of the present invention.
The technology of Fig. 3 explanation another execution mode according to the present invention.
Fig. 4 explanation is according to the technology of one embodiment of the present invention.
Fig. 5 A explains another embodiment of the invention, and Fig. 5 B representes the distortion of this execution mode.
Fig. 6 A explains another embodiment of the invention, and Fig. 6 B representes the distortion of this execution mode.
Fig. 7 explains another embodiment of the invention.
Fig. 8 explains another embodiment of the invention, and it is similar to the execution mode of Fig. 7, except dopant is put upside down.
Fig. 9 A explanation is used for making common this paper and is called SmartSi
TMThe implementation of processes example of ready used for solar batteries substrate (a solar-cell ready substrate).
Fig. 9 B explanation can be used for the SmartSi wafer is converted into the implementation of processes example of SmartSi PV solar cell.
The complete solar cell that Figure 10 explanation is made according to the embodiment of the present invention.
The execution mode of Figure 11 A and the many knots of 11B explanation SmartSi solar cell.
Figure 12 A and 12B explanation have the execution mode of many knot SmartSi solar cells of diffused junction.
Figure 13 A and 13B explanation two sides is clipped in the execution mode of the balanced configuration of the metalluragical silicon substrate between the Si:H film that i-Si/ mixes.
Figure 14 A and 14B explanation are according to the metalluragical silicon wafer preparation method that substitutes of embodiment of the present invention.
Figure 15 explanation utilizes the metalluragical silicon wafer to make the alternative method of solar cell according to embodiment of the present invention.
Figure 16 A～16F explanation is carried out texturing and pretreated method according to embodiment of the present invention to substrate surface.
Figure 17 A～17E explanation is carried out texturing and pretreated alternative method to substrate surface according to the embodiment of the present invention.
Embodiment
Execution mode of the present invention is provided for the low-cost method of making solar cell, reduces related health and environmental hazard in the conventional solar cell manufacturing simultaneously.As pointing out on the solar energy website of USDOE: " will be as the semi-conducting material in the solar cell, silicon must be purified to 99.9999% purity " (can on http://wwwl.eere.energy.gov/solar/silicon.html, obtain).This is commonly called 6N or solar energy level silicon, SoG Si.Opposite with conventional wisdom, the present invention provides the metallurgical grade silicon MG Si that utilizes purity 3N～5N to produce the method for substrate and solar cell.Various execution modes disclose the benefit of combination silica-based solar cell and thin film based solar cell to provide conversion efficiency about battery more than 14%.
Fig. 1 is the flow chart of explanation according to the technology of one embodiment of the present invention.In Fig. 1, this technology starts from step 100, through producing the metalluragical silicon particulate material with the graphite reduction quartz.The purity level of gained can be 99.9% or 99.999% purity, and promptly about three nine are arrived about five nine purity.It should be noted that quartz obtains easily at low cost.In addition, this technology has been omitted gasification step, thereby has avoided the dangerous process of gasification and production of silane.
At next step in 200, particle fusion in big square or circular mould, is for example taken advantage of 1 meter for 1 meter, and made liquid slowly be frozen into the cylinder with big silicon crystal grain.Randomly, the cylinder remelting that will solidify, portions is solidified then, so that impurity is moved on to a cylindrical side.Along continuous straight runs control cooldown rate and temperature gradient in this process are so that make impurity move to cylindrical surface and the top of (for example, mould is reduced to be lower than smelting furnace lentamente) solid of impurity being concentrated on obtain vertically.In step 200, randomly contain 1E17～1E18cm with production with this molten silicon of small amount of boron doping
-3The p-Si of boron.In step 300, cutting is solidified cylindrical periphery and is had the layer of a large amount of impurity with removal, and produces square body.In step 400, this square body is cut into ingot casting, for example 16 square body ingot castings.In step 500, for example use diamond or wire saw that each ingot casting section is about 20 mils, i.e. 0.020 inch thick Si wafer.Can collect waste material reuses in fusion.
Fig. 2 explanation is according to the technology of one embodiment of the present invention.This technology starts from by " dirty " silicon, i.e. the wafer DSi 200 that processes of 3～5 nine metalluragical silicon obtaining of the technology of the execution mode through Fig. 1 for example.Utilize for example PECVD, deposition concentration is 1.0E16 atom/cm on the end face of wafer 210
3The n-layer.On this n-type layer 210, SiN layer 220 is provided with plasma chamber then.Be utilized in the POCl under the temperature that is higher than 900 ℃ then
3Processing is extracted impurity the molten glass layers 230 from DSi layer 200.This has improved the purity of p-type layer 200, around the knot that forms especially before this.Yet adopt the etch processes peel ply 230 after the for example chemico-mechanical polishing (CMP).This has removed and has contained the layer 230 that extracts from the impurity of layer 200.Silver contact 240 is set on n-doped layer 220 at last, and aluminium electrode 250 is provided on layer 200.About 700 ℃, make total body annealing then, make silver electrode to n-type layer 210 and make 250 pairs of p-types of aluminium electrode layer 200 accomplish low-resistance ohmic contact.
The technology of Fig. 3 explanation another execution mode according to the present invention.This technology starts from step 100, the thick amorphous silicon layer of distillation 2 μ m from the crucible that contains metalluragical silicon.This will carry out being lower than under the Ar background vacuum pressure of about 10E-6 holder under 1000～1200 ℃ of silicon fusing point.This step is confirmed purer active junction layer, because do not distil at 1200 ℃ of following any carbon and metal impurities.In addition, a spot of residual oxygen helps to promote distillation through on crucible surface, forming a small amount of silicon monoxide in the argon gas background environment.In step 200, at O
2Add N
2Or under the environment of Ar wafer is exposed to and contains P gas such as POCl
3Or PBr
3This step is through Doped n-profile and make B be able to form the silicon layer after " dirty " substrate is out-diffusion to clean distillation p-n junction.
Yet etching or CMP (chemico-mechanical polishing) are carried out to remove the glass of any Doping Phosphorus in the back side of this wafer in step 300.Secondly, in step 400, plasma is used for front (n-type) the deposition SiN anti-reflective film at this wafer.In step 500, form contact, for example, available laser comes to be contact boring.In step 600, make conductive electrode, for example, can adopt silk screen or other method to stick with paste to limit electrode at the front and back plated metal.Contact to form at 600 ℃～700 ℃ following sintering wafers then.Through silk screen with deposition of silver on the SiN anti-reflective film and do not pass under the situation of contact hole of any laser drill of this layer, utilize higher temperature to make silver be able to pass whole SiN layer.
Fig. 4 explanation is according to the technology of one embodiment of the present invention.This technology is from 400 beginnings of dirty p-type silicon wafer.Utilize evaporation process on wafer 400, to produce the SiOx layer 410 of evaporation then.N-type layer 420 (this can partly be diffused in this layer 410 through the Si layer of dopant deposition phosphorus or through other acceptable method and carry out) is provided on SiOx layer 410.Use layer 430 sealant 410 then, utilize gettering (gettering) that impurity is drawn the layer 400 to provide purity to improve to the bottom 440 of wafer 400.Can before the deposition lead, remove this bottom 440 then.
According to another execution mode, at first the dirty silicon wafer of etching is to provide texture on its end face.Then at POCl
3Handle this wafer in the stove to form the p-n junction of this wafer.Cover the end face of this wafer with the SiN layer of plasma deposition.Then this wafer is exposed to POCl once more
3Whole metal impurities being received (getter) back side, and make this knot sclerosis avoid spilling.Remove the glass on the chip back surface through for example back etched then.Utilize for example laser drilling or contact etch to form contact hole then.Utilize conventional technology to form Metal Contact then.If not, the silver that directly on the nitride layer of plasma deposition, forms silk screen is stuck with paste, and then～700 ℃ of annealing down, makes silver be diffused into the layer near the Doping Phosphorus at wafer top, and does not use any contact hole.
In case it should be noted that to form metallurgical Si p-n junction, because the metal impurities in the junction interface very easily spill.POCl
3An effect be to form the n-layer, impurity is drawn to the near surface that forms knot.Therefore, in order from the knot in front, metal impurities to be moved on to the back side of wafer, carry out the 2nd POCl in this embodiment
3Step is simultaneously with the active front of SiN protection.Metal is concentrated in the glass of the watery fusion on the chip back surface, remove through chemical etching or CMP then.
Replace silicon substrate, people can use by stainless steel that is coated with distillation Si or the substrate that glass is processed, and form p-n junction through from centrifugally cast B, P glass, being diffused in this substrate.This is different from and is used for dull and stereotyped application of thin-film transistor and the amorphous PECVD silicon of deposition, because the film of distillation does not have any captive hydrogen.Therefore, when High temperature diffusion step subsequently, they do not decompose.The PECVD film lost efficacy in time, maybe be because the composition relevant with the H desorb changes.
Fig. 5 A explains another embodiment of the invention.The raw material that is used for the execution mode of Fig. 5 A is through casting, and slowly the purity made of cooling is about three 9 to five 9 i.e. low-cost polycrystalline metalluragical silicon wafers of 99.9% to 99.999% subsequently.Metalluragical silicon is easily by quartzy (SiO
2) make based on the chemical reaction of smelting furnace with graphite (C), the two is present in the mine all over the world.These two kinds of materials are the purer form of sand and coal basically.Graphite can enough oil accessory substance or organic plant material that other comprises pure C replace.Make metallurgical silica flour fusion, the P and/or the B that in melt, add test volume as required are to produce about 5E17 atom * cm
-3P-type concentration of dopant.Slowly cooling is to produce the cylindrical ingot casting of siliceous poly grains to make melt, and the impurity that contains about 10ppm is Cr, Fe, Ni, Mn and C for example.Regulate cooling procedure so that make Impurity Distribution in the sedimentary cluster of what is called.Their trends are electroactive less than even distribution atom, and the latter typically occupies substituted electroactive site on the silicon crystal lattice.Substituted impurity plays the trap that is used for electron-hole recombinations or the effect at center, this compound photovoltaic conversion efficiency that is considered to reduce through the diffusion length that reduces charge carrier in the light absorbing zone solar cell.The light that has functional relation through well-known test and light wavelength converts the physics method of the quantum efficiency of electric charge carrier into can estimate diffusion length.With the material of casting, promptly ingot casting is processed into less cylinder, is sawn into wafer, etching to be to remove surface damage, operates on the one or both sides according to the industry of standard then and polishes.The metallurgical grade wafer that this will obtain is as the substrate of producing solar cell.Do not resemble the conventional used silicon substrate of polysilicon solar cell, this execution mode need not use usually by gas phase SiH
xCl
ySeven 9 of making of compound reduction or high-purity polycrystalline more.
Substrate 500 cleans through pre-deposition, and typically relate to 100: 1HF removes any natural oxide, uses NH
4OH/H
2O
2Remove organic pollution, remove any metal impurities with HCl then.This step can also comprise the described cutting damage removal etching of any position of this paper.Under the situation that does not have impurity gas to exist, be utilized in SiH then
4And H
2In the plasma that produces in the PECVD of standard equipment, apply as thin as a wafer (
), typically be lower than
The unadulterated amorphous Si:H of intrinsic layer 505.Next, the a-Si:H layer 510 that mixes through deposition n-forms the active parts of tying, and this can carry out in same apparatus easily, contains SiH but utilize
4And H
2And PH
3Plasma.This is for example ZnO of transparent conductive oxide 520 subsequently
2, ITO or InSnO and if desired by SiO
xN
yThe pantostrat of the anti-reflective film 515 that constitutes.These form top electrode, can daylight be transferred to silicon absorbed layer body through this electrode.For extra charge collection efficiency, can on this transparent conductive oxide layer 520, form typically and stick with paste a series of electrodes that constitute by silver.For the low resistance contact at the battery structure back side, the paste that contains Al through PVD process deposits or silk screen printing applies Al layer 525 in the bottom surface of wafer, and sintering is to form low resistance contact then.
So the solar cell that obtains comprises following at least new feature.N-layer through deposited amorphous Si:H film on the light absorption wafer of being processed with the p-type polycrystalline metallurgical grade silicon wafer of few about ten times of the conventional silicon wafer of solar energy or the manufacturing of semiconductor grade polysilicon by cost Billy forms p-n junction.Contain the thick metallurgical p-type polysilicon light absorbing zone of 250～500 μ m that the metallurgical silica flour of B dopant makes by casting and replace adopting much expensive solar-grade polysilicon.Between metallurgical substrate of p-type and n-Si:H film, insert optional intrinsic (undoped) Si:H film intermediate layer so that because polycrystalline character and the impurity in the material typically have the surface passivation of the metalluragical silicon of fracture (suspension) key, thus improvement photovoltaic conversion efficiency.Can omit ARC layer 515 in order to practice thrift cost, the surface that replaces through etching metallurgical grade silicon in KOH makes it coarse in the crystal grain that (100) are orientated substantially, to expose (111) face.This roughening makes the light reflection minimized, so that the ARC layer can be unnecessary.
On the other hand, Fig. 5 B has explained that transparent conductive layer is also as the embodiment of antireflection (ARC) layer.Except having removed the step that forms the ARC layer, with the solar cell of the mode shop drawings 5B similar with Fig. 5 A.The substitute is, tco layer is processed made it can also be as the thickness of ARC layer.For example; In one embodiment; ITO is sputtered to the thickness of
, so that ITO forms transparent conductive layer and ARC.Can regulate the frequency band reflection of thickness of ITO to prevent wanting.What Fig. 5 B also showed is the back layer of amorphous p type, and it utilized PECVD to deposit before aluminium lamination.
Fig. 6 A explains another embodiment of the invention.The execution mode of Fig. 6 A is similar to Fig. 5, except doping is put upside down.That is to say, absorbed layer 600 is fabricated to n-type metalluragical silicon.The amorphous layer 610 of deposition has reversed polarity, promptly is used to the p-type of tying.Fig. 6 B has simulated the structure of Fig. 5 B, except utilizing n-type wafer doping is put upside down.
Fig. 7 explains another embodiment of the invention.The execution mode of Fig. 7 is similar to Fig. 5.Yet; In the execution mode of Fig. 7; Before the aluminium lamination 725 of making back side contact, make optional by a-i Si:H film 730 structure that constitutes of a-n Si:H film 735 subsequently; So that utilize heterojunction to be higher than the conversion efficiency of absorptive substrate, this heterojunction has the intrinsic passivation layer structure of the Si-H of the intrinsic as thin as a wafer layer that contains deposition, active Si-H thin layer on the electricity of reversed polarity.In this respect, for the described execution mode in Fig. 5～8, with the manufacturing sequence of parenthesized letter representation for the layer suggestion of each explanation.Fig. 8 explains another embodiment of the invention, and it is similar to the execution mode of Fig. 7, except dopant is put upside down.That is to say that substrate is designated as n-type metallurgical grade silicon, knot layer 810 is p-types, and layer 835 is n-types.
As that kind that can be understood, the execution mode of Fig. 5～8 is tied through structure film on the metallurgical grade silicon substrate solar cell is provided.Because the performance of metalluragical silicon, to compare with having as thin as a wafer the conventional hull cell of absorbed layer, this has light absorption advantage preferably.Therefore, improved conversion efficiency.On the other hand, use metallurgical silicon chip to provide and be lower than the conventional solar energy or the cost of semiconductor grade silicon wafer.In addition, as described herein through using the metallurgical grade silicon wafer, reduced health and environmental hazard.
The intention that relates to the execution mode of Fig. 5～8 is to distinguish three functions of getting in touch with PV technology, this technology at first in silicon absorbing light produce minority carrier (electronics) stream through the band gap of utilizing p-n junction then to produce electron hole pair, convert light into electric current.Usually, in the polycrystalline or monocrystalline silicon of the p-n junction structure with diffusion, two processes take place simultaneously.When from monocrystalline silicon to Czochralsky monocrystalline silicon to zone melting of the polysilicon of routine, minority carrierdiffusion length can change to 300 μ m to 100 μ m from 50 μ m.Corresponding PV conversion efficiency is about 18%, 22% and 25%.At the other end, it is absorbed layer that the thin film solar cell of deposited amorphous unijunction relies on the thick middle aSi:H layer of typically about 1 μ m.Diffusion length is arrived about 1 μ m by the thickness limits of thin layer.Corresponding PV conversion efficiency is reduced to about 6～10%.In this execution mode of the present invention, minority carrierdiffusion length does not receive the restriction of film, but is decided by the characteristic of metalluragical silicon substrate.
Embodiment 1
Through the silicon grain of two nine of induction fusings in the graphite crucible of about 1.5m * 1.5m, slowly be cooled to the cylindrical metallurgical grade silicon of producing three nine then through 24 hours.Remove the surface crust of rich carbon, and the cylinder pulverizing is crystal grain or particle.The material that obtains contains B and P, but normally has the p-type of the resistivity in 0.1～1ohmcm scope.Then the material that obtains is cast former of the metallurgical grade silicon (bole) of about 0.5m * 1m * 1m, be accompanied by control cooling and dopant and regulate.With said former block of ingot casting that cuts into 16 square sectionals, a side is less times greater than 5 ".Smooth periphery, the thick wafer of sawing 500 μ m from the ingot casting then.Face of mechanical polishing, two faces of slight etching are to expose the big grainiess of polygon on chip back surface.This produces about 500 metallurgical grade silicon wafers of four nine and five nine purity.Utilize 4 point probes to measure wafer is divided into two groups, main group has the resistivity of 0.3～0.5ohmcm, and remaining is at～1ohmcm.The SIMS of 4N and 5N material forms distributional class seemingly, has IE14 atom cm
-3Transition metal impurity concentration.Metal impurities typically are those relevant with metalluragical silicon, i.e. Fe, Cr, Mn, Co, Ni, Cu.In addition, there is IE15 atom cm
-3Concentration of carbon.
Sample with wafer is made solar cell.Containing suitable doping gas PH
3And B
2H
6SiH
4, H
2In utilize the rf plasma, with PECVD (plasma reinforced chemical vapour deposition) equipment deposition i type a-Si:H film, p type a-Si:H and n type a-Si:H film.Adopt PVD (plasma gas-phase deposit) sputtering equipment deposition approximately
In
xSn
yO
z, with the transparent conductive oxide that acts on top electrode and hearth electrode.Adopt the dark silicon tableland (silicon mesas) of the about 10 μ m of etching machines etching to produce the diode of isolating with the wafer remainder.Utilize this technology,, produce the single heterojunction of intrinsic passivation layer structure, and measure the diode I-V and the quantum efficiency of passing this spectral region of this knot with the p+ back of the body contact that contains diffusion since 0.1 Ω cm p-type (100) metallurgical grade silicon wafer.Utilize the curve of 1/QE contrast λ wavelength, slope provides diffusion length L by μ m.Length L and I
DsatIt is the predictor of well-known PV conversion efficiency.This structure provides the I of 400mA
DsatWith the length L of 80 μ m, the PV conversion efficiency corresponding to about 20%.The structure that on 0.4 Ω cmp-type metallurgical grade silicon wafer, forms is also worked finely, has minority carrier (electronics) the diffusion length L of 7 μ m
e, corresponding to 12～13% PV conversion efficiency, putative structure has the series resistance of excellent control.The structure that on 1.0 Ω cm p-type metallurgical grade silicon wafers, forms is also worked finely, has minority carrier (electronics) the diffusion length L of 8 μ m
e, corresponding to 14% PV conversion efficiency, putative structure has the series resistance of excellent control.
Embodiment 2
Through in the front being " device " side depositing nano level Si:H film stack and the a-Si:H film of " contact " side sedimentary facies contra-doping overleaf, formation contains the single heterojunction of intrinsic passivation layer device architecture on metallurgical grade substrate cheaply.The metallurgical grade substrate needn't be thinned to 250 μ m from 500 μ m with substrate especially as crystallization Si substrate is done, exempted loss.Thicker wafer provides more firm operation in automatic assembly line.This material also avoided based on polysilicon gasification, solidify, cost, cycle and the complexity of fusion and czochralski process because through being produced this active device by the thin Si:H film outside the metallurgical grade real estate of nanoscale intrinsic a-Si:H film passivation just.
The metallurgical grade substrate can form for for example 6 inches, 8 inches, 12 inches by the size of standard, can in the semiconductor PECVD of standard process equipment, process.On the contrary, large tracts of land (usually, 4 * 6ft or 6 * 7ft) the solar cell that produces conventional based thin film on glass, this needs the special big chamber of internal capacity, causes being difficult to be extracted into low pressure and causes being used to form the active gases waste of thin layer.Therefore, these PECVD reactors are bought costliness and because the high running costliness of running stores (that is the active gases of, discarding) cost.The high internal capacity of the chamber that these are special also causes depreciation difficulty and cost.Otherwise, can in the little standard reaction device of internal capacity, carry out at formation film on the standard-sized wafer, so that the problem of running and depreciation is minimum.Because than the order of magnitude of long minority carrierdiffusion length, the structure of thin film device that on the metalluragical silicon substrate, obtains has the PV efficient greater than the about twice of thin film solar cell of routine in the metalluragical silicon substrate.
Embodiment 3
Fig. 9 A explains among common this paper and is called SmartSi
TMAn embodiment of technology who is used to make ready used for solar batteries substrate.In step 900, in the electrolysis tank of graphitiferous electrode,, let its cooling and solidifying then so that about two nine metalluragical silicon ingot casting to be provided with quartzy fusion of metallurgical grade and reduction.Ingot casting is broken into particle, in chemicals, handles, cast ingot casting then to leach surface impurity.Peel off the shell of ingot casting then and be broken into three to five nine metallurgical silico briquette.The piece that obtains is according to their resistivity classification.
In step 915, the MG silico briquette of classification is cast.Make melt solidifying become former, processing is cut into ingot casting, and is sliced into the for example wafer of 350 micron thick in step 920.In addition, also each wafer is carried out etching and be used for the further surface of the wafer of processing to remove the cutting damage and to clean and prepare.In addition, in this step, can also carry out texturing etching (texture etch) so that the positive texturing of each wafer.In step 925, form the front of intrinsic amorphous silicon thin layer i-a-Si:H with passivation MG-Si substrate with the PECVD chamber.In step 930, on passivation layer, form n-type layer n-a-Si:H with the PECVD chamber.At this moment, produced " SmartSi
TM" or
Wafer 935 makes it possible to anywhere use seldom investment, more a spot of simple and mechanical and few technological know-how in fact to form the PV solar cell industry in the world.That is to say, as that kind that can be understood, for the SmartSi wafer is converted into solar cell needed all are the contacts of making front and back.This adopts existing silk screen printing or printing technology easily to carry out.In addition, shown in mark, can carry out another step 930 of PECVD ' with the back side at substrate form p-type layer 935 ', so that improve contact to the subsequent conductive layer.
Fig. 9 B explanation can be used for the SmartSi wafer is converted into an embodiment of the technology of SmartSi PV solar cell.As stated, needed is in the back side of SmartSi substrate and front, to form to contact.As for the front, a kind of method is the metal grill that forms conduction.Usual way is the grid that design has the many thin conductive contact that spreads to each part of battery surface.The contact of grid must be enough wide with good conductive (having low resistance), but want enough narrow in order to avoid block a large amount of incident lights.This grid keeps low resistance loss, only covers about 3% to 5% of battery surface simultaneously.The end face grid can be made up of for example aluminium, silver or molybdenum, through on the battery through mask plated metal steam, on battery, smear them, perhaps with the highest performance being provided but the highest photoetching process of cost through the reticulated printing method.
That alternative metal grill contacts is transparent conductive oxide (TCO) layer, for example tin oxide (SnO
2) or be commonly called the tin indium oxide of ITO.The advantage of TCO is that they almost are sightless to incident light, and they form the good bridge joint from the semi-conducting material to the external circuit.Execution mode shown in Fig. 9 B utilizes TCO as the contact to battery front side.In step 940, utilize PVD technology to form tco layer.In step 945, adopt silk screen, printing etc. on the front, to utilize the for example micro-metal paste of describing with the front contact metallization.In step 950, employing silk screen, printing etc. are utilized in the for example metal paste of describing on the back side (for example, silver is stuck with paste) perhaps makes back side contact metallization to form collector electrode through sputtered aluminum on the back side of substrate or other metal.When using paste, shown in step 955, be desirable in order to form this wafer of good Ohmic contact sintering with the front contact metallization.According to conversion efficiency wafer is classified then, so that produce SmartSi PV battery 960.
In above-mentioned all execution modes, before forming any layer, can be through for example making the etching of MG Si substrate make one of which or two faces by texturing at alkaline solution such as potassium hydroxide solution.Can wash this substrate then, and make its drying through for example heating this substrate.In addition, can reduce the carbon amount on the substrate surface with the plasma discharge of hydrogen.Can in the PECVD chamber, adopt and hydrogen (H
2) the silane gas (SiH that mixes
4) form the intrinsic amorphous silicon thin layer.Can in the PECVD chamber, adopt silane, hydrogen and phosphine gas (PH
3) form n-type amorphous silicon thin layer.Can in the PECVD chamber, adopt silane, hydrogen and Boroethane gas (B
2H
6) form p-type amorphous silicon thin layer.
The complete solar cell that Figure 10 explanation is made according to the embodiment of the present invention.On metallurgical grade silicon substrate 1000, form solar cell, this substrate is doped p-type in the present embodiment.Form intrinsic amorphous silicon layer 1005 at end face then, form n-type amorphous silicon layer 1010 subsequently.On n-type layer, form tco layer 1020, and on TCO, form the for example silver-colored contact 1025 of contact to form good Ohmic contact.For example can using, aluminium forms back of the body contact.This moment, battery was accomplished also available; Yet, avoid the element influence in order to make it, carry out following further processing.The front receives the protection of optional resin film layer 1015, and for example ethene-vinyl acetate copolymer is followed by glass 1045.Resin molding 1035 also can be used in the back side, glass or other protective layer 1040 are protected subsequently.
Shown in Fig. 9 A and 9B, can make the SmartSi wafer with the execution mode of top discussion, can wafer further be processed to make the SmartSi solar cell.According to another aspect of the present invention, in order to improve the photovoltaic conversion efficiency, can further process the SmartSi solar cell and make many knot SmartSi solar cells with a plurality of band gap.An execution mode of the many knots of explanation SmartSi solar cell in Figure 11 A.In Figure 11 A, metallurgical grade silicon substrate 1100 is doped p-types.The end face of this p-type substrate is by 1105 passivation of intrinsic amorphous silicon thin layer, and this amorphous silicon has dispersion wherein and occupy the hydrogen atom of silicon dangling bonds.This is called as silane sometimes.Shown in above-mentioned SmartSi solar cell execution mode, on intrinsic layer 1105, form the thin layer 1110 of n-type amorphous hydrogenated silicon, thereby form p-i-n knot.Originally the n-type of seeking peace layer 1105 and 1110 than the thin layer relative thin of typical conventional thin film solar cell many, in this execution mode, the first film structure needn't play absorber of light, but in the metalluragical silicon substrate absorbing light.
In order to improve the conversion efficiency of SmartSi solar cell, on the SmartSi solar cell, form conventional thin film solar cell p-i-n structure now.At first, on the SmartSi solar cell, form film p-type amorphous hydrogenated silicon layer 1120.On p-type layer 1120, form film intrinsic amorphous hydrogenated silicon layer 1125 then, and on this intrinsic layer 1125, form film n-type amorphous hydrogenated silicon layer 1130.Intrinsic layer 1125 plays another absorber of light and produces electron hole pair, thereby converts light into electric energy.In order to collect electric energy, on n-type layer 1130, form top transparency electrode ITO 1135, on ITO 1135, form Metal Contact 1140 then.Here Metal Contact 1140 is made from silver, and for example adopts silver to stick with paste, and this structure of sintering is to form good Ohmic contact then.In addition, form metal electrode 1145 in the bottom of substrate 1100.Here contacting 1145 is formed from aluminium.Figure 11 B explains similar multijunction structure, except the polarity reversal with layer.
Figure 12 A and 12B explanation have the execution mode of many knot SmartSi solar cells of diffused junction.The execution mode of Figure 12 A and 12B is substantially the same, except the polarity reversal with layer.Therefore, only the execution mode of a kind of Figure 12 of the being A in them is described.In Figure 12 A, make metalluragical silicon substrate 1200 according to aforesaid execution mode, and it is doped n-type.Then, the top layer diffusion that makes substrate is to form p-type diffusion layer 1260.This forms p-n junction and solar cell is provided in the metalluragical silicon substrate transition region is similar to the silica-based solar cell of standard.On the p-type layer of diffusion, form the thin passivation layer 1205 of intrinsic amorphous hydrogenated silicon then.On this intrinsic layer 1205, form n-type amorphous hydrogenated silicon layer 1215, consequently layer 1215,1205 and 1260 forms and has the p-i-n knot that is different from the band gap of p-n junctions in the substrate 1200, so with different frequency absorption light.On layer 1215, form conventional film p-i-n knot through forming p-type amorphous hydrogenated silicon layer 1220, intrinsic amorphous hydrogenated silicon layer 1225 and n-type amorphous hydrogenated silicon layer 1230 then.In this structure, when the time spent of doing of 1225 absorber of light of intrinsic layer, it has the thickness far above intrinsic layer 1205.In addition, this film p-i-n structure have with its under the structure different band gap, therefore with different frequency absorption light.Therefore, through carefully selecting the thickness of layer, people can " adjust " this structure with in wide frequency range absorbing light.
Figure 13 A and 13B explanation two sides is clipped in the execution mode of the balanced configuration of the metalluragical silicon substrate between the Si:H film that intrinsic Si/ mixes.Figure 13 A and 13B are enantiomers each other, except the polarity reversal with layer.Therefore key-drawing 13A only.In Figure 13 A, p-type metalluragical silicon substrate 700 has the last intrinsic layer 705 and following intrinsic layer 730 as passivation layer rather than absorber.On intrinsic layer 705, form the thin layer 710 of n-type amorphous hydrogenated silicon then, and on intrinsic layer 730, form another n-type layer 735.As described, form contact 720 and 725 then with respect to other execution mode.
The preparation of the metalluragical silicon wafer that Figure 14 A explanation substitutes according to the embodiment of the present invention.At step 1400A,, and make it to be frozen into former with metalluragical silicon particle or powder fusion in mould.Said former can be foursquare, is determined as for example one square metre, and thickness is about 25 centimetres.In this technology, can control cooling rate and temperature gradient in the horizontal direction, so that impurity moves to former outer surface.In addition, can also in heater, mould vertically be reduced, so that impurity concentrates on former end face.Randomly, former remelting will solidifying divides along the cross section then and solidifies, so that impurity is moved on to a cylindrical side.At step 1405A, former sawing will solidifying becomes several ingot castings with desirable cylindrical shape (square or dead square cross section) (for example 16 ingot castings).At step 1410A, each ingot casting sawing is become wafer.At step 1415A, as required each wafer is polished and cleans.At step 1420A, utilize for example PVD technology, with the back side of aluminium layer deposition at each wafer.Can be at high temperature, for example 200 ℃～400 ℃, with sputtered aluminum to wafer.At step 1425A, utilize for example pecvd process, H:SiN is deposited upon the front of each wafer.This step can be accomplished down for for example 200 ℃～400 ℃ at high temperature.At step 1430A, wafer is annealed at for example 400 ℃～700 ℃.In this step, a large amount of hydrogen is got in the wafer, and aluminium lamination is guaranteed hydrogen is captured in the wafer.At step 1435A, utilize for example wet etching removal H:SiN layer, and, also utilize for example wet etching removal Al layer in step 1440.
The preparation of Figure 14 B explanation metalluragical silicon wafer that substitutes according to the embodiment of the present invention.At step 1400B,, and make it to be frozen into former with metalluragical silicon particle or powder fusion in mould.Said former can be foursquare, is determined as for example one square metre, and thickness is about 25 centimetres.In this technology, can control cooling rate and temperature gradient in the horizontal direction, so that impurity moves to former outer surface.In addition, can also in heater, mould vertically be reduced,, and make impurity concentrate on former end face thus so that melt is upwards solidified by the bottom.That is, impurity preferentially concentrates on melt rather than solid.So when mould being reduced and bottom when beginning to solidify, impurity tends to stay in the liquid, makes former bottom have less impurity thus.In addition, boron and former solidifies faster than phosphorus, and this makes former bottom be tending towards the p type, and its top is the n type.Randomly, former remelting will solidifying, portions is solidified then, so that impurity is moved on to a cylindrical side.At step 1405B, former sawing will solidifying becomes the ingot casting (for example 16 ingot castings) in several cylindrical shapes with hope (square or dead square cross section).In step 1410B, each ingot casting sawing is become wafer.
In step 1415B, on each wafer, cut damage and remove etching.For example can utilizing, KOH, HNA etc. cut damage removal etching.For example, according to a kind of method, utilize HNA or KOH to remove 15～30 microns from each side of wafer.Remove technology for HNA cutting damage, can adopt weight ratio is 1.5: 14.4: 1.9 HF: HNO
3: acetate mixture.Remove for KOH cutting damage, can adopt about 60 ℃～90 ℃ 30% KOH mixture.Can also adopt the cleaning step of semi-conductor industry, for example RC-1, SPM, Piranha, rare HF and various combination thereof, clean wafers is with from surface removal metal and organic material.Any be deposited upon wafer before, adopt DI flushing or other dry process of Marangoni.According to a certain embodiments, each wafer at first removes organic material through the SPM cleaning and removing, and SPM is made up of the mixture about 80 ℃～100 ℃ of sulfuric acid and peroxide.Then, adopting about 60 ℃～90 ℃ 30% KOH mixture to cut damage removes.Then, in HF and HCl, remove oxide and metal.In rare HF mixture (wherein, rare HF mixture refers to about 1～4% HF solution), carry out last hydrophobic etching.After this step is Marangoni dry method step.
According to another embodiment, wafer at first removes organic material through the SPM cleaning and removing, and SPM is made up of the mixture about 80 ℃～100 ℃ of sulfuric acid and peroxide.Then, adopting about 60 ℃～90 ℃ 30% KOH mixture to cut damage removes.Then, carry out about 10 minutes standard RCA-1 (NH
4H/H
2O
2/ H
2O).Afterwards, be in rare HF and subsequently at RCA-2 (HCl/H
2O
2/ H
2O) about 10 minutes oxide etching in.Then, in HF and HCl, remove oxide and metal.In rare HF mixture, carry out last hydrophobic etching.After this step is Marangoni dry method step.
At step 1420B, utilize for example evaporation or PVD technology with the back side of aluminium layer deposition at each wafer.In one embodiment, titanium lamina is PVD, and it was splashed to the back side of wafer before PVD is splashed to aluminium lamination.Titanium layer helps aluminium to adhere to the back side of wafer.According to another execution mode, before sputtered titanium or aluminium, for example utilize PECVD will with said wafer mutually the amorphous layer of homotype (, then being p-type amorphous layer for example) if wafer is the p type deposit to the back side.Can be lower than under about 350 ℃ for example 200 ℃～350 ℃ temperature deposition p-type amorphous silicon.In one embodiment, for p-type wafer, resulting structure is p-type amorphous layer, the titanium layer on the p-type layer and the aluminium lamination on the titanium layer on the back side.
At step 1425B, form sacrifice layer in the front of wafer.According to an embodiment, sacrifice layer comprises the H:SiN layer that utilizes the pecvd process deposition.According to another embodiment; Amorphous n+ layer and the H:SiN layer that is deposited on the pact
on the positive n+ layer through in front wafer surface deposition about
form sacrifice layer.According to an embodiment, in the time of deposition of sacrificial layer wafer is heated to about 200 ℃～400 ℃.The order that note that step 1420B and 1425B can be put upside down.
At step 1430B, wafer was annealed about 15 minutes to 1 hour at for example 400 ℃～800 ℃.In this step, a large amount of hydrogen gets into wafer, and aluminium lamination has been guaranteed hydrogen is captured in the wafer.In addition, suppose that some impurity transfer to aluminium lamination by chip back surface, part is received in the wafer thus.At step 1435B, for example utilize plasma etching to remove sacrifice layer for example n+ layer and H:SiN layer and do not disturb back layer.Though original position plasma and long distance plasma all can adopt, in one embodiment, adopt the long distance plasma so that " soft " etching that has seldom or do not have the example bombardment to be provided.At step 1443B, on the front of wafer, form solar device (i.e. knot).Use this method, in annealing/hydrogenation process, the metal layer at the back side is used to cover wafer.In annealing process, it also is used for part and packs up wafer.In addition,, improved with the metallization that obtains at the back side contacting under high relatively temperature, promptly obtained lower series resistance because annealing is accomplished.So in this embodiment, aluminium is not removed, but be retained on the wafer as the last back side contact of solar cell.
Figure 15 explanation utilizes the metalluragical silicon wafer of execution mode of the present invention alternatively to make solar cell.In step 1500, adopt wet equipment technology to clean metalluragical silicon wafer, the wafer that for example adopts method shown in Figure 14 to obtain.In optional step 1505, the end face of wafer is carried out texturing.Can adopt the technology that causes in the preferential attack of crystal boundary or specific crystal orientation (for example the lower direction of atomic density, for example the etching of (100) face is faster than (111) or (211)), accomplish texturing through wet type or dry-etching.Correspondingly, have facet crystal grain, its surface mainly is (111) and depression crystal boundary.This result is lower surface reflectivity, causes more incident light to be absorbed and in metalluragical silicon, produces electron-hole pair.This can be that the etching repeatedly of the native oxide after each oxidation step is accomplished through front oxidation repeatedly then.This technology can cause preferential attack at crystal boundary, makes surface-texturing.The texturing on surface helps internal light reflection to strengthen the absorptivity of solar cell.For the coverage of improving next sedimentary deposit and avoid piercing through down one deck, can be soft etching after the optional texturing step, to remove the sharp edges that causes by texturing.In step 1515, for example utilize pecvd process in the front deposition intrinsic silicon layer.If desired, can carry out preprocessing process, before deposition i-layer, to remove any native oxide in step 1510.In step 1520, for example adopting, pecvd process is deposited upon n-on the i-layer.In step 1525, for example adopt PVD technology with tco layer ITO for example) be deposited on the n-layer.In step 1530, for example adopt contact layer after the PVD process deposits.In step 1535, adopt contact layer before for example typography forms on tco layer.
Figure 16 A～16F explanation is carried out texturing and pretreated method to substrate surface according to the embodiment of the present invention.Figure 16 A～16E is the cross section of the amplifier section of substrate, and it is illustrated in the crystal grain of substrate top surface, and Figure 16 F is a vertical view of accomplishing texturing and preliminary treatment end face afterwards.The cross section of substrate top surface before Figure 16 A explanation texturing step.This can be after the step 1440 of for example Figure 14.Then, for example adopting, wet etch step makes the substrate texturing.Following technology can be used as and adopts wet etching to carry out textured example: substrate is immersed HF+ (nitric acid) HNO
3Solution; The flushing substrate; Substrate is immersed KOH or NaOH solution; The flushing substrate; Substrate is immersed HF+HCl solution; The flushing substrate; Dry substrate.Through this wet processing, it is more coarse that end face becomes, and it has more sharp-pointed peak and darker paddy, and this part is because the preferential attack of crystal boundary.This state describes in the cross section of Figure 16 B.Then, substrate can pass through photoetch and handle, and for example dry ecthing is to remove the spike on surface.The result is shown in Figure 16 C.Then, deposit SiO from the teeth outwards
2Or the thin layer of Si.Shown in Figure 16 D, deep valley naturally can be by preferential deposition, and this makes deep valley by SiO
2Cover.Then, substrate is through another etching process, to remove the SiO of deposition
2Or Si.But shown in Figure 16 E, the SiO of deposition
2Or Si is retained in crystal grain boundary.The vertical view of Figure 16 F has shown this state.Most of crystal grain of SG substrate have 211 orientations.So, adopt above-mentioned technology to eliminate crystal boundary basically, obtained substantial 2-dimension " discontinuous " crystal, the crystal grain of same orientation constitutes said crystal by having in fact, and the defective of crystal boundary is by through residual SiO after the etch processes
2Layer institute " covers " or suppresses.
Figure 17 A～17E explanation is carried out texturing and pretreated alternative method to substrate surface according to the embodiment of the present invention.This method helps to offset the defect influence of the crystal grain boundary of polycrystalline grain substrate.When using substrate, this technology is effective especially as device (for example solar cell or LED) when using metallurgical grade silicon.
Figure 17 A～17D is the cross section of the amplifier section of substrate, and it is illustrated in the crystal grain of substrate top surface, and Figure 17 E is a vertical view of accomplishing texturing and preliminary treatment end face afterwards.The cross section of substrate top surface before Figure 17 A explanation texturing step.This can be after the step 1440 of for example Figure 14.Then, for example adopting, wet etch step makes the substrate texturing.Following technology can be used as and adopts wet etching to carry out textured example: substrate is immersed HF+ (nitric acid) HNO
3Solution; The flushing substrate; Substrate is immersed KOH or NaOH solution; The flushing substrate; Substrate is immersed HF+HCl solution; The flushing substrate; Dry substrate.Through this wet processing, it is more coarse that end face becomes, and it has more sharp-pointed peak and darker paddy, and this part is because the preferential attack of crystal boundary.This state describes in the cross section of Figure 17 B.Then, deposit SiO from the teeth outwards
2Or the thin layer of Si.Shown in Figure 17 C, deep valley naturally can be by preferential deposition, and this makes deep valley by SiO
2Or Si covers.Then, substrate is through etching process, to remove the SiO of deposition
2Or Si.This etch processes, the sedimentary deposit on most of surfaces has been removed in for example dry ecthing, and has removed some spikes of surface microstructure.But shown in Figure 17 D, the SiO of deposition
2Or Si is retained in the deep valley of crystal grain boundary.The vertical view of Figure 17 E has shown this state.Most of crystal grain of SG substrate have (211) orientation.So, adopt above-mentioned technology to eliminate crystal boundary basically, obtained substantial 2-dimension " discontinuous " crystal, the crystal grain of same orientation constitutes said crystal by having in fact, and the defective of crystal boundary is by through residual SiO after the etch processes
2Layer institute " covers " or suppresses.
Should understand technology as herein described is not relevant with any device inherently with technology, and can implement through the combination of any suitable assembly.In addition, can adopt various types of common apparatus according to instruction as herein described.Can also prove that it is favourable making up the isolated plant of carrying out method step as herein described.Having described the present invention with respect to concrete embodiment, is illustrative and nonrestrictive from all aspect intentions.The many various combinations that it will be appreciated by those skilled in the art that hardware, software and firmware will be suitable for embodiment of the present invention.
Having described the present invention with respect to special embodiment, is illustrative and nonrestrictive from all aspect intentions.The many various combinations that it will be appreciated by those skilled in the art that hardware, software and firmware will be suitable for embodiment of the present invention.In addition, to those skilled in the art, considered disclosed explanation of the present invention of this paper and enforcement, other enforcement of the present invention will be conspicuous.It is exemplary that intention only is used as specification and embodiment, shows true scope of the present invention and essence through equivalent structures.
Claims (20)
1. method of utilizing metallurgical grade silicon to prepare substrate comprises:
The wafer that acquisition is made up of metallurgical grade silicon;
On said wafer, carry out preparatory etching;
Deposition of sacrificial layer on the front of said wafer;
Plated metal layer on the back side of said wafer;
At high temperature said wafer is annealed; And
Remove sacrifice layer and do not disturb said metal layer.
2. according to the process of claim 1 wherein, carry out preparatory etching and comprise from every side of wafer and remove 15～30 microns.
3. according to the method for claim 2, wherein, carry out preparatory etching and be included in the said wafer of etching in HNA or the KOH solution.
4. according to the method for claim 3, wherein, carry out preparatory etching and further comprise and remove the organic material etching and remove metal etch.
5. according to the method for claim 3, wherein, carry out preparatory etching and further comprise: in sulfuric acid and peroxide solution, carry out etching, in the solution of HF and HCl, carry out etching and in rare HF solution, carry out etching.
6. according to the process of claim 1 wherein, deposition of sacrificial layer is included in the hydride layer of deposited silicon nitride on the front of wafer.
7. according to the method for claim 6, wherein, deposition of sacrificial layer further comprises: before deposited silicon nitride layer, n-type amorphous silicon layer directly is deposited on the front of said wafer, and said silicon nitride layer directly is deposited on the said n-type amorphous silicon layer.
8. according to the method for claim 5, wherein, deposition of sacrificial layer further comprises: before deposited silicon nitride layer, n-type amorphous silicon layer directly is deposited on the front of said wafer, and silicon nitride layer directly is deposited on the said n-type amorphous silicon layer.
9. according to the method for claim 7; Wherein, With wafer doping is the p-type, and the plated metal layer comprises overleaf: p-type amorphous silicon layer directly is deposited on the back side of said wafer, with titanium layer be deposited on the said p-type amorphous silicon and with aluminium layer deposition on said titanium layer.
10. according to Claim 8 method wherein, is removed sacrifice layer and is comprised that the said front of plasma dry is to remove said sacrifice layer fully.
11. according to the method for claim 10, wherein, plasma dry comprises utilizes remote plasma source to carry out said etching.
12. according to the method for claim 11, wherein, be the p-type, and further comprise n-type amorphous silicon layer is deposited on the front of said wafer with said wafer doping.
13. the method according to claim 12 further comprises: before deposition n-type amorphous silicon layer, intrinsic amorphous silicon layer directly is deposited on the front of said wafer, and n-type amorphous silicon layer directly is deposited on the said intrinsic amorphous silicon layer.
14., further be included in and directly deposit ITO on the n-type amorphous silicon layer according to the method for claim 13.
15., further be included in ITO and go up directly formation contact grid according to the method for claim 14.
16. a method of utilizing metallurgical grade silicon to prepare the used for solar batteries substrate, it comprises:
The wafer that acquisition is made up of metallurgical grade silicon;
On said wafer, remove the cutting damnification etching;
On said wafer, clean etching;
Depositing hydrogenated sacrifice layer on the front of said wafer;
Plated metal layer on the back side at said wafer under first high temperature;
Said wafer is annealed being higher than under second high temperature of first high temperature; And
Remove the sacrifice layer of said hydrogenation and do not disturb said metal layer.
17. according to the method for claim 16, wherein, said first high temperature is selected from 200 ℃～400 ℃, and second high temperature is selected from 400 ℃～700 ℃.
18. according to the method for claim 17, wherein, depositing hydrogenated sacrifice layer is included in the silicon nitride layer of the temperature deposit hydrogenation that is selected from 200 ℃～400 ℃.
19. method according to claim 16; Wherein, With wafer doping is the p-type, and goes up the plated metal layer overleaf and comprise: p-type amorphous silicon layer directly is deposited on the back side of said wafer, with titanium layer be deposited on the said p-type amorphous silicon and under first high temperature with aluminium layer deposition on said titanium layer.
20., wherein, be lower than about 350 ℃ temperature deposit p-type amorphous silicon according to the method for claim 19.
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