CN102386094B - Method for forming bottle-type groove and method for forming bottle-type groove capacitor - Google Patents
Method for forming bottle-type groove and method for forming bottle-type groove capacitor Download PDFInfo
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- CN102386094B CN102386094B CN 201010275192 CN201010275192A CN102386094B CN 102386094 B CN102386094 B CN 102386094B CN 201010275192 CN201010275192 CN 201010275192 CN 201010275192 A CN201010275192 A CN 201010275192A CN 102386094 B CN102386094 B CN 102386094B
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Abstract
The invention provides a method for forming a bottle-type groove and a method for forming a bottle-type groove capacitor. The method for forming the bottle-type groove comprises the following steps of: providing a semiconductor substrate and forming a groove in the semiconductor substrate; forming a wet-process etching blocking layer from the top part of the groove to the side wall of the preset position, wherein the wet-process etching blocking layer is made of silicon nitride or silicon dioxide; taking the wet-process etching blocking layer as a masking film, and etching the groove into thebottle-type groove by a wet process; and removing the wet-process etching blocking layer in the bottle-type groove. In the method, the wet-process etching blocking layer made of silicon nitride or silicon dioxide is formed, so that the problem of metal pollution can be solved; an atomic layer deposition method or a low-pressure gas-phase deposition is utilized for forming the wet-process etching blocking layer made of silicon nitride or silicon dioxide, so that the technical problem that in the prior art, since the opening of the groove is smaller and smaller, the uniformity and the depth of the wet-process etching blocking layer are hard to control can be solved; and the method can be implemented in the existing reaction cavity, so that the process capability of the existing reaction cavity can be expanded.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the method that forms bottle formula groove and bottle formula trench capacitor.
Background technology
In dynamic random access memory (DRAM), capacitor is responsible for storing data, and the electric charge of capacitor stores is more many, more is difficult for affected by noise when reading data.The structure of dynamic random access memory (DRAM) capacitor mainly is divided into two kinds, stacked capacitor (stack capacitor) and slot type capacitor (trench capacitor).Slot type capacitor is extensive use of in dynamic random access memory (DRAM).
Along with development of semiconductor, dynamic random access memory (DRAM) device is more and more littler, and thereupon, the size of slot type capacitor is also more and more littler.Under the situation of dwindling at device, the storage capacity of dynamic random access memory (DRAM) is constant or higher, the electric capacity that just need guarantee capacitor is constant or higher, especially, slot type capacitor DRAM for the following technology of 100 nanometers (nm), wherein very The key factor be how to guarantee capacitor in each memory cell capacitance more than 30fF, the area that this just needs to increase the last bottom crown of slot type capacitor just increases the area of groove.
In the prior art, in order to increase the area of groove, common way is to enlarge the area that lower half part of groove is divided, and namely forms bottle formula groove, can increase the area of whole groove like this.Fig. 1 a～Fig. 1 d is the cross-sectional view that forms bottle formula groove in the prior art, and with reference to figure 1a～Fig. 1 d, the method that prior art forms bottle formula groove is:
With reference to figure 1a, Semiconductor substrate 10 is provided, form silicon nitride (SiN) layer 11 in Semiconductor substrate 10, be the described Semiconductor substrate 10 of mask etching with silicon nitride layer 11, in Semiconductor substrate 10, form groove 20.
With reference to figure 1b, form wet etching barrier layer 12 in the upper portion side wall of described groove 20 (account for whole trenched side-wall 1/7), in the prior art, the material that adopt on wet etching barrier layer 12 is aluminium oxide (Al
2O
3).Utilize chemical vapour deposition (CVD) in the detailed process of the upper portion side wall formation aluminium oxide of groove 20 to be: in reaction chamber, to feed Al (CH
3)
3(trimethyl aluminium is called for short TMA) G﹠O (O
2), make Al (CH
3)
3G﹠O (O
2) reaction generation aluminium oxide, the alumina deposit that the reaction back generates is to surface and groove 20 upper portion side wall of silicon nitride layer 11, thus formation wet etching barrier layer 12.The effect of protection upper portion side wall during the bottom of wet etching groove 20, is played below in this wet etching barrier layer 12, prevents wet etching corrosion upper portion side wall.
With reference to figure 1c, after forming wet etching barrier layer 12, utilize the upper portion side wall of wet etching erosion grooves 20 with the trenched side-wall of lower part, form bottle formula groove 30, thereby reach the purpose of the area that enlarges groove.Wherein, wet etching mainly adopts acid flux material to carry out isotropic etching, such as hydrofluoric acid.
With reference to figure 1d, after forming bottle formula groove 30, remove wet etching barrier layer 12.Be specially and adopt dry etching to remove wet etching barrier layer 12, adopt chlorine-based gas to carry out etching usually.
The bottle formula groove that above-described prior art forms, the technology of formation bottle formula groove belongs to the FEOL in the whole DRAM technology, and when forming the wet etching barrier layer, because Al (CH
3)
3(TMA) G﹠O (O
2) have metal A l ion to exist when reacting, therefore, when forming gate oxide, this metal ion will pollute gate oxide possibly, in order to control metallic pollution, when forming gate oxide, can introduce a lot of extra processing steps, with the control metallic pollution, and because the existence of metallic pollution causes the DRAM performance of final formation bad.
And, because the upper portion side wall at groove forms the wet etching barrier layer, and do not form the wet etching barrier layer at the lower sides of groove, and therefore need special reaction chamber and special technology, be formed on the upper portion side wall of groove to guarantee the wet etching barrier layer.
In addition, when forming the wet etching barrier layer, because the loading effect of aluminium oxide, along with the opening of groove is more and more littler, the uniformity on this wet etching barrier layer and the degree of depth are difficult to control.
In the prior art, have many about forming the method for trench capacitor, for example, Granted publication number is the Chinese patent disclosed " structure of slot type capacitor and manufacture method thereof " of " CN1269206C ", and publication number is the Chinese patent application of " CN1838401A " disclosed " manufacture method of doleiform groove and doleiform slot type capacitor ".Yet, all do not solve the shortcoming that exists in the above-described prior art.
Summary of the invention
The problem that the present invention solves is that the method for the formation bottle formula groove of prior art can cause the metallic pollution in the subsequent technique; Need special reaction chamber and special technology; And along with the opening of groove is more and more littler, the uniformity on wet etching barrier layer and the degree of depth are difficult to control.
For addressing the above problem, the invention provides a kind of bottle method of formula groove that forms, comprising:
Semiconductor substrate is provided, is formed with groove in the described Semiconductor substrate;
Sidewall in described groove top to precalculated position forms the wet etching barrier layer, and the material on described wet etching barrier layer is silicon nitride or silicon dioxide;
Be mask with described wet etching barrier layer, the described groove of wet etching forms a bottle formula groove;
Remove the wet etching barrier layer in the described bottle formula groove.
Optionally, described sidewall in described groove top to precalculated position forms the wet etching barrier layer and comprises:
Form first laying in the surface of described Semiconductor substrate, sidewall and the bottom of groove;
After forming first laying, fill the photoresist of first predetermined altitude in described groove, this first predetermined altitude is that channel bottom is to the distance in described precalculated position;
Remove first laying that is not covered by the photoresist of described first predetermined altitude;
Remove the photoresist of first predetermined altitude in the groove;
Behind the photoresist of described first predetermined altitude in removing groove, form second laying, described second laying covers the surface of described Semiconductor substrate, the sidewall of groove, and forms in described groove and seal;
After formation is sealed, in described groove, fill the photoresist of second predetermined altitude, this second predetermined altitude is the distance of sealing bottom to described precalculated position;
Photoresist with described second predetermined altitude is mask, removes second laying on the photoresist of this second predetermined altitude;
Remove the photoresist of described second predetermined altitude;
Behind the photoresist of removing described second predetermined altitude, in the surface of described Semiconductor substrate and groove, form the wet etching barrier layer, described wet etching barrier layer covers described semiconductor substrate surface, the described trenched side-wall that seals and seal, and the material on described wet etching barrier layer is silicon nitride or silicon dioxide;
Remove described semiconductor substrate surface and cover described wet etching barrier layer of sealing;
Be mask with the wet etching barrier layer, wet etching is removed first laying and second laying in the groove.
Optionally, described is mask with described wet etching barrier layer, and the described groove of wet etching forms bottle formula groove and comprises:
Be mask with described wet etching barrier layer, form a bottle formula groove with the described groove of ammoniacal liquor etching.
Optionally, described precalculated position is the position of whole gash depth 1/10～1/5 for the described groove of distance top.
Optionally, the material of described first laying is tetraethoxysilance or silicon nitride.
Optionally, the material of described second laying is tetraethoxysilance or silicon nitride.
Optionally, the photoresist of filling first predetermined altitude comprises in described groove:
In described groove, fill up photoresist;
Return and carve the photoresist that the photoresist that fills up forms first predetermined altitude.
Optionally, the photoresist of filling second predetermined altitude comprises in described groove:
In described groove, fill up photoresist;
Return and carve the photoresist that the photoresist that fills up forms second predetermined altitude.
Optionally, the described semiconductor substrate surface of described removal and cover described wet etching barrier layer of sealing and comprise:
Remove wet etching barrier layer on described semiconductor substrate surface and described the sealing with dry etching.
Optionally, removing first laying that is not covered by the photoresist of described first predetermined altitude comprises:
Remove first laying that is not covered by the photoresist of described first predetermined altitude with hydrofluoric acid, this first laying material is tetraethoxysilance;
Or remove first laying that is not covered by the photoresist of described first predetermined altitude with phosphoric acid, this first laying material is silicon nitride.
Optionally, second laying of removing on the photoresist of second predetermined altitude comprises:
Remove second laying on the photoresist of second predetermined altitude with hydrofluoric acid, the material of this second laying is tetraethoxysilance;
Or remove second laying on the photoresist of second predetermined altitude with phosphoric acid, the material of this second laying is silicon nitride.
Optionally, forming the wet etching barrier layer in the surface of described Semiconductor substrate and groove comprises:
In the surface of described Semiconductor substrate and groove, form the wet etching barrier layer with Atomic layer deposition method or low pressure gas phase deposition method.
The present invention also provides a kind of bottle method of formula trench capacitor that forms, and comprising:
Form bottle formula groove with above-described method;
In described bottle formula groove, fill the capacitor dielectric layer of predetermined thickness;
Behind the capacitor dielectric layer of filling predetermined thickness, continue filling semiconductor material in described bottle formula groove.
Optionally, described capacitor dielectric layer is silicon dioxide.
Optionally, described Semiconductor substrate is the polysilicon substrate, and described semi-conducting material is polysilicon.
Compared with prior art, the present invention has the following advantages:
The present invention replaces aluminium oxide wet etching of the prior art barrier layer, thereby can not have the problem of metallic pollution by forming silicon nitride wet etching barrier layer or silicon dioxide wet etching barrier layer.
In specific embodiments of the invention, because when utilizing Atomic layer deposition method or low pressure gas phase deposition to form silicon nitride or silicon dioxide wet etching block film layer, has good uniformity, therefore it is more and more littler to solve in the prior art opening along with groove, and the uniformity on wet etching barrier layer and the degree of depth are difficult to the technical problem of control.
In addition, in specific embodiments of the invention, form silicon nitride wet etching barrier layer or silicon dioxide wet etching barrier layer and do not need special reaction chamber and special process, therefore can in existing reaction chamber, carry out, enlarge the technological ability of existing reaction chamber, that is to say, can in existing reaction chamber, carry out more technology, reduce installation cost.
Description of drawings
Fig. 1 a～Fig. 1 d is the generalized section that prior art forms the method for bottle formula groove;
Fig. 2 is the flow chart of method of the formation bottle formula groove of the specific embodiment of the invention;
Fig. 3 is the flow chart on the formation wet etching barrier layer of the specific embodiment of the invention;
Fig. 4 a～Fig. 4 n is the generalized section of the formation bottle formula groove of the specific embodiment of the invention;
Fig. 5 is the generalized section of bottle formula trench capacitor of the formation of the specific embodiment of the invention.
Embodiment
The method of the formation bottle formula groove of the specific embodiment of the invention, form silicon nitride wet etching barrier layer or silicon dioxide wet etching barrier layer by the upper portion side wall at groove, replacing aluminium oxide wet etching of the prior art barrier layer, thereby can solve the problem of the metallic pollution that exists in the prior art.
For those skilled in the art be can better understand the present invention, describe the method for the formation bottle formula groove of the specific embodiment of the invention in detail below in conjunction with accompanying drawing.
Fig. 2 is the flow chart of method of the formation bottle formula groove of the specific embodiment of the invention, and with reference to figure 2, the method for the formation bottle formula groove of the specific embodiment of the invention comprises:
Step S1 provides Semiconductor substrate, is formed with groove in the described Semiconductor substrate;
Step S2, the sidewall in described groove top to precalculated position forms the wet etching barrier layer, and the material on described wet etching barrier layer is silicon nitride or silicon dioxide;
Step S3 is mask with described wet etching barrier layer, and the described groove of wet etching forms bottle formula groove;
Step S4 removes the wet etching barrier layer in the described bottle formula groove.
Fig. 3 is the flow chart on the formation wet etching barrier layer of the specific embodiment of the invention, with reference to figure 3, in the specific embodiment of the invention, step S2, sidewall in described groove top to precalculated position forms the wet etching barrier layer, and the material on described wet etching barrier layer is that silicon nitride or silicon dioxide comprise:
Step S201 forms first laying in the surface of described Semiconductor substrate, sidewall and the bottom of groove;
Step S202, form first laying after, in described groove, fill the photoresist of first predetermined altitude, this first predetermined altitude is that channel bottom is to the distance in described precalculated position;
Step S203 removes first laying that is not covered by the photoresist of described first predetermined altitude;
Step S204, the photoresist of first predetermined altitude in the removal groove;
Step S205 behind the photoresist of described first predetermined altitude in removing groove, forms second laying, and described second laying covers the surface of described Semiconductor substrate, the sidewall of groove, and forms in described groove and seal;
Step S206 after formation is sealed, fills the photoresist of second predetermined altitude in described groove, this first predetermined altitude is the distance of sealing bottom to described precalculated position;
Step S207 is mask with the photoresist of described second predetermined altitude, removes second laying on the photoresist of this second predetermined altitude;
Step S208 removes the photoresist of described second predetermined altitude;
Step S209, behind the photoresist of removing described second predetermined altitude, in the surface of described Semiconductor substrate and groove, form the wet etching barrier layer, described wet etching barrier layer covers described semiconductor substrate surface, the described trenched side-wall that seals and seal, and the material on described wet etching barrier layer is silicon nitride or silicon dioxide;
Step S210 removes described semiconductor substrate surface and covers described wet etching barrier layer of sealing;
Step S211 is mask with the wet etching barrier layer, and wet etching is removed first laying and second laying in the groove.
Fig. 4 a～Fig. 4 n is the generalized section of the formation bottle formula groove of the specific embodiment of the invention, describes the method for the formation bottle formula groove of the specific embodiment of the invention in detail below in conjunction with Fig. 2, Fig. 3 and Fig. 4 a～Fig. 4 n.
In conjunction with reference to figure 2 and Fig. 4 a, execution in step S1 provides Semiconductor substrate 40, is formed with groove 50 in described Semiconductor substrate, and in this specific embodiment, the degree of depth of groove 50 is 6～8 microns, is preferably 7 microns.Be specially: Semiconductor substrate 40 is provided, at the surface deposition hard mask layer 41 of Semiconductor substrate 40, in this specific embodiment, hard mask layer 41 is silicon nitride layer, be mask dry etching Semiconductor substrate 40 with hard mask layer 41, in Semiconductor substrate 40, form groove 50.In this step, the technology of not describing photoetching process in detail and forming hard mask layer, it is techniques well known, is not described in detail at this.In the specific embodiment of the invention, Semiconductor substrate 40 can be for being monocrystalline silicon or SiGe; It also can be silicon-on-insulator (SOI); The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.
In conjunction with reference to figure 2, Fig. 3 and Fig. 4 b～Fig. 4 n, execution in step S2, the sidewall in described groove top to precalculated position forms the wet etching barrier layer, and the material on described wet etching barrier layer is silicon nitride or silicon dioxide.Be specially:
In conjunction with reference to figure 3 and Fig. 4 b, execution in step S201 forms first laying 42 in the surface of described Semiconductor substrate 40, sidewall and the bottom of groove 50.In this specific embodiment, the surface of Semiconductor substrate 40 is formed with hard mask layer 41, and then first laying 42 is formed on the surface of the sidewall of hard mask layer 41 and groove 50 and bottom forming.In this specific embodiment of the present invention, the material of first laying 42 is tetraethoxysilance (TEOS), and its thickness is 100 dusts～500 dusts, is preferably 300 dusts.The method that forms first laying 42 is chemical vapour deposition (CVD).In other embodiments of the invention, the material of first laying 42 also can have the material of good deposition uniformity, for example silicon nitride for other.
In conjunction with reference to figure 3 and Fig. 4 c, execution in step S202, form first laying 42 after, in described groove 50, fill the first predetermined altitude H
1Photoresist 51, this first predetermined altitude H
1Be the distance of channel bottom to described precalculated position.In specific embodiments of the invention, described precalculated position is the position of whole gash depth 1/10～1/5 for the described groove of distance top, therefore the described first predetermined altitude H
1The condition that satisfies is: the distance h at the top of the photoresist 51 of described first predetermined altitude to groove top is that gash depth (is H
1With the h sum) 1/10～1/5, be preferably 1/7.Fill the first predetermined altitude H
1The method of photoresist 51 comprise: in described groove, fill up photoresist; Return and carve the photoresist that the photoresist that fills up forms first predetermined altitude.Be specially spin coating photoresist on wafer, photoresist is filled in the process of spin coating in the groove 50, after photoresist fills up groove 50, returns and carves the photoresist 51 that the photoresist that fills up forms first predetermined altitude.Afterwards, remove the photoresist of crystal column surface.In the specific embodiment of the invention, form the photoresist 51 of first predetermined altitude after, first laying 42 is divided into two parts by photoresist 51, top first laying 421 and bottom first laying 422.
In conjunction with reference to figure 3 and Fig. 4 d, execution in step S203 removes first laying that is not covered by the photoresist 51 of described first predetermined altitude.In the specific embodiment of the invention, first laying 42 is divided into two parts by photoresist 51, top first laying 421 and bottom first laying 422.If the material of first laying is tetraethoxysilance, remove first laying that is not covered by the photoresist of described first predetermined altitude with hydrofluoric acid, namely remove top first laying 421 that is not covered by described photoresist with hydrofluoric acid, wherein, the concentration of hydrofluoric acid is 10%～0.5%.If the first laying material is silicon nitride, remove first laying that is not covered by described photoresist with phosphoric acid, namely remove the first laying top, first laying 421 that is not covered by described photoresist with phosphoric acid, wherein, the phosphoric acid that uses is pure phosphoric acid.
In conjunction with reference to figure 3 and Fig. 4 e, execution in step S204 removes the photoresist 51 of first predetermined altitude in the groove 50.In specific embodiments of the invention, utilize cineration technics to remove the photoresist 51 of first predetermined altitude in the groove 50, its method is the known technology of this area, this does not elaborate.
In conjunction with reference to figure 3 and Fig. 4 f, execution in step S205 behind the photoresist of described first predetermined altitude in removing groove, forms second laying 43, described second laying 43 covers the surface of described Semiconductor substrate 40, the sidewall of groove 50, and forms in described groove and seal.In diagram, dotted line is the line of demarcation of first laying and second laying, in specific embodiments of the invention, the material of described second laying 43 is tetraethoxysilance (TEOS) or silicon nitride, identical with the material of first laying, therefore after forming second laying 40, because material is identical, mix is one deck to first laying with second laying.The thickness that deposition forms second laying 43 is relevant with concrete technology, in the specific embodiment of the invention, second laying 43 seals groove 50 near described first laying and the described second laying connecting position with described groove 50, namely second laying 43 seals inner generation of groove, can stop to deposit tetraethoxysilance (TEOS) this moment, space 60 is after formation is sealed in the diagram, because the heterogeneity of tetraethoxysilance (TEOS) deposition forms the space in groove 50 bottoms.In the specific embodiment of the invention, with reference to figure 4f, the connecting position that seals at first laying and second laying of generation is downward concavity, and seals the bottom to the non-perpendicular shape of the sidewall that seals the top.
In conjunction with reference to figure 3 and Fig. 4 g, execution in step S206 after formation is sealed, fills the second predetermined altitude H in described groove 50
2Photoresist 52, this second predetermined altitude H
2For sealing the distance in bottom to described precalculated position.In the specific embodiment of the present invention, the height of photoresist 52 is by seal location and need between the bottom (being the precalculated position) of bottleneck of the bottle formula groove form apart from definite, that is to say, photoresist 52 plays the effect of bottleneck position, location, namely locate the effect of the bottom position of bottleneck, in specific embodiments of the invention, the second predetermined altitude H
2The condition that satisfies of photoresist be: the distance at the top of the photoresist of described second predetermined altitude to groove top is 1/10～1/5 of gash depth, is preferably 1/7.The tip position of the photoresist 52 of second predetermined altitude and the photoresist 51 of first predetermined altitude is all in the pre-position, in the technology of reality, the height of the photoresist 52 of second predetermined altitude can be a little than the height height of the photoresist 51 of first predetermined altitude, its role is the effect of bottleneck position, location, and the effect of playing mask in corresponding processing step.In the specific embodiment of the invention, form the second predetermined altitude H
2The method of photoresist 52 comprise: in described groove, fill up photoresist; Return and carve the photoresist that the photoresist that fills up forms second predetermined altitude.Be specially spin coating photoresist on wafer, photoresist is filled in groove 50 in the process of spin coating, after photoresist fills up groove 50, returns and carves the photoresist 52 that the photoresist that fills up forms second predetermined altitude.Afterwards, remove the photoresist of crystal column surface.After forming the photoresist 52 of second predetermined altitude, in the specific embodiment of the invention, second laying 43 is divided into two parts by photoresist 52, second laying 432 under second laying 431 on the photoresist 52 of second predetermined altitude and the photoresist 52 of second predetermined altitude.
In conjunction with reference to figure 3 and Fig. 4 h, execution in step S207 is mask with the photoresist 52 of described second predetermined altitude, removes second laying 431 on the photoresist 52 of this second predetermined altitude.Second laying of removing on the photoresist of second predetermined altitude 431 comprises: if the material of second laying is tetraethoxysilance, remove second laying on the photoresist 52 of second predetermined altitude with hydrofluoric acid, namely remove with hydrofluoric acid with hydrofluoric acid and remove second laying 431 on the photoresist 52 of second predetermined altitude, wherein, the concentration of hydrofluoric acid is 10%～0.5%.If the second laying material is silicon nitride, remove first laying on the photoresist 52 of second predetermined altitude with phosphoric acid, namely remove second laying 431 on the photoresist 52 of second predetermined altitude with phosphoric acid, the phosphoric acid that uses is pure phosphoric acid.
In conjunction with reference to figure 3 and Fig. 4 i, execution in step S208 removes the photoresist 52 of described second predetermined altitude.In specific embodiments of the invention, utilize cineration technics to remove the photoresist 52 of second predetermined altitude in the groove 50, its method is the known technology of this area, this does not elaborate.
In conjunction with reference to figure 3 and Fig. 4 j, execution in step S209, behind the photoresist 52 of removing described second predetermined altitude, in the surface of described Semiconductor substrate and groove, form wet etching barrier layer 44, described wet etching barrier layer 44 covers described semiconductor substrate surface, the described trenched side-wall that seals and seal, and the material on described wet etching barrier layer is silicon nitride or silicon dioxide.In the specific embodiment of the invention, with Atomic layer deposition method formation wet etching barrier layer 44 in the surface of described Semiconductor substrate 40 and groove 50.In other embodiments of the invention, also can use the low pressure gas phase deposition method in the surface of described Semiconductor substrate and groove, to form the wet etching barrier layer.
In conjunction with reference to figure 3 and Fig. 4 k, execution in step S210 removes described semiconductor substrate surface and covers described wet etching barrier layer 44 of sealing.The described semiconductor substrate surface of described removal and cover described wet etching barrier layer of sealing and comprise: remove described semiconductor substrate surface and cover described wet etching barrier layer of sealing with dry etching.If the material on wet etching barrier layer is silicon nitride, hydrofluorocarbons gas etching silicon nitride then is to remove semiconductor substrate surface and to cover described wet etching barrier layer of sealing.If the material on wet etching barrier layer is silicon dioxide, then use the fluorocarbon gases etching silicon dioxide, to remove semiconductor substrate surface and to cover described wet etching barrier layer of sealing.The wet etching barrier layer of described trenched side-wall is owing to be positioned on the sidewall of groove, and dry etching can not removed it, and when removing the wet etching barrier layer with dry etching, just remove on the wet etching barrier layer that semiconductor substrate surface and covering are sealed.
In conjunction with reference to figure 3 and Figure 41, execution in step S211 is mask with the wet etching barrier layer, and wet etching is removed in the groove 50 first laying and second laying.In the specific embodiment of the invention, remove in the groove 50 first laying and second laying with hydrofluoric acid or phosphoric acid.If the material of first laying and second laying is tetraethoxysilance, remove 50 remaining first laying and second layings in the groove with hydrofluoric acid.If the material of first laying and second laying is silicon nitride, remove 50 remaining first laying and second layings in the groove with phosphoric acid.
In conjunction with reference to figure 3 and Fig. 4 m, execution in step S3 is mask with described wet etching barrier layer, and the described groove of wet etching forms a bottle formula groove.Described is mask with described wet etching barrier layer, and the described groove of wet etching forms a bottle formula groove and comprises: be mask with described wet etching barrier layer, form a bottle formula groove with the described groove of ammoniacal liquor etching.
In conjunction with reference to figure 3 and Fig. 4 n, execution in step S4 removes the wet etching barrier layer 44 in the described bottle formula groove.In the specific embodiment of the invention, the method for removing the wet etching barrier layer 44 in the described bottle formula groove is wet etching, if the material on wet etching barrier layer 44 is silicon nitride, uses pure phosphoric acid to remove the wet etching barrier layer of trenched side-wall; If the material on wet etching barrier layer 44 is silicon dioxide, use hydrofluoric acid to remove the wet etching barrier layer of trenched side-wall, the concentration of hydrofluoric acid is 10%～0.5%.
The present invention replaces aluminium oxide wet etching of the prior art barrier layer, thereby can not have the problem of metallic pollution by forming silicon nitride wet etching barrier layer or silicon dioxide wet etching barrier layer.
In specific embodiments of the invention, utilize Atomic layer deposition method or low-pressure vapor phase chemical deposition to form silicon nitride wet etching barrier layer or silicon dioxide wet etching barrier layer, has good uniformity, therefore it is more and more littler to solve in the prior art opening along with groove, and the uniformity on wet etching barrier layer and the degree of depth are difficult to the technical problem of control.
In addition, in specific embodiments of the invention, form silicon nitride wet etching barrier layer or silicon dioxide wet etching barrier layer and do not need special reaction chamber and special process, therefore can in existing reaction chamber, carry out, enlarge the technological ability of existing reaction chamber, that is to say, can in existing reaction chamber, carry out more technology, reduce installation cost.
The present invention also provides a kind of bottle method of formula trench capacitor that forms, and with reference to figure 5, comprises with above-described method forming bottle formula groove; In described bottle formula groove, fill the capacitor dielectric layer 61 of predetermined thickness, namely after forming bottle formula groove, form the capacitor dielectric layer 61 that covers sidewall surfaces and lower surface in sidewall and the bottom of bottle formula groove; Afterwards, filling semiconductor material 62 in groove, in the specific embodiment of the invention, the semi-conducting material of filling is polysilicon, capacitor dielectric layer is silicon dioxide.In other embodiments of the invention, capacitor dielectric layer also can be known other dielectric materials of those skilled in the art.In specific embodiments of the invention, Semiconductor substrate 40 is the polysilicon substrate, and it serves as first pole plate of capacitor; The semi-conducting material 62 of filling, namely polysilicon serves as second pole plate of capacitor.
The above only is specific embodiments of the invention; in order to make those skilled in the art better understand spirit of the present invention; yet protection scope of the present invention is not limited range with the specific descriptions of this specific embodiment; any those skilled in the art is in the scope that does not break away from spirit of the present invention; can make an amendment specific embodiments of the invention, and not break away from protection scope of the present invention.
Claims (14)
1. one kind forms bottle method of formula groove, it is characterized in that comprising:
Semiconductor substrate is provided, is formed with groove in the described Semiconductor substrate;
Sidewall in described groove top to precalculated position forms the wet etching barrier layer, and the material on described wet etching barrier layer is silicon nitride or silicon dioxide; Described sidewall in described groove top to precalculated position forms the wet etching barrier layer and comprises:
Form first laying in the surface of described Semiconductor substrate, sidewall and the bottom of groove;
After forming first laying, fill the photoresist of first predetermined altitude in described groove, this first predetermined altitude is that channel bottom is to the distance in described precalculated position;
Remove first laying that is not covered by the photoresist of described first predetermined altitude;
Remove the photoresist of first predetermined altitude in the groove;
Behind the photoresist of described first predetermined altitude in removing groove, form second laying, described second laying covers the surface of described Semiconductor substrate, the sidewall of groove, and forms in described groove and seal;
After formation is sealed, in described groove, fill the photoresist of second predetermined altitude, this second predetermined altitude is the distance of sealing bottom to described precalculated position;
Photoresist with described second predetermined altitude is mask, removes second laying on the photoresist of this second predetermined altitude;
Remove the photoresist of described second predetermined altitude;
Behind the photoresist of removing described second predetermined altitude, in the surface of described Semiconductor substrate and groove, form the wet etching barrier layer, described wet etching barrier layer covers described semiconductor substrate surface, the described trenched side-wall that seals and seal, and the material on described wet etching barrier layer is silicon nitride or silicon dioxide;
Remove described semiconductor substrate surface and cover described wet etching barrier layer of sealing;
Be mask with the wet etching barrier layer, wet etching is removed first laying and second laying in the groove;
After removing first laying and second laying in the groove, be mask with described wet etching barrier layer, the described groove of wet etching forms bottle formula groove;
Remove the wet etching barrier layer in the described bottle formula groove.
2. the method that forms bottle formula groove as claimed in claim 1 is characterized in that described is mask with described wet etching barrier layer, and the described groove of wet etching forms bottle formula groove and comprises:
Be mask with described wet etching barrier layer, form a bottle formula groove with the described groove of ammoniacal liquor etching.
3. the method that forms bottle formula groove as claimed in claim 1 is characterized in that, described precalculated position is the position of whole gash depth 1/10～1/5 for the described groove of distance top.
4. the method that forms bottle formula groove as claimed in claim 1 is characterized in that the material of described first laying is tetraethoxysilance or silicon nitride.
5. the method that forms bottle formula groove as claimed in claim 1 is characterized in that the material of described second laying is tetraethoxysilance or silicon nitride.
6. the method that forms bottle formula groove as claimed in claim 1 is characterized in that, the photoresist of filling first predetermined altitude in described groove comprises:
In described groove, fill up photoresist;
Return and carve the photoresist that the photoresist that fills up forms first predetermined altitude.
7. the method that forms bottle formula groove as claimed in claim 1 is characterized in that, the photoresist of filling second predetermined altitude in described groove comprises:
In described groove, fill up photoresist;
Return and carve the photoresist that the photoresist that fills up forms second predetermined altitude.
8. a method that forms bottle formula groove as claimed in claim 1 is characterized in that, the described semiconductor substrate surface of described removal and cover described wet etching barrier layer of sealing and comprise:
Remove wet etching barrier layer on described semiconductor substrate surface and described the sealing with dry etching.
9. the method that forms bottle formula groove as claimed in claim 4 is characterized in that, removes first laying that is not covered by the photoresist of described first predetermined altitude and comprises:
Remove first laying that is not covered by the photoresist of described first predetermined altitude with hydrofluoric acid, this first laying material is tetraethoxysilance;
Or remove first laying that is not covered by the photoresist of described first predetermined altitude with phosphoric acid, this first laying material is silicon nitride.
10. a method that forms bottle formula groove as claimed in claim 5 is characterized in that, second laying of removing on the photoresist of second predetermined altitude comprises:
Remove second laying on the photoresist of second predetermined altitude with hydrofluoric acid, the material of this second laying is tetraethoxysilance;
Or remove second laying on the photoresist of second predetermined altitude with phosphoric acid, the material of this second laying is silicon nitride.
11. a method that forms bottle formula groove as claimed in claim 1 is characterized in that, forms the wet etching barrier layer and comprise in the surface of described Semiconductor substrate and groove:
In the surface of described Semiconductor substrate and groove, form the wet etching barrier layer with Atomic layer deposition method or low pressure gas phase deposition method.
12. one kind forms bottle method of formula trench capacitor, it is characterized in that comprising:
Form bottle formula groove with each described method of claim 1～11;
In described bottle formula groove, fill the capacitor dielectric layer of predetermined thickness;
Behind the capacitor dielectric layer of filling predetermined thickness, continue filling semiconductor material in described bottle formula groove.
13. the method that forms bottle formula trench capacitor as claimed in claim 12 is characterized in that described capacitor dielectric layer is silicon dioxide.
14. the method that forms bottle formula trench capacitor as claimed in claim 12 is characterized in that described Semiconductor substrate is the polysilicon substrate, described semi-conducting material is polysilicon.
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| CN 201010275192 CN102386094B (en) | 2010-09-02 | 2010-09-02 | Method for forming bottle-type groove and method for forming bottle-type groove capacitor |
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| CN102623305B (en) * | 2012-03-23 | 2015-01-07 | 上海华力微电子有限公司 | Metal-multilayer insulator-metal capacitor as well as preparation method and integrated circuit thereof |
| CN107706181A (en) * | 2017-10-27 | 2018-02-16 | 睿力集成电路有限公司 | High aspect ratio structure, capacitor arrangement, semiconductor storage unit and preparation method |
| CN110534642B (en) * | 2018-05-25 | 2023-03-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110943163B (en) * | 2018-09-21 | 2022-07-05 | 长鑫存储技术有限公司 | Method for improving appearance of capacitor hole |
| CN113130746B (en) * | 2019-12-30 | 2022-09-30 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN111366618B (en) * | 2020-04-01 | 2022-07-29 | 上海华虹宏力半导体制造有限公司 | Temperature and humidity sensor and manufacturing method thereof |
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