CN102386077B - Method for manufacturing semiconductor device - Google Patents
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- CN102386077B CN102386077B CN201010274989.7A CN201010274989A CN102386077B CN 102386077 B CN102386077 B CN 102386077B CN 201010274989 A CN201010274989 A CN 201010274989A CN 102386077 B CN102386077 B CN 102386077B
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Abstract
The invention discloses a method for manufacturing a semiconductor device, comprising the following steps of: providing a substrate; depositing a material layer required by a grid structure and photoresist with a pattern on the substrate; adjusting temperature deviation of an etching machine according to preset grid structure critical dimension deviation, trimming the photoresist with the pattern; etching the material layer to form the grid structure with the actual grid structure critical dimension; and forming a liner material layer on the substrate and the grid structure by adopting a chemical vapor deposition method, and etching to form a liner layer. According to the method disclosed by the invention, uniformity of electrical properties of the semiconductor device can be effectively improved, and yield can be increased.
Description
Technical field
The present invention relates to process for fabrication of semiconductor device, particularly a kind of method of making semiconductor device.
Background technology
Along with constantly dwindling of semiconductor device critical size, in technique, must consider thermal effect, temperature is for the impact of semiconductor device electric property.Therefore, in semiconductor fabrication process, use chemical vapour deposition (CVD) (CVD) method to replace furnace oxidation method to form the various film layer structures in semiconductor device now.
Chemical vapour deposition (CVD) is that reactive material issues biochemical reaction in gaseous state condition, generates solid matter and is deposited on the solid matrix surface of heating, and then make the technology of solid material.Its advantage is to realize at a lower temperature the growth of large area film.But compared with furnace oxidation method, chemical vapour deposition technique has its shortcoming, thickness and the covering uniformity of the film that chemical vapour deposition technique forms are poor.Especially obvious for the deposition performance of laying and gap parietal layer, reason is that laying and gap parietal layer will cover on the sidewall and substrate of grid structure successively, and the unevenness on surface makes the thickness of film and the lack of homogeneity of covering show particularly outstandingly.And in etching technics subsequently, the inhomogeneities of this thin film deposition can be handed on, cause the overall critical dimension uniformity of grid structure and sidewall poor.The overall critical size that is usually expressed as the center and peripheral of wafer differs greatly.But owing to there being multiple tube cores on each wafer, the corresponding semiconductor device of each tube core, if skewness will make the quality of each semiconductor device different, thereby makes the uniformity of electrical properties of semiconductor device poor.
As shown in Figure 1, for thering is the profile of semiconductor device of grid structure of sidewall.In Semiconductor substrate 100, have grid structure 101, grid structure 101 comprises the gate oxide layers 101A and the gate material layers 101B that are formed on substrate.On the sidewall of grid structure 101, be provided with laying 102 and gap parietal layer 103 that one deck is very thin.Facts have proved, grid structure 101 is more outstanding with the impact that the uniformity of the overall critical size of laying 102 distributes on the quiescent current of semiconductor device, and quiescent current distributes and more restrains, and the uniformity of the electric property of this semiconductor device can be better.
Make semiconductor device as shown in Figure 1 utilizing chemical vapor deposition method, when particularly deposition forms the required material layer of laying, due to the inherent defect of above-mentioned chemical vapour deposition (CVD), be therefore difficult to improve the uniformity of thin film deposition from chemical vapor deposition method itself.The inhomogeneous meeting of laying directly affects the uniformity of the overall critical size of grid structure and laying, further affects semiconductor device electrical properties uniformity, thereby reduces yields.
Therefore, be badly in need of at present a kind of method of making semiconductor device, to improve semiconductor device electrical properties uniformity, improve yields.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to solve the poor problem of electrical properties uniformity of semiconductor device in prior art, the present invention proposes a kind of manufacture method of semiconductor device, comprising: substrate is provided; On described substrate, deposition forms required material layer and the figuratum photoresist of tool of grid structure; Adjust the temperature deviation of etching machine bench according to predetermined grid structure key size deviation, prune the figuratum photoresist of described tool; Material layer described in etching, forms the grid structure with actual grid structure critical size; And on described substrate and described grid structure, adopt chemical gaseous phase depositing process to form cushioning material layer, and etching forms laying.
According to one aspect of the invention, described in be trimmed to and pass into the reacting gas that comprises oxygen the critical size of photoresist opening is adjusted.
According to one aspect of the invention, the key size deviation opposite number each other of described predetermined grid structure key size deviation and laying.
According to one aspect of the invention, the required material layer of described formation grid structure comprises gate oxide layers and gate material layers.
According to one aspect of the invention, the predetermined grid structure key size deviation of described basis is adjusted temperature deviation, comprise: in the time that the grid structure key size deviation of described reality is less than described predetermined grid structure key size deviation, reduce described temperature deviation; And in the time that the grid structure key size deviation of described reality is greater than described predetermined grid structure key size deviation, increase described temperature deviation.
According to one aspect of the invention, the predetermined grid structure key size deviation of described basis is adjusted temperature deviation, comprising: determine in advance the relation curve between grid structure key size deviation and described temperature deviation; And according to described predetermined grid structure key size deviation, adjust described temperature deviation according to described relation curve.
According to one aspect of the invention, the described pre-step of determining relation curve comprises: pruning in the figuratum photoresist process of described tool, change described temperature deviation; After forming described grid structure, detect respectively described grid structure key size deviation; And the data point of described temperature deviation and described grid structure key size deviation composition is carried out to matching, obtain described relation curve.
According to one aspect of the invention, the temperature of described etching machine bench is 30～50 ℃.
According to one aspect of the invention, described temperature deviation is-15～15 ℃.
The method according to this invention, can improve the uniformity of semiconductor device electrical properties effectively, improves yields.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the profile with the semiconductor device of the grid structure of sidewall;
Fig. 2 is the profile of semiconductor device according to the invention;
Fig. 3 is the flow chart of the manufacture method of semiconductor device according to the invention;
Fig. 4 is the key size deviation of grid structure that obtains according to one embodiment of the present invention and the relation curve of the temperature deviation of etching machine bench;
Fig. 5 is without overcompensation with through the comparison diagram of the quiescent current of the semiconductor device of overcompensation.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that semiconductor device is made in explanation method according to the present invention.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution mode.
Method of the present invention is carried out the critical size of compensating liner layer by the critical size that changes grid structure on wafer, thereby the overall critical size of grid structure and laying is evenly distributed at the regional of whole wafer.As shown in Figure 2, be formed with grid structure 201 on substrate 200, grid structure 201 comprises gate oxide layers 201A and gate material layers 201B.The both sides of grid structure 201 are formed with laying 202.Wherein, the critical size of grid structure 201 is d
1, the critical size of laying 202 is d
2, the overall critical size of grid structure 201 and laying 202 is (d
1+ 2d
2).
The method according to this invention, can measure the critical size d of laying in advance
2distribution on wafer, then adjusts the critical size d of grid structure according to this distribution
1distribution on wafer, thus make overall critical size (d
1+ 2d
2) on wafer, zones of different is substantially equal.Specifically, if the critical size d of the laying of measuring in advance
2central area at wafer is larger,, in the time forming grid structure, dwindles the critical size d of central area grid structure
1, and then reach on wafer the object that overall critical size everywhere equates substantially.To describe the method according to this invention below in detail.
Fig. 3 is the flow chart of the manufacture method of semiconductor device according to the invention.
In step 301, provide the substrate with fleet plough groove isolation structure.Described substrate can be including but not limited at least one in following mentioned material: for example silicon, silicon-on-insulator (silicon oninsulator, SOI), stacked silicon (stacked silicon on insulator on insulator, SSOI), stacked SiGe (stacked SiGe on insulator on insulator, S-SiGeOI), germanium on insulator SiClx (SiGe on insulator, and germanium on insulator (Ge on insulator, GeOI) SiGeOI).
In step 302, on substrate, deposition forms required various material layers and the figuratum photoresist of tool of grid structure.Wherein, described various material layer for example comprises the gate oxide layers and the gate material layers etc. that form by traditional deposition.
In step 303, adjust the temperature deviation of etching machine bench according to predetermined grid structure key size deviation, prune the figuratum photoresist of tool, to compensate the key size deviation that deposition and etching were produced due to laying.Described being trimmed to passes into the reacting gas that comprises oxygen the critical size of photoresist opening adjusted.Adjust the critical size of opening by controlling the time that passes into of reacting gas, thereby adjust the critical size of grid structure.Wherein, grid structure key size deviation is the difference between the critical size of central area grid structure on wafer and the critical size of fringe region grid structure, and the temperature deviation of etching machine bench is the difference between etching machine bench central temperature and lip temperature.Inventor's discovery, the grid structure key size deviation at center wafer and edge is relevant with the temperature deviation of etching machine bench center and peripheral.Reason is, temperature is one of impact principal element of adjusting speed, and the high speed of pruning of temperature is fast, and vice versa.Therefore can, by changing the temperature of zones of different on wafer, adjust the pruning speed of zones of different, thereby reach predetermined grid structure key size deviation.
The temperature deviation of adjusting etching machine bench according to predetermined grid structure key size deviation, comprising: in the time that actual grid structure key size deviation is less than predetermined grid structure key size deviation, reduce the temperature deviation of etching machine bench; And in the time that actual grid structure key size deviation is greater than predetermined grid structure key size deviation, increase the temperature deviation of etching machine bench.
In practical operation, adjust the concrete operation step of the temperature deviation of etching machine bench according to predetermined grid structure key size deviation, comprising: determine in advance the relation curve between grid structure key size deviation and the temperature deviation of etching machine bench; And according to predetermined grid structure key size deviation, adjust the temperature deviation of etching machine bench according to this relation curve.
Wherein, determine that in advance the step of relation curve comprises: pruning in the figuratum photoresist process of tool, change the temperature deviation of etching machine bench centerand edge; After formation grid structure, detect respectively the grid structure key size deviation at center wafer and edge; And the data point of temperature deviation to etching machine bench and grid structure key size deviation composition carries out matching, obtain relation curve.
In addition, the key size deviation opposite number each other of predetermined grid structure key size deviation and laying, needs the key size deviation that grid structure key size deviation can compensating liner layer.The laying of making for same process condition, can adopt optical critical dimension measurement (OCD) to measure the key size deviation of preformed laying, to regulate the finishing parameter of next group wafer grid structure according to measurement result.Described being compensated for as in the time that the key size deviation of laying is B, makes the key size deviation of grid structure be-B, the i.e. key size deviation of laying and the key size deviation of utmost point opposite number each other.For instance, if the key size deviation of laying is 1nm, the key size deviation of adjusting grid structure is to-1nm; If the key size deviation of laying is-0.5nm to adjust the key size deviation of grid structure to 0.5nm.
In step 304, take the photoresist after repairing as mask, etching forms grid structure.
In step 305, on substrate and grid structure, form cushioning material layer, and etching forms laying.The present invention adopts the method for chemical vapour deposition (CVD) to form cushioning material layer.As, can adopt low-pressure chemical vapor deposition (LPCVD) equipment or plasma enhanced chemical vapor deposition (PECVD) equipment etc.Can there are along with the change of technology some differences in the structure of laying.For instance, in some technique, laying is one deck oxide; Also have in some techniques, laying is oxide and nitride layer.
The pre-step of determining relation curve will be described according to one embodiment of the present invention in detail below.
First, in photoresist pruning process, change the temperature deviation of etching machine bench centerand edge, after grid structure etching, detect respectively the grid structure key size deviation at center wafer and edge.This process need be carried out many group experiments, to obtain multiple data points that are made up of temperature deviation and key size deviation.Wherein, need to keep other parameter constant, only change the temperature deviation of etching machine bench centerand edge.
According to an embodiment of the invention, what etching formation grid structure and laying adopted is LAM KIYO45 type etching machine bench.In order to take into account temperature operation scope and other technological requirement of pruning technique, the temperature of etching machine bench can regulate within the scope of 30～50 ℃ conventionally.The temperature deviation scope of etching machine bench is-15～15 ℃, and concrete temperature deviation is for example-15 ℃ ,-10 ℃ ,-5 ℃, 5 ℃, 10 ℃ and 15 ℃.Centered by-15 ℃, temperature is lower 15 ℃ than lip temperature, and temperature is higher 15 ℃ than lip temperature centered by 15 ℃.
Then, described data point is carried out to matching, obtain predetermined relationship curve.According to an embodiment of the invention, obtain the relation curve shown in Fig. 4.As shown in Figure 4, in figure, abscissa is the temperature deviation of board centerand edge, and ordinate is the key size deviation of the grid structure at wafer surface center and the grid structure at edge.401 is each data point of testing the corresponding key size deviation of temperature deviation of the different etching board obtaining, and 402 is the relation curve obtaining according to each data point matching.As can be seen from the figure, the key size deviation of grid structure and the temperature deviation of etching machine bench present extraordinary linear relationship, and along with the temperature deviation of etching machine bench constantly reduces, the grid structure key size deviation obtaining is increasing, therefore can be for automatic control operation according to compensation method of the present invention.
Quiescent current to semiconductor device is measured, to reflect the electric property of semiconductor device.Fig. 5 is the comparison diagram of the quiescent current of the semiconductor device made without overcompensation with through overcompensation.As shown in Figure 5, transverse axis represents different wafers, and the longitudinal axis represents the numerical values recited of quiescent current.Block diagram can illustrate that the distribution of quiescent current is convergence or disperses very easily, and quiescent current distributes to disperse and shows that the electric property of semiconductor device is inhomogeneous, and on the contrary, convergence in distribution shows that electric property is even.The quiescent current that A group is the semiconductor device made without overcompensation distributes, and B group is the method according to this invention, and through overcompensation, and the quiescent current of the semiconductor device of making distributes.Two groups are clear that the quiescent current convergence in distribution that adopts the semiconductor device that obtains of the method according to this invention very much to specific energy, illustrate its electric property uniformity with respect to existing methodical making semiconductor device be improved significantly.
The method according to this invention, can in a big way, adjust the key size deviation of grid structure, thereby laying is compensated by depositing with the caused deviation of etching, and then make total critical size of grid structure and laying even, make the electric property of the semiconductor device of different die on wafer even.Because the temperature deviation of grid structure key size deviation according to the present invention and etching machine bench presents extraordinary linear relationship, therefore can also be used for automatic control operation according to compensation method of the present invention.
Have according to the semiconductor device of execution mode manufacture as mentioned above and can be applicable in multiple integrated circuit (IC).For example memory circuitry according to IC of the present invention, as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcie arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-mentioned execution mode, but should be understood that, above-mentioned execution mode is the object for giving an example and illustrating just, but not is intended to the present invention to be limited within the scope of described execution mode.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-mentioned execution mode, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a manufacture method for semiconductor device, comprising:
Substrate is provided;
On described substrate, deposition forms required material layer and the figuratum photoresist of tool of grid structure;
The pre-relation curve of determining between grid structure key size deviation and the temperature deviation of etching machine bench, according to predetermined described grid structure key size deviation, adjust the temperature deviation of described etching machine bench according to described relation curve, prune the figuratum photoresist of described tool;
Take the described photoresist after finishing as mask, material layer described in etching, forms the grid structure with actual grid structure critical size; And
On described substrate and described grid structure, adopt chemical gaseous phase depositing process to form cushioning material layer, and etching form laying;
Wherein, the described pre-step of determining relation curve comprises: pruning in the figuratum photoresist process of described tool, change described temperature deviation; After forming described grid structure, detect respectively described grid structure key size deviation; And the data point of described temperature deviation and described grid structure key size deviation composition is carried out to matching, obtain described relation curve.
2. the method for claim 1, is characterized in that, described in be trimmed to and pass into the reacting gas that comprises oxygen the critical size of photoresist opening is adjusted.
3. the method for claim 1, is characterized in that, the key size deviation opposite number each other of described predetermined grid structure key size deviation and laying.
4. the method for claim 1, is characterized in that, the required material layer of described formation grid structure comprises gate oxide layers and gate material layers.
5. the method for claim 1, is characterized in that, the predetermined grid structure key size deviation of described basis is adjusted temperature deviation, comprising:
In the time that the grid structure key size deviation of described reality is less than described predetermined grid structure key size deviation, reduce described temperature deviation; And
In the time that the grid structure key size deviation of described reality is greater than described predetermined grid structure key size deviation, increase described temperature deviation.
6. the method for claim 1, is characterized in that, the temperature of described etching machine bench is 30～50 ℃.
7. the method for claim 1, is characterized in that, described temperature deviation is-15～15 ℃.
8. an integrated circuit that comprises the semiconductor device of manufacturing by the method as described in any one in claim 1-7, wherein said integrated circuit is selected from dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC) and radio circuit.
9. an electronic equipment that comprises the semiconductor device of manufacturing by the method as described in any one in claim 1-7, wherein said electronic equipment is selected from personal computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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| CN105374682B (en) * | 2014-08-28 | 2018-01-02 | 中国科学院微电子研究所 | Method for controlling fin size of fin field effect transistor device |
| CN109273353A (en) * | 2018-08-29 | 2019-01-25 | 上海华力集成电路制造有限公司 | Improve the method for residual defects after wafer photolithography glue develops |
| CN116313876B (en) * | 2023-05-25 | 2023-08-04 | 粤芯半导体技术股份有限公司 | Method for monitoring substrate temperature in ion implantation process |
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| CN1609711A (en) * | 2003-10-21 | 2005-04-27 | 应用材料有限公司 | Method for controlling accuracy and repeatability of an etch process |
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| CN101320711A (en) * | 2007-06-05 | 2008-12-10 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and preparation thereof |
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| JPH01122137A (en) * | 1987-11-05 | 1989-05-15 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP3147036B2 (en) * | 1997-05-02 | 2001-03-19 | 日本電気株式会社 | Compound semiconductor device and method of manufacturing the same |
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| CN1609711A (en) * | 2003-10-21 | 2005-04-27 | 应用材料有限公司 | Method for controlling accuracy and repeatability of an etch process |
| CN1588234A (en) * | 2004-07-12 | 2005-03-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Photoetching glue correcting method |
| CN101133682A (en) * | 2005-03-03 | 2008-02-27 | 应用材料股份有限公司 | Method for etching having a controlled distribution of process results |
| CN101320711A (en) * | 2007-06-05 | 2008-12-10 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and preparation thereof |
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| JP特开平10-308351A 1998.11.17 |
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