CN102377432B - Multiplex analog-to-digital conversion device - Google Patents
Multiplex analog-to-digital conversion device Download PDFInfo
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- CN102377432B CN102377432B CN201010264941.8A CN201010264941A CN102377432B CN 102377432 B CN102377432 B CN 102377432B CN 201010264941 A CN201010264941 A CN 201010264941A CN 102377432 B CN102377432 B CN 102377432B
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Abstract
The invention relates to a multiplex analog-to-digital conversion device which comprises two sampling maintenance circuits, a multi-path switch and an analog-to-digital converter, wherein the two sampling maintenance circuits are electrically connected with the multi-path switch; the analog-to-digital converter is electrically connected with the multi-path switch; the two sampling maintenance circuits respectively receive an I signal and a Q signal in I/Q signals and transmit the I signal and the Q signal to the multi-path switch; the multi-path switch changes the received I signal and Q signal into an I/Q staggered signal and transmits the I/Q staggered signal to the analog-to-digital converter; and the analog-to-digital converter processes the received I/Q staggered signal. According to the invention, the I/Q staggered signal is processed by utilizing one analog-to-digital converter, thereby realizing that the I/Q signal multiplexes the same analog-to-digital converter, reducing the area of a circuit and reducing the power of the circuit.
Description
Technical field
The present invention relates to a kind of signal processing apparatus, particularly a kind of device realizing utilizing an analog to digital converter to process i/q signal.
Background technology
ADC(Analog-to-Digital Converter, analog to digital converter) be radio frequency transceiver chip or other there is I/Q(In-phase/Quadrature, orthogonal in the same way) system of signal and the requisite module of chip.Radio frequency transceiver chip and digital baseband chip are most important chips in cell phone system, and therefore ADC is also absolutely necessary in cell phone system.
During radio frequency transceiver chip operation, signal is also demodulated to i/q signal by frequency mixer by signal in receiving path, and the phase difference of i/q signal is apart from 90 degree, and i/q signal is by delivering to ADC after Analog Baseband process.Way current is at present employing two ADC, and I signal uses an ADC, and Q signal uses another ADC.Owing to employing two ADC respectively for i/q signal, therefore its area and power consumption are all larger, and also there is mismatch between ADC.
Summary of the invention
Technical problem to be solved by this invention is to provide the multiplexing adc circuit of a kind of I/Q, realizes the multiplexing same ADC of i/q signal, thus reduces area and reduce circuit power consumption.
The technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of multiplex analog-to-digital conversion device, comprises two sampling hold circuits, the variable connector be electrically connected with two sampling hold circuits, and the analog to digital converter be electrically connected with variable connector; Described two sampling hold circuits receive I signal in i/q signal and Q signal respectively, and send variable connector to, the I signal received and Q signal are become I/Q interleaving signal and send analog to digital converter to by described variable connector, and described analog to digital converter processes the I/Q interleaving signal received;
Described two sampling hold circuits are identical with the clock frequency of variable connector, and the clock frequency of described analog to digital converter is 2 times of two sampling hold circuits and variable connector clock frequency;
Described two sampling hold circuits and variable connector synchronous working.
The invention has the beneficial effects as follows: by two sampling hold circuits to I signal and Q signal respectively but gather simultaneously and be converted to I/Q interleaving signal by the signal that sampling hold circuit sends by a variable connector, I/Q interleaving signal is the I signal and Q signal that successively produce in a time cycle, an analog to digital converter is utilized to process I/Q interleaving signal, thus realize the multiplexing same analog to digital converter of i/q signal, reduce circuit area and reduce circuit power consumption.Achieve the I signal of analog to digital converter in the middle of the reason I/Q interleaving signal of its different rising edge clock punishment other places and Q signal.
On the basis of technique scheme, the present invention can also do following improvement.
Further, the clock frequency of described two sampling hold circuits and variable connector is 30.72MHz, and the clock frequency of described analog to digital converter is 61.44MHz.
Further, the clock duty cycle of described two sampling hold circuits is 1/4, and the clock duty cycle of described variable connector is 1/2.
Further, the rising edge of described analog to digital converter clock is in advance in the rising edge of variable connector clock.
The beneficial effect of above-mentioned further scheme is adopted to be ensure that analog to digital converter can both process I signal or Q signal at each rising edge.
The present invention adopts two sampling hold circuits, is realized the problem of the multiplexing analog to digital converter of i/q signal by the application of new clock.Although the clock frequency that analog to digital converter carries out sampling adds one times, but area and power consumption still use two analog to digital converters little than i/q signal two-way respectively, and there is not mismatch between analog to digital converter, only has the being unworthy of property between sampling hold circuit, by the appropriate design to sampling hold circuit, the being unworthy of property between sampling hold circuit can accomplish not affect system.
Accompanying drawing explanation
Fig. 1 is the structure principle chart of multiplex analog-to-digital conversion device of the present invention;
Fig. 2 is multiplex analog-to-digital conversion device sequential chart of the present invention.
Embodiment
Be described principle of the present invention and feature below in conjunction with accompanying drawing, example, only for explaining the present invention, is not intended to limit scope of the present invention.
As shown in Figure 1, multiplex analog-to-digital conversion device of the present invention comprises the first sampling hold circuit 1, second sampling hold circuit 2, variable connector 3 and analog to digital converter 4, wherein the first sampling hold circuit 1 and the second sampling hold circuit 2 are electrically connected with variable connector 3 respectively, and variable connector 3 is electrically connected with analog to digital converter 4.
First sampling hold circuit 1 and the second sampling hold circuit 2 receive I signal in i/q signal and Q signal respectively, I signal becomes IOUT+-signal through the first sampling hold circuit 1, Q signal becomes QOUT+-signal through the second sampling hold circuit 2, IOUT+-signal and QOUT+-signal are sent to variable connector 3 by the first sampling hold circuit 1 and the second sampling hold circuit 2 respectively, the IOUT+-signal received and QOUT+-signal are become INP/INN signal by variable connector 3, and INP/INN signal is sent to analog to digital converter 4, analog to digital converter 4 processes received INP/INN signal.
In Fig. 1, the clock of the first sampling hold circuit 1 is CK1, and the clock of the second sampling hold circuit 2 is CK2, and the clock of variable connector 3 is CK3, and the clock of analog to digital converter 4 is CK_ADC; Clock CK1, CK2, CK3 and CK_ADC provide by clock processing module.
In present embodiment, first sampling hold circuit 1, the clock frequency of the second sampling hold circuit 2 and variable connector 3 all adopts 30.72MHz, the clock frequency that analog to digital converter 4 adopts is the first sampling hold circuit 1, second sampling hold circuit 2 and variable connector 3 adopt 2 times of clock frequency, be specially 61.44MHz, the clock duty cycle of the first sampling hold circuit 1 and the second sampling hold circuit 2 is 1/4, the clock duty cycle of variable connector 3 is 1/2, the clock CK1 of the first sampling hold circuit 1, the rising edge alignment of the clock CK2 of the second sampling hold circuit 2 and the clock CK3 of variable connector 3, namely trigger rising edge simultaneously, the rising edge of the clock CK_ADC of analog to digital converter 4 shifts to an earlier date some time than the rising edge of the clock CK3 of variable connector 3.Certainly, multiplex analog-to-digital conversion device of the present invention also can select other clock frequency value as required, present embodiment is only described as instantiation, the clock duty cycle of the first sampling hold circuit 1, second sampling hold circuit 2 and variable connector 3 is also a preferably execution mode, and other clock duty cycles also can be adopted to realize.The setting of above-described clock frequency and clock duty cycle, just a kind of embodiment of the present invention, is not intended to limit the present invention.
Fig. 2 is multiplex analog-to-digital conversion device sequential chart of the present invention.As shown in Figure 2, during multiplex analog-to-digital conversion device work of the present invention, the clock CK1 of the first sampling hold circuit 1 is identical with the clock CK2 of the second sampling hold circuit 2, the time in 1/4 cycle is used for carrying out sampling hold circuit signal sampling, is used for for 3/4 cycle time carrying out the maintenance of sampling hold circuit signal.I/q signal becomes IOUT+-signal and QOUT+-signal respectively after the first sampling hold circuit 1 and the second sampling hold circuit 2, and when the trailing edge of the clock CK1 of the first sampling hold circuit 1 and clock CK2 of the second sampling hold circuit 2, IOUT+-signal and QOUT+-signal start to export.IOUT+-signal and QOUT+-signal control through variable connector 3 that (namely the clock CK3 of variable connector 3 is in high level and passes I signal, passes Q signal when being in low level; Certainly, also can pass Q signal when clock CK3 is in high level as required, be in low level pass I signal) after become INP/INN signal, INP/INN signal is I/Q interleaving signal, and INP/INN signal is sent to analog to digital converter 4 by variable connector 3.Analog to digital converter 4 first rising edge process I signal of 2 times of clock frequency (61.44M) clock CK_ADC of variable connector 3 clock frequency, second rising edge process Q signal, thus realize I signal and Q signal is multiplexing.
In the present invention, namely sampling hold circuit can adopt the design of the circuit of identical parameters, also can adopt the circuit design of different parameters; As adopted the circuit design of different parameters, retention time many sampling hold circuit (the second sampling hold circuit 2 adopting Q signal in corresponding diagram 1) circuit performance requirement is lower.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a multiplex analog-to-digital conversion device, is characterized in that: comprise two sampling hold circuits, the variable connector be electrically connected with two sampling hold circuits, and the analog to digital converter be electrically connected with variable connector; Described two sampling hold circuits receive I signal in i/q signal and Q signal respectively, and send variable connector to, the I signal received and Q signal are become I/Q interleaving signal and send analog to digital converter to by described variable connector, and described analog to digital converter processes the I/Q interleaving signal received;
Described two sampling hold circuits are identical with the clock frequency of variable connector, and the clock frequency of described analog to digital converter is 2 times of two sampling hold circuits and variable connector clock frequency; Analog to digital converter first rising edge process I signal of 2 times of clock frequency clocks of variable connector clock frequency, second rising edge process Q signal, thus realize I signal and Q signal is multiplexing;
Described two sampling hold circuits and variable connector synchronous working.
2. multiplex analog-to-digital conversion device according to claim 1, is characterized in that: the clock frequency of described two sampling hold circuits and variable connector is 30.72MHz, and the clock frequency of described analog to digital converter is 61.44MHz.
3. multiplex analog-to-digital conversion device according to claim 1, is characterized in that: the clock duty cycle of described two sampling hold circuits is 1/4, and the clock duty cycle of described variable connector is 1/2.
4. multiplex analog-to-digital conversion device according to claim 3, is characterized in that: the rising edge of described analog to digital converter clock is in advance in the rising edge of variable connector clock.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010264941.8A CN102377432B (en) | 2010-08-27 | 2010-08-27 | Multiplex analog-to-digital conversion device |
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| CN201010264941.8A CN102377432B (en) | 2010-08-27 | 2010-08-27 | Multiplex analog-to-digital conversion device |
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| CN102377432A CN102377432A (en) | 2012-03-14 |
| CN102377432B true CN102377432B (en) | 2015-01-07 |
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| CN103020566B (en) * | 2012-12-18 | 2016-02-17 | 深圳市华士精成科技有限公司 | A kind of radio-frequency identification reader/writer circuit for detecting intensity of received signal and detection method |
| JP6266328B2 (en) * | 2013-12-12 | 2018-01-24 | ザインエレクトロニクス株式会社 | Signal multiplexer |
| CN106411320B (en) * | 2016-09-07 | 2020-02-07 | 深圳怡化电脑股份有限公司 | Circuit for simulating signal |
| CN108923779B (en) * | 2018-07-09 | 2020-08-11 | 威创集团股份有限公司 | Signal multiplexing circuit and method |
| DE102019205040A1 (en) * | 2019-04-09 | 2020-10-15 | Sivantos Pte. Ltd. | Hearing aid and method for operating such a hearing aid |
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| CN1318957A (en) * | 2000-04-14 | 2001-10-24 | 朗迅科技公司 | Receiver system and method using RF analog-digital conversion |
| CN201393307Y (en) * | 2009-03-05 | 2010-01-27 | 京信通信系统（中国）有限公司 | Automatic searching module of GSM base station channel number |
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| KR100583723B1 (en) * | 2003-09-16 | 2006-05-25 | 삼성전자주식회사 | Apparatus for sampling a plurality of analog signals |
| JP4323968B2 (en) * | 2004-01-14 | 2009-09-02 | 株式会社日立コミュニケーションテクノロジー | Timing adjustment method for wireless communication device |
| US8089854B2 (en) * | 2007-04-03 | 2012-01-03 | Qualcomm, Incorporated | Companded transmit path for wireless communication |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1318957A (en) * | 2000-04-14 | 2001-10-24 | 朗迅科技公司 | Receiver system and method using RF analog-digital conversion |
| CN201393307Y (en) * | 2009-03-05 | 2010-01-27 | 京信通信系统（中国）有限公司 | Automatic searching module of GSM base station channel number |
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