CN102376717A - Electrically erasable programmable read-only memory array operated under low voltage - Google Patents
Electrically erasable programmable read-only memory array operated under low voltage Download PDFInfo
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- CN102376717A CN102376717A CN2010102497307A CN201010249730A CN102376717A CN 102376717 A CN102376717 A CN 102376717A CN 2010102497307 A CN2010102497307 A CN 2010102497307A CN 201010249730 A CN201010249730 A CN 201010249730A CN 102376717 A CN102376717 A CN 102376717A
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Abstract
The invention discloses an electrically erasable programmable read-only memory array operated under low voltage, which comprises a plurality of parallel bit lines, word lines and common source lines. The bit lines are divided into first bit lines, the word lines comprise a first word line and a second word line, and the common source lines comprise a first common source line and a second common source line. The electrically erasable programmable read-only memory array also comprises a plurality of memory sub-arrays, each memory sub-array is connected with one bit line, two word lines and two common source lines and comprises a first memory unit cell and a second memory unit cell, the first memory unit cell is connected with the first bit line, the first common source line and the first word line, the second memory unit cell is connected with the first bit line, the second common source line and the second word line, and the first memory unit cell and the second memory unit cell are arranged symmetrically and are respectively arranged between the first common source line and the second common source line. The electrically erasable programmable read-only memory array can not only be operated under the low voltage, but also has the bit group writing and erasing functions.
Description
Technical field
The present invention is relevant a kind of memory array, particularly about a kind of eeprom array of low voltage operating.
Background technology
(Complementary Metal Oxide Semiconductor, CMOS) process technique has become ASIC (application specific integrated circuit, manufacturing approach commonly used ASIC) to the complementary metal oxide semiconductor.In today of computing information product prosperity; Flash memory (Flash) and the read-only read-only memory of electric erazable programmable (Electrically Erasable Programmable Read Only Memory; EEPROM) owing to all possessing the non-volatile memory function of electrically writing with erase data is arranged; And turn off the back data at power supply and can not disappear, so be widely used on the electronic product.
Nonvolatile memory is for programmable, its be in order to store charge changing the transistorized grid voltage of memory, or not store charge to stay the transistorized grid voltage of former memory.Erase operation for use then is that the electric charge that is stored in the nonvolatile memory is removed, and makes nonvolatile memory get back to the transistorized grid voltage of former memory.For present flash memory architecture, though area is less, cost is lower, only supports smearing of big block to write, and can't only smear a specific bit memory cell and write, and is inconvenient in the use; In addition for the framework of the read-only read-only memory of electric erazable programmable; Has the function that the bit group writes (byte write); Relatively flash memory uses more conveniently, and one of which bit memory cell circuit diagram, and memory cell structure cutaway view are respectively like Fig. 1, shown in Figure 2.Each memory cell comprises two-transistor: a memory transistor 10, is selected a transistor 12 and a capacitance structure 13; Capacitance structure 13 is tops of being located at memory transistor 10, with as a polysilicon memory cell, because such structure; Cause area big than flash memory; And carrying out bit when erasing, the position that often needs not choose isolates with transistor, and then the demand that raises the cost.
Therefore, the present invention is to above-mentioned puzzlement, proposes a kind of eeprom array of low voltage operating, to solve the problem that convention was produced.
Summary of the invention
Main purpose of the present invention; Be to provide a kind of eeprom array of low voltage operating; It is to have small size and EEPROM framework cheaply, and the bias voltage mode of low-voltage more capable of using is reached the function that the bit group writes and erases.
For reaching above-mentioned purpose; The present invention provides a kind of eeprom array of low voltage operating; Comprise a plurality of parallel bit lines, it is to comprise one first bit line, and word line that the bit line is parallel with a plurality of and common source line are orthogonal; And word line comprises first, second word line, and the common source line comprises first, second common source line.Other has the complex operator memory array; Each quantum memory array connects a bit line, two word lines and two common source lines, and each quantum memory array comprises first, second memory cell, and first memory cell connects the first bit line, the first common source line and first word line; Second memory cell connects the first bit line, the second common source line and second word line; First, second memory cell is in the shared same contact of the first bit line, and balanced configuration mutually, and all between first, second common source line.
First, second memory cell is all as an operative memory structure cell; Choose memory cell in one of them conduct of selection operation memory cell; When operating, and choose the operative memory structure cell that memory cell is connected same bit line, and not with choose the operative memory structure cell that memory cell is connected same common source line; As plural coordination metamemory structure cell; With choose the operative memory structure cell that memory cell is connected same word line, with the word memory cell, all the other operative memory structure cells are not then chosen memory cell as plural number as plural number.
First, second memory cell all tool is arranged in the N type field-effect transistor of p type wells district or P type substrate, and also or all tool is arranged in the P type field-effect transistor of N type wellblock or N type substrate.
When memory cell tool N type field-effect transistor, and desire when operation, then apply basic voltage V in choosing p type wells district or the P type substrate that memory cell connects
Subp, and apply the first bit voltage V respectively in choosing bit line, word line, the common source line that memory cell connects
B1, the first word voltage V
W1, the first common source voltage V
S1, the word line, the common source line that connect in each coordination metamemory structure cell apply the second word voltage V respectively
W2, the second common source voltage V
S2, apply the second bit voltage V respectively with bit line, common source line that the word memory cell connects in each
B2, the first common source voltage V
S1, the word line that connects in the homology memory cell applies the second word voltage V
W2, apply the second bit voltage V respectively in each bit line, word line, common source line of not choosing the memory cell connection
B2, the second word voltage V
W2, the second common source voltage V
S3, when memory cell tool N type field-effect transistor, satisfy following condition: write fashionablely, satisfy V
B2Be suspension joint, V
SubpGround connection, and V
B1＞V
S1, V
W1＞V
S1, V
B1＞V
S1＞0, V
B1＞V
W2＞0, V
B1＞V
S2＞0; When erasing, satisfy V
S1Be ground connection, V
SubpGround connection, V
B2Be suspension joint, V
B1＞V
W2＞V
W1>=0, V
B1＞V
S2＞V
W1>=0.
When memory cell tool P type field-effect transistor, apply basic voltage V in N type substrate or the N type wellblock of choosing the memory cell connection
Subn, and satisfy following condition: write fashionablely, satisfy V
B2Be suspension joint, and V
Subn＞V
S1＞V
B1, V
Subn＞V
S1＞V
W1, V
Subn＞V
S2＞V
B1, V
Subn＞V
W2＞V
B1When erasing, V
B2Be suspension joint, V
Subn=V
S1>=V
W1＞V
B1, V
Subn＞V
S2＞V
B1, V
Subn＞V
W2＞V
B1
Now for making architectural feature of the present invention and the effect reached more there are further understanding and understanding, sincerely helps with preferred embodiment figure and cooperate detailed explanation, explain as afterwards:
Description of drawings
Fig. 1 is a bit memory cell circuit diagram of prior art;
Fig. 2 is the structure cutaway view of a bit memory cell of prior art;
Fig. 3 is a circuit diagram of the present invention;
Fig. 4 is a circuit layout sketch map of the present invention;
Fig. 5 is the circuit diagram of quantum memory array of the present invention;
Fig. 6 is the structure cutaway view of N type field-effect transistor of the present invention and electric capacity;
Fig. 7 is the structure cutaway view of P type field-effect transistor of the present invention and electric capacity.
Description of reference numerals:
10-remembers transistor; 12-selects transistor; The 13-capacitance structure; 14-bit line; The 16-first bit line; The 18-word line; 20-first word line; 22-second word line; 24-common source line; The 26-first common source line; The 28-second common source line; 30-quantum memory array; 32-first memory cell; 34-second memory cell; The 36-field-effect transistor; 38-electric capacity; The 40-field-effect transistor; 42-electric capacity; The 44-drain contact; 46-N type field-effect transistor; 47-P type field-effect transistor; 48-P N-type semiconductor N substrate; 49-N N-type semiconductor N substrate; The 50-floating grid; The 52-oxide layer; 54-controls grid; 56-electric capacity.
Embodiment
Below please consult Fig. 3 and Fig. 4 simultaneously.The present invention comprises a plurality of parallel bit lines 14, and it is to comprise one first bit line 16.Other has and bit line 14 mutually perpendicular a plurality of parallel word lines 18, and it is to comprise first, second word line 20,22.With word line 18 parallel to each other a plurality of parallel common source lines 24 are arranged, it is to comprise first, second common source line 26,28.Above-mentioned bit line 14, word line 18 can be connected complex operator memory array 30, i.e. 2x1 bit memory cell with common source line 24.Each quantum memory array 30 connects a bit line 14, two word lines 18 and a common source line 24.Because the annexation of each quantum memory array 30 and bit line 14, two word lines 18, common source line 24 is very close, below the statement that just exists together mutually.
See also Fig. 4 and Fig. 5; Each quantum memory array 30 comprises first, second memory cell 32,34; First memory cell 32 connects the first bit line 16, first word line 20 and the first common source line, 26, the second memory cells, 34 connections, the first bit line 16, second word line 22 and the second common source line 28, first, second memory cell 32,34 mutual balanced configurations; And all at first, second common source line 26, between 28, the common source line 24 that first, second memory cell 32,34 connects is not shared.Because first, second memory cell 32,34 all connects the first bit line 16, therefore also in the first bit line, 16 shared same contacts.
Please consult Fig. 3 again; Above-mentioned field- effect transistor 36,40 can be all the N type field-effect transistor that is arranged in P type substrate or p type wells district; Also or be arranged in the P type field-effect transistor of N type substrate or N type wellblock; And mode of operation of the present invention is below first talked about light field effect transistor 36,40 and is the mode of operation of N type field-effect transistor in response to N type or P type field-effect transistor and difference is arranged.In order to clearly demonstrate this mode of operation, need the name of each memory cell is called clear and definite definition:
Above-mentioned first, second memory cell 32,34 is all as an operative memory structure cell, and can choose these a little operative memory structure cells one of them as choosing memory cell, to operate.With choose memory cell and be connected same bit line 14, and not with choose the operative memory structure cell that memory cell is connected same common source line 24, as plural coordination metamemory structure cell; With choose the operative memory structure cell that memory cell is connected same word line 18, as plural number with the word memory cell; All the other operative memory structure cells are not then chosen memory cell as plural number in addition.
Mode of operation of the present invention is following, the mode of operation below utilizing, and the memory cell that other are not chosen is unaffected, to operate specific single memory cell.
P type substrate or p type wells district in choosing the memory cell connection apply basic voltage V
Subp, and apply the first bit voltage V respectively in choosing bit line 14, word line 18, the common source line 24 that memory cell connects
B1, the first word voltage V
W1, the first common source voltage V
S1, the word line 18, the common source line 24 that connect in each coordination metamemory structure cell apply the second word voltage V respectively
W2, the second common source voltage V
S2, apply the second bit voltage V respectively with bit line 14, common source line 24 that the word memory cell connects in each
B2, the first common source voltage V
S1, apply the second bit voltage V respectively in each bit line 14, word line 18, common source line 24 of not choosing the memory cell connection
B2, the second word voltage V
W2, the second common source voltage V
S2, and satisfy following condition: write fashionablely, satisfy V
B2Be suspension joint, V
SubpGround connection, and V
B1＞V
S1, V
W1＞V
S1, V
B1＞V
S1＞0, V
B1＞V
W2＞0, V
B1＞V
S2＞0; When erasing, satisfy V
S1Be ground connection, V
SubpGround connection, V
B2Be suspension joint, V
B1＞V
W2＞V
W1>=0, V
B1＞V
S2＞V
W1>=0.
When field- effect transistor 36,40 is P type field-effect transistor, more in applying basic voltage V in N type substrate or the N type wellblock of choosing the memory cell connection
Subn,, according to the definition of above-mentioned memory cell and voltage, write fashionablely, satisfy V
B2Be suspension joint, and V
Subn＞V
S1＞V
B1, V
Subn＞V
S1＞V
W1, V
Subn＞V
S2＞V
B1, V
Subn＞V
W2＞V
B1When erasing, V
B2Be suspension joint, V
Subn=V
S1>=V
W1＞V
B1, V
Subn＞V
S2＞V
B1, V
Subn＞V
W2＞V
B1
Utilize above-mentioned bias voltage mode, can before not adding isolated transistor, put, can reach nonvolatile storage equally and use upper tuple to write the function of (byte write is also referred to as byte and writes), byte erase (byte erase is also referred to as byte and erases).
When memory cell during in the operation of doing to write; Its voltage is boosted via charge pump (charg epump) by about 2.5 volts or 3.3 volts and is added to a stable high voltage; But, can cause electric current generation between drain electrode and source electrode, and make high pressure produce change because of pressure reduction between drain electrode and source electrode; When electric current is healed big; The change that high pressure produces is bigger, and its required charge pump (charge pump) is stronger, and the area on layout is also bigger; Usually the Flash framework is when doing programming; Its biasing is: grid capacitance and drain electrode add high pressure, source ground, and electric current is about 500u ampere/bit between its drain electrode and source electrode; And the present invention is when stylizing, and institute's biasing is: grid capacitance and drain electrode add high pressure, and source electrode adds in one presses, and electric current is about 50u ampere/bit between its drain electrode and source electrode.The present invention is under the added low bias condition of programming, and it is less to produce electric current, and the area on charge pump (charge pump) layout is also less.
Below introduce the structure cutaway view of field- effect transistor 36,40 and electric capacity 38,42, and be example with N type field-effect transistor.See also Fig. 6; N type field-effect transistor 46 is located in the P type semiconductor substrate 48 as semiconductor substrate; And has a floating grid 50; Be provided with an oxide layer 52 and a control grid 54 on this floating grid 50 in regular turn, control grid 54 is to form electric capacity 56 with oxide layer 52, floating grid 50, and the material of floating grid 50 and control grid 54 is all polysilicon.When semiconductor substrate is the N type, then can in substrate, establish a p type wells district, let N type field-effect transistor 46 be located in the p type wells district again.If P type field-effect transistor is as long as the dopant profile of source electrode, drain electrode, wellblock and substrate is done corresponding exchange, as shown in Figure 7.P type field-effect transistor 47 is located in the N type semiconductor substrate 49 as semiconductor substrate; And has a floating grid 50; Be provided with an oxide layer 52 and a control grid 54 on this floating grid 50 in regular turn; Control grid 54 is to form electric capacity 56 with oxide layer 52, floating grid 50, and floating grid 50 is all polysilicon with the material of controlling grid 54.When semiconductor substrate is the P type, then can in substrate, establish a N type wellblock, let P type field-effect transistor 47 be located in the N type wellblock again.The structural design of this kind memory cell, i.e. flash memory (Flash) framework can significantly reduce the area and the cost thereof of non-volatile memory array.
In sum, the present invention not only has the less and lower-cost flash framework of area, and bias voltage mode more capable of using is to reach the character group and write the function of (byte write).
The above; Be merely the present invention's one preferred embodiment; Be not to be used for limiting the scope that the present invention implements,, all should be included in the claim scope of the present invention so the equalization of doing according to the described shape of claim of the present invention, structure, characteristic and spirit such as changes and modifies.
Claims (7)
1. the eeprom array of a low voltage operating is characterized in that, comprises:
The bit line that a plurality of are parallel, it is to comprise one first bit line;
The word line that a plurality of are parallel, it is orthogonal with those bit lines, and comprises first, second word line;
The common source line that a plurality of are parallel is parallel to each other with those word lines, and comprises first, second common source line; And
The complex operator memory array, each this quantum memory array connects this bit line, two these word lines and two these common source lines, and between two these common source lines, each this quantum memory array comprises:
One first memory cell, it is to connect this first bit line, this first common source line and this first word line; And
One second memory cell; It is to connect this first bit line, with the shared same contact of this first memory cell, and connect this second common source line and this second word line; The mutual balanced configuration of this first, second memory cell again, and between this first, second common source line.
2. the eeprom array of low voltage operating according to claim 1; It is characterized in that; When this first, second memory cell all comprised the N type field-effect transistor that is arranged in P type substrate or p type wells district, this first, second memory cell was all as an operative memory structure cell, choose those operative memory structure cells one of them as choosing memory cell; When operating; Choose memory cell with this and be connected same this bit line, and do not choose those operative memory structure cells that memory cell is connected same this common source line, as plural coordination metamemory structure cell with this; Choose those operative memory structure cells that memory cell is connected same this word line with this; With the word memory cell, all the other those operative memory structure cells are not then chosen memory cell as plural number as plural number, this is chosen memory cell carry out method of operating and comprise:
Apply basic voltage V in this this P type substrate or this p type wells district that chooses the memory cell connection
Subp, and choose this bit line, this word line, this common source line that memory cell connects in this and apply the first bit voltage V respectively
B1, the first word voltage V
W1, the first common source voltage V
S1, this word line, this common source line of connecting in each this coordination metamemory structure cell apply the second word voltage V respectively
W2, the second common source voltage V
S2, should apply the second bit voltage V respectively with this bit line, this common source line that the word memory cell connects in each
B2, the first common source voltage V
S1, this this bit line, this word line, this common source line of not choosing the memory cell connection applies the second bit voltage V respectively in each
B2, the second word voltage V
W2, the second common source voltage V
S2, and satisfy following condition:
Write fashionablely, satisfy V
B2Be suspension joint, V
SubpGround connection;
V
b1＞V
S1；
V
w1＞V
S1；
V
b1＞V
S1＞0；
V
B1＞V
W2＞0; And
V
B1＞V
S2＞0; And
When erasing, satisfy V
S1Be ground connection, V
B2Be suspension joint, V
SubpGround connection;
V
B1＞V
W2＞V
W1>=0; And
V
b1＞V
S2＞V
w1≥0。
3. the eeprom array of low voltage operating according to claim 1; It is characterized in that; When this first, second memory cell all comprised the P type field-effect transistor that is arranged in N type substrate or N type wellblock, this first, second memory cell was all as an operative memory structure cell, choose those operative memory structure cells one of them as choosing memory cell; When operating; Choose memory cell with this and be connected same this bit line, and do not choose those operative memory structure cells that memory cell is connected same this common source line, as plural coordination metamemory structure cell with this; Choose those operative memory structure cells that memory cell is connected same this word line with this; With the word memory cell, all the other those operative memory structure cells are not then chosen memory cell as plural number as plural number, this is chosen memory cell carry out method of operating and comprise:
Apply basic voltage V in this this N type substrate or this N type wellblock of choosing the memory cell connection
Subn, and choose this bit line, this word line, this common source line that memory cell connects in this and apply the first bit voltage V respectively
B1, the first word voltage V
W1, the first common source voltage V
S1, this word line, this common source line of connecting in each this coordination metamemory structure cell apply the second word voltage V respectively
W2, the second common source voltage V
S2, should apply the second bit voltage V respectively with this bit line, this common source line that the word memory cell connects in each
B2, the first common source voltage V
S1, this this bit line, this word line, this common source line of not choosing the memory cell connection applies the second bit voltage V respectively in each
B2, the second word voltage V
W2, the second common source voltage V
S2, and satisfy following condition:
Write fashionablely, satisfy V
B2Be suspension joint;
V
subn＞V
S1＞V
b1；
V
subn＞V
S1＞V
w1；
V
Subn＞V
S2＞V
B1And
V
Subn＞V
W2＞V
B1And
When erasing, V
B2Be suspension joint;
V
subn＝V
S1≥V
w1＞V
b1；
V
Subn＞V
S2＞V
B1And
V
subn＞V
w2＞V
b1。
4. the eeprom array of low voltage operating according to claim 1 is characterized in that, this first memory cell more comprises:
One field-effect transistor, tool one floating grid, and the drain electrode of this field-effect transistor connects this first bit line, with the shared same contact of this second memory cell, its source electrode connects this first common source line; And
One electric capacity; The one of which end connects this floating grid; The other end connects this first word line; Receiving the bias voltage of this first word line, this field-effect transistor receives the bias voltage of this first bit line and this first common source line, this floating grid of this field-effect transistor is write data maybe the data of this floating grid of this field-effect transistor is erased.
5. the eeprom array of low voltage operating according to claim 1 is characterized in that, this second memory cell more comprises:
One field-effect transistor, tool one floating grid, and the drain electrode of this field-effect transistor connects this first bit line, with the shared same contact of this first memory cell, its source electrode connects this second common source line; And
One electric capacity; The one of which end connects this floating grid, and the other end connects this second word line, to receive the bias voltage of this second word line; This field-effect transistor receives the bias voltage of this first bit line and this second common source line, this floating grid is write data maybe the data of this floating grid is erased.
6. according to the eeprom array of claim 4 or 5 described low voltage operatings, it is characterized in that this field-effect transistor is N type field-effect transistor or P type field-effect transistor.
7. according to the eeprom array of claim 4 or 5 described low voltage operatings; It is characterized in that; This field-effect transistor is located in the semiconductor substrate; Be provided with an oxide layer and a control grid on this floating grid in regular turn, this control grid and this oxide layer, this this electric capacity of floating grid formation, and this floating grid and this control grid are all polysilicon.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102917177A (en) * | 2012-10-22 | 2013-02-06 | 清华大学 | Floating gate type image sensor array structure and read-out method thereof |
| CN110880350A (en) * | 2018-09-06 | 2020-03-13 | 亿而得微电子股份有限公司 | Method for operating low-current electrically erasable rewritable read-only memory array |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310800B1 (en) * | 1997-12-12 | 2001-10-30 | Matsushita Electronics Corporation | Non-volatile semiconductor memory device and method for driving the same |
| CN1512587A (en) * | 2002-12-30 | 2004-07-14 | 旺宏电子股份有限公司 | Structure of non-volatile memory and its operation method |
| US7733693B2 (en) * | 2003-05-13 | 2010-06-08 | Innovative Silicon Isi Sa | Semiconductor memory device and method of operating same |
-
2010
- 2010-08-05 CN CN 201010249730 patent/CN102376717B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310800B1 (en) * | 1997-12-12 | 2001-10-30 | Matsushita Electronics Corporation | Non-volatile semiconductor memory device and method for driving the same |
| CN1512587A (en) * | 2002-12-30 | 2004-07-14 | 旺宏电子股份有限公司 | Structure of non-volatile memory and its operation method |
| US7733693B2 (en) * | 2003-05-13 | 2010-06-08 | Innovative Silicon Isi Sa | Semiconductor memory device and method of operating same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102917177A (en) * | 2012-10-22 | 2013-02-06 | 清华大学 | Floating gate type image sensor array structure and read-out method thereof |
| CN110880350A (en) * | 2018-09-06 | 2020-03-13 | 亿而得微电子股份有限公司 | Method for operating low-current electrically erasable rewritable read-only memory array |
| CN110880350B (en) * | 2018-09-06 | 2021-08-13 | 亿而得微电子股份有限公司 | Method for operating low-current electrically erasable rewritable read-only memory array |
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