CN102360564A

CN102360564A - Twin transistor memory

Info

Publication number: CN102360564A
Application number: CN 201110285756
Authority: CN
Inventors: 陈静; 余涛; 罗杰馨; 伍青青; 柴展
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2011-09-23
Filing date: 2011-09-23
Publication date: 2012-02-22
Anticipated expiration: 2031-09-23
Also published as: CN102360564B

Abstract

The invention provides a twin transistor memory which comprises an I-MOS (Impact-Ionization Metal Oxide Semiconductor) transistor and an MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), wherein the grid electrode of the I-MOS transistor is connected with a word line, the drain electrode of the I-MOS transistor is connected with a first bit line, the grid electrode of the MOSFET is connected with the source electrode of the I-MOS transistor, the drain electrode of the MOSFET is connected with a second bit line, and the source electrode of the MOSFET is grounded. In the invention, the twin transistor memory composed of the I-MOS transistor and the MOSFET not only has very high switching speed but also can effectively avoid the influence of the GIDL (Gate Induced Drain Leakage) current in a '0' state, thereby prolonging the '0' state retention time.

Description

The pair transistor reservoir

Technical field

The present invention relates to microelectronics and solid state electronics technical field, particularly relating to a kind of novel high-density does not have electric capacity TTRAM pair transistor reservoir.

Background technology

Tradition DRAM storage unit comprises a MOSFET, and (Metal-Oxide-Semiconductor Field-Effect Transistor is MOSFET) with a mos capacitance (being 1T1C).Wherein, MOSFET is equivalent to a switch, is used for the operation that the control store unit writes, upgrades and read, and the mos capacitance device is then as the usefulness of charge storage.In practical application, the electric charge that is stored on the capacitor can run off gradually, so the work of DRAM is " dynamically ", need do periodically and refresh.According to the mole theorem, as long as DIY hardware is updating, the internal memory specification also will constantly substitute, and the size of capacitor will seriously hinder the further reduction of memory cell area with being coupled among traditional DRAM.Therefore, people propose to utilize the intrinsic floater effect of SOI MOSFET to realize the notion of dynamic storage cell.

In storer family, two big typical structure types are arranged based on float structure (FBC).A kind ofly be: the Z-RAM that created out by Switzerland Innovative Silicon company in 2002 (Zero capacitor RAM) technology; It is not to adopt the electric charge that is stored in the capacitor to come expression information, stores data but under the raceway groove of a traditional SOI (SOI) MOSFET, catch electric charge through the DRAM unit that adopts this technology.This Z-RAM technology based on float structure (FBC) is to adopt single-transistor (1T) structure.Therefore, it can have the access speed of nearly SRAM and the memory density that surpasses traditional DRAM.Other one type is: 2005, Japanese Renesas company proposed the notion of TTRAM, and it is in series by two identical PD-SOI n type MOSFET.Last transistor plays read/write function, and back one transistor is a storage unit.Its advantage is: (1) fully with CMOS process compatible, though cellar area than Z-RAM (1T) structure greatly, but less than the storage unit of traditional 1T1C.(2) operating voltage is compatible mutually with the voltage of CMOS logical circuit fully, and different with the Z-RAM single-transistor is (at least 3 kinds of operating voltages), and TTRAM only needs VDD, VDD/2 and 0 three kinds of voltages, has reduced the requirement to peripheral circuit.(3) retention time (retention time) of TTRAM storage unit differentiation " 0 " and one state will be longer than the Z-RAM unit.

Wherein, the retention time is important index of DRAM storage unit.Retention time can be distinguished " 0 " and the longest time of one writing state exactly, also can think the refresh time that storage unit is the longest.Because the biasing keeping the attitude bit line is different, can cause the retention time of " 0 " and " 1 " to have a strong impact on.For example " 0 " has write the floater effect unit; Get into hold mode then, if again to carry out the one writing operation with array storage unit, bit line will certainly be biased to higher positive voltage; Because the public bit line of same column; So the bit line of storage unit that is in maintenance " 0 " state is being also for just, like this can anti-tagma partially to the P-N knot of drain electrode, produce reverse leakage.Can produce the GIDL effect in addition, described GIDL effect is meant: grid adds negative bias, forms accumulation layer in channel surface; Drain electrode simultaneously adds positive voltage; Can occur exhausting in the overlapping region of grid and drain electrode, finally form inversion layer, the result causes band to band tunneling tunnelling.Like this, the electronics in tagma can be tunneling to drain electrode, stays the hole in the tagma, finally causes keeping " 0 " attitude to have a strong impact on.In other words, because the existence of GIDL electric current can make the tagma constantly charge, thereby change " 0 " state, the retention time of state is in worst case that Here it is " 0 ".

Summary of the invention

The shortcoming of prior art in view of the above; The object of the present invention is to provide a kind of pair transistor reservoir; So that it not only has very fast switching speed, and the influence of GIDL electric current can effectively avoid " 0 " state the time, thereby improve " 0 " attitude retention time.

For realizing above-mentioned purpose and other relevant purposes; The present invention provides a kind of pair transistor reservoir; It is characterized in that; Comprise: the I-MOS pipe; Have buried insulator layer, comprise first source region, first drain region and in the intrinsic region between said first source region and first drain region and in first drain electrode in first source electrode in corresponding said first source region on the said semiconductor layer, corresponding said first drain region and at the first grid insulation course of corresponding said intrinsic region also between said first source electrode and first drain electrode at the semiconductor layer on the said buried insulator layer, said semiconductor layer; One side of said first grid insulation course upper surface is piled up first grid is arranged, and said first grid is connected with word line, and said first drain electrode is connected with first bit line; And MOSFET pipe; Have substrate, be formed with second source region, be formed with second drain region at the opposite side of said substrate in said substrate one side, at second drain electrode and second gate insulation layer between said second source electrode drains with second in second source electrode in corresponding said second source region on the said substrate, corresponding said second drain region; Pile up on said second gate insulation layer second grid is arranged; Said second grid connects said first source electrode; Said second drain electrode is connected with second bit line, said second source ground.

Pair transistor reservoir of the present invention wherein, comprises effective channel region in the intrinsic region of said I-MOS pipe, and the width of said effective channel region changes with the grid voltage size that applies on the said first grid.Said I-MOS pipe is P type raceway groove I-MOS pipe.

Pair transistor reservoir of the present invention, wherein, said MOSFET pipe is enhancement mode MOSFET pipe, perhaps is depletion type MOS FET pipe.

As stated, pair transistor reservoir of the present invention and the structural difference of traditional TTRAM are: the T1 pipe adopts I-MOS structure (Impact-Ionization MOS), and the T2 pipe is normal MOSFET.Its advantage is: not only have very fast switching speed, this can implement quick conversion to the writing of " 0 " and one state, maintenance, read states.And the influence of GIDL electric current can effectively avoid " 0 " state the time, thereby improve " 0 " attitude retention time.

Description of drawings

Fig. 1 is shown as pair transistor reservoir of the present invention and forms structural representation.

Fig. 2 is shown as the I-MOS tubular construction synoptic diagram in the pair transistor reservoir of the present invention.

When being shown as I-MOS of the present invention pipe OFF state, Fig. 3 a can be with synoptic diagram.

When being shown as I-MOS of the present invention pipe ON state, Fig. 3 b can be with synoptic diagram.

Fig. 4 is shown as the P-N knot synoptic diagram in the avalanche multiplication mechanism.

Embodiment

Below through specific instantiation embodiment of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this instructions disclosed.The present invention can also implement or use through other different embodiment, and each item details in this instructions also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.

See also Fig. 1 to Fig. 4; Need to prove; The diagram that is provided in the present embodiment is only explained basic conception of the present invention in a schematic way; Satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and plotted when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also maybe be more complicated.

See also Fig. 1, Fig. 1 is shown as pair transistor reservoir of the present invention and forms structural representation, and is as shown in the figure; The present invention provides a kind of pair transistor reservoir 1; Comprise I-MOS pipe 11 and MOSFET pipe 12, wherein, the grid of said I-MOS pipe 11 connects word line WL; The drain electrode of said I-MOS pipe 11 is connected with the first bit line BL1; The grid of said MOSFET pipe 12 connects the source electrode of said I-MOS pipe 11, and the drain electrode of said MOSFET pipe 12 is connected with the second bit line BL2, the source ground of said MOSFET pipe 12.In present embodiment, said I-MOS pipe 11 is a P type raceway groove I-MOS pipe.So be not limited thereto, said I-MOS pipe 11 also can be N type raceway groove I-MOS pipe.Said MOSFET pipe 12 is enhancement mode MOSFET pipe, perhaps is depletion type MOS FET pipe.

See also Fig. 2; Be shown as the I-MOS tubular construction synoptic diagram in the pair transistor reservoir of the present invention; As shown in the figure; Said I-MOS pipe 11 has buried insulator layer 111, is positioned at the semiconductor layer (indicating) on the said buried insulator layer 111, said semiconductor layer comprises first source region 112, first drain region 113 and the intrinsic region 114 between said first source region 112 and first drain region 113 and drain 116 and at said first the source electrode 115 and first also first grid insulation course 117 of corresponding said intrinsic region 114 that drains between 116 in first of first source electrode 115 in corresponding said first source region 112 on the said semiconductor layer, corresponding said first drain region 113; One side of said first grid insulation course 117 upper surfaces is piled up has first grid 118; Particularly; The area that said first grid 118 is laid is less than the area of said first grid insulation course 117; So that said first grid 118 is overlapping with the channel part of below, in other words, on said first grid insulation course 117, reserve Overlap.Wherein, comprise effective channel region in the intrinsic region 114 of said I-MOS pipe 11, the width of said effective channel region changes with the grid voltage size that applies on the said first grid 118.

Said I-MOS pipe 11 is through the adjusting of utilization to length of effective channel, and then the transverse electric field of control intrinsic region 114 is controlled a kind of gate control diode of open and close attitude.Adopting the P-I-N knot is in order to obtain lower avalanche breakdown field intensity, and this is that electric field required during puncture is bigger because the depletion widths of P-N knot is very narrow.In addition, when electronics obtains atomic time of enough kinetic collision intrinsic regions 114 from electric field, intrinsic region 114 can obtain more electron-hole pair.The unique texture of said I-MOS pipe 11, promptly first grid 118 not all with the ditch trace overlap, can effectively avoid the influence of GIDL electric current when maintenance " 0 " attitude.

Said MOSFET pipe 12 has substrate 121, is formed with second source region 122 in said substrate 121 1 sides, is formed with second drain region 123 at the opposite side of said substrate 121, at second source electrode 124 in corresponding said second source region 122 on the said substrate 121, second drain electrode 125 in corresponding said second drain region 123 and second gate insulation layer 126 that drains between 125 at said second source electrode 124 and second, piling up on said second gate insulation layer 126 has second grid 127.

Especially need to prove; In pair transistor reservoir 1 of the present invention; Said first grid 118 is connected with word line WL, and said first drain electrode 116 is connected with the first bit line BL1, and said second grid 127 connects said first source electrode 115; Said second drain electrode 125 is connected with the second bit line BL2, said second source electrode, 124 ground connection.

For further illustrating principle of the present invention and effect, see also Fig. 3 a to Fig. 4, at first see also Fig. 3 a, can be with synoptic diagram when being shown as I-MOS pipe OFF state.As shown in the figure, said I-MOS pipe 11 is under OFF state, and first grid 118 adds less positive bias, and can not form transoid and can not accumulate again this moment, and length of effective channel is whole intrinsic region 114.At this moment, transverse electric field is not enough to reach breakdown field strength, and the electronics of source end can't obtain enough energy generation ionizing collisions.

See also Fig. 3 b again, can be with synoptic diagram when being shown as I-MOS pipe ON state.As shown in the figure, said I-MOS pipe 11 is under ON state, and first grid 118 adds bigger negative bias, and accumulation P-district (Lgate as shown in Figure 1) appears in the raceway groove of said first grid 118 belows, thereby has shortened the length of effective channel of device.At this moment along with V _DSIncrease, a part of incremental voltage drop can drop on the LI zone (as shown in Figure 1), and the transverse electric field that promptly is added on the said intrinsic region 114 increases, and transverse electric field can increase along with the increase of grid voltage simultaneously.At this moment the electronics of first source electrode 115 can obtain enough kinetic energy, to such an extent as to when producing bump with intrinsic region 114 atoms, can destroy key and produce electron-hole pair, these process life and growth in nature successively produce new electron-hole pair.Because this multiplier effect makes to increase a large amount of charge carriers of the interior generation of potential barrier I district unit inverse current rapidly, thereby the P-N junction breakdown takes place.

See also Fig. 4, be shown as the P-N knot synoptic diagram in the avalanche multiplication mechanism.Said I-MOS pipe 11 is under bigger reverse biased; Electric field in the potential barrier intrinsic region 114 is very strong, and electronics in intrinsic region 114 and hole have very big kinetic energy owing to receive the drift action of highfield; When they and intrinsic region 114 interior character atoms bump; Can come out the electron collision on the valence link, become conduction electrons, produce a hole simultaneously.Electronics e collides out an electronics e and a hole h in the P-I-N junction barrier, and these three charge carriers are under the highfield effect, and motion also can continue to bump the mechanism of avalanche breakdown that Here it is in the opposite direction.Avalanche breakdown except with the barrier region in electric field intensity closely related; Also relevant with the barrier region width; Because the increase of charge carrier kinetic energy also needs an accelerator, if the barrier region is very thin; Even electric field very by force avalanche breakdown can not take place, this also is one of our reason of adopting broad intrinsic region 114.

By on can know that the principle of work of pair transistor reservoir 1 of the present invention is:

(a) one writing state, said first grid 118 adds negative bias, can occur accumulating the p district in the overlapping region of first grid 118 with raceway groove, and length of effective channel shortens to LI.Be biased to first drain electrode 116 just this moment; Avalanche breakdown enough greatly consequently takes place in the transverse electric field that is added on the LI zone, and the electronics of generation flows out through drain electrode, and the hole, tagma is managed 11 first source electrodes 115 through said I-MOS and discharged; Second grid 127 current potentials of said MOSFET pipe 12 are raised by the hole of said I-MOS pipe 11; Said MOSFET pipe 12 will be opened this moment, through measuring one writing, the distinguishable different conditions of the current value of two serial transistors when " 0 ".

(b) accomplish when one writing, get into the maintenance attitude.Only need this moment the first bit line BL1 zero offset, the hole is pumped to the P district storage that said 1-MOS manages 11 raceway grooves below.

When (c) reading " 1 ", WL adds positive potential with word line, and the hole is again by the second grid 127 of row to said MOSFET pipe 12, and this moment, said MOSFET pipe 12 was unlocked, and promptly can read current value by the second bit line BL2.

(d) write " 0 " state, said first grid 118 still adds negative bias, the p district can occur accumulating in the overlapping region of first grid 118 and raceway groove, and be biased to first drain electrode 116 negative this moment, and 11 first drain electrode, 116 discharges are managed in the hole thereupon by said I-MOS.

(e) accomplish when writing " 0 ", get into the maintenance attitude.Only need this moment the first bit line BL1 is biased to zero, do not had unnecessary hole in the at this moment said I-MOS pipe 11.

When (d) reading " 0 ", WL adds positive potential with word line, and this moment, said MOSFET pipe 12 still ended, and the current value that is read by the second bit line BL2 is zero.

Through distinguishing the current value of the said second bit line BL2 under the state of " 1 " " 0 ", can accomplish storage.

In sum, pair transistor reservoir of the present invention and the structural difference of traditional TTRAM are: the T1 pipe adopts I-MOS structure (Impact-Ionization MOS), and the T2 pipe is normal MOSFET.Its advantage is: not only have very fast switching speed, this can implement quick conversion to the writing of " 0 " and one state, maintenance, read states.And the influence of GIDL electric current can effectively avoid " 0 " state the time, thereby improve " 0 " attitude retention time.

The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any be familiar with this technological personage all can be under spirit of the present invention and category, the foregoing description is modified or is changed.Therefore, have common knowledge the knowledgeable in the affiliated such as technical field, must contain by claim of the present invention not breaking away from all equivalence modifications of being accomplished under disclosed spirit and the technological thought or changing.

Claims

1. a pair transistor reservoir is characterized in that, comprising:

The I-MOS pipe; Have buried insulator layer, comprise first source region, first drain region and in the intrinsic region between said first source region and first drain region and in first drain electrode in first source electrode in corresponding said first source region on the said semiconductor layer, corresponding said first drain region and at the first grid insulation course of corresponding said intrinsic region also between said first source electrode and first drain electrode at the semiconductor layer on the said buried insulator layer, said semiconductor layer; One side of said first grid insulation course upper surface is piled up first grid is arranged; Said first grid is connected with word line, and said first drain electrode is connected with first bit line; And

The MOSFET pipe; Have substrate, be formed with second source region, be formed with second drain region at the opposite side of said substrate in said substrate one side, at second drain electrode and second gate insulation layer between said second source electrode drains with second in second source electrode in corresponding said second source region on the said substrate, corresponding said second drain region; Pile up on said second gate insulation layer second grid is arranged; Said second grid connects said first source electrode; Said second drain electrode is connected with second bit line, said second source ground.

2. pair transistor reservoir according to claim 1 is characterized in that: comprise effective channel region in the intrinsic region of said I-MOS pipe, the width of said effective channel region changes with the grid voltage size that applies on the said first grid.

3. pair transistor reservoir according to claim 2 is characterized in that: said I-MOS pipe is P type raceway groove I-MOS pipe.

4. pair transistor reservoir according to claim 1 is characterized in that: said MOSFET pipe is enhancement mode MOSFET pipe.

5. pair transistor reservoir according to claim 1 is characterized in that: said MOSFET pipe is depletion type MOS FET pipe.