CN102360280B - Method for allocating registers for mixed length instruction set - Google Patents
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Abstract
The invention discloses a method for allocating registers for a mixed length instruction set. By less revising the conventional graph coloring register allocation method, namely fully utilizing the characteristics of a mixed coding instruction set, codes with higher code density are generated. The method has the characteristics of simplicity, practicability and high in reliability.
Description
Technical field
The present invention relates to a kind of technique of compiling, relate in particular to a kind of register allocation method for mixed length instructions collection.
Background technology
Embedded system often adopts RISC framework, and its instruction set is generally fixed length instruction set, only has the instruction of single length.Instruction length is generally integral words joint, for example, and 16 bit instructions, 32 bit instructions.The longer instruction length more operand of can encoding, the more register of addressing, or can use larger immediate etc., therefore generally there is better performance; And shorter instruction length can be so that the executable program that compiling generates be less.In order to have the high performance high code density simultaneously with short instruction of long instruction, modern risc processor starts to adopt the instruction set of two kinds or two or more different length instruction hybrid codings.For example, the cskyv2 instruction set of the thumb2 instruction set He Zhongtianwei company of ARM is all 16 instruction set (hereinafter to be referred as " shuffling instruction set ") with 32 bit instruction hybrid codings.
In shuffling instruction set, short instruction is compared long instruction, and the operand number of addressing is few, and the immediate scope of codified is little, or individual address is used component register only.For example, in cskyv2 instruction set, long instruction can be used all totally 32 general-purpose registers of R0 ~ R31, and most short instruction is used R0 ~ R15 totally 16 general-purpose registers only; Long instruction generally has 3 operands, and short instruction only has at most 2 operands.Short instruction is a subset of long instruction in function.Conventionally, compiler generates assembly instruction according to the function of long instruction, and assembler is while generating machine instruction, can decide and generate long instruction or short instruction according to the type of instruction and its operand.
Take cskyv2 as example, if certain register manipulation number of an instruction has been assigned with the register of R16 ~ R31, this instruction will generate a long instruction (except indivedual instructions, lower outside will introduction) so; Even but the register of R0 ~ R15 is only used in instruction, it also might not generate short instruction, because it may use the immediate that exceeds short instruction codified scope, or has used 3 different operands etc.Take cskyv2 as example, if certain register manipulation number of an instruction has been assigned with the register of R16 ~ R31, this instruction will generate a long instruction (except indivedual instructions, lower outside will introduction) so; Even but the register of R0 ~ R15 is only used in instruction, it also might not generate short instruction, because it may use the immediate that exceeds short instruction codified scope, or has used 3 different operands, etc.If one the final machine instruction generating of instruction is that long instruction or short instruction depend on its register being assigned to (hereinafter to be referred as category-A instruction); Otherwise if no matter which register its register manipulation number is assigned to, it must generate a long instruction, or must generate a short instruction (hereinafter to be referred as category-B instruction).As how less cost makes the final machine instruction generating of all category-A instructions, being short instruction, is the difficult point that technician need to overcome.
Summary of the invention
For above-mentioned technological difficulties, a kind of register allocation method for mixed length instructions collection of proposition of the present invention.
In order to solve the problems of the technologies described above, technical scheme of the present invention is as follows:
A register allocation method for mixed length instructions collection, comprises the steps:
1) search all life cycles in function, by zone bit is set, whether set judges that establishing this lifetime is category-A lifetime or category-B lifetime;
2) Renumber of the painted register allocation method of execution graph
1, build
1, coalesce
1, spill cost
1, and simplify
1five processes, for all category-As lifetime is distributed lo-regs register, the conflict graph G that obtains not carrying out any overflow operation
1;
3) computation-free lo-regs register is counted m, if described conflict graph G
1non-NULL, to count m be 0 to idle lo-regs register, if described conflict graph G
1for empty graph, the select of the painted register allocation method of execution graph
1process, and count m according to the lo-regs register of the register allocative decision computation-free generating, and record idle register information;
4) Renumber of the painted register allocation method of execution graph
2, build
2, coalesce
2, simplify
2, spill code
2and select
2process, for the category-B lifetime is distributed hi-regs register and m idle lo-regs register, and according to the hi-regs register quantity n of the allocative decision computation-free generating, and record idle register information;
5) the spill code of the painted register allocation method of execution graph
1and select
1process, if select
1process exists
Step 3) is carried out, and step finishes, if do not had, repeats spill code
1, Renumber
1, build
1, coalesce
1, spill cost
1, simplify
1process is until described conflict graph G
1for sky, then carry out select
1process is the category-A lifetime to generate register allocative decision;
Renumber
1, build
1, coalesce
1, spill cost
1, simplify
1, spill code
1, select
1, Renumber
2, build
2, coalesce
2, spill cost
2, simplify
2, spill code
2and select
2process is the step of graph coloring register allocation method;
Described graph coloring register allocation method comprises the steps:
11) Renumber: on the basis of data-flow analysis, find all lifetimes in function, and for it distributes unique numbering, since a definite value of a variable, finish one of them lifetime to the last use to this value;
12) build: set up conflict graph G, the node in described conflict graph G is the lifetime, limit represents there is conflict by its two connected lifetimes, can not distribute same register for them;
13) coalesce: judge whether to merge the lifetime, as need to be deleted unnecessary copy-statement by the merging lifetime, return after merging, re-execute step 12), if do not needed to merge, perform step 14);
14) spill cost: the cost of overflowing of calculating each lifetime;
15) simplify: described conflict graph G is simplified, check repeatedly figure G, delete the number of degrees in G and be less than the node that available register is counted k, in the time of deletion, this node is pressed into stack s;
16) spill code: when the degree of all nodes is all more than or equal to k in described conflict graph G, the lifetime of overflowing Least-cost need to be overflowed, delete its node, be pressed into stack s, and be labeled as and overflow, return to execution step 11 after overflowing a lifetime);
17) select: when described conflict graph G is sky, the lifetime in stack s being ejected, is that it distributes register, and insert flooding code for being labeled as the lifetime of overflowing;
Described lo-regs register is the addressable register of short instruction, remaining is described hi-regs register, the described zone bit whether standard of set is: the lifetime that has category-A instruction to quote is made as to set, the lifetime of only having category-B instruction to quote is made as to not set;
Described category-A instruction is that the final machine instruction generating of an instruction is that long instruction or short instruction depend on the register that it is assigned to;
No matter which register described category-B instruction is assigned to for its register manipulation number, it must generate a long instruction, or must generate a short instruction.
Further, described zone bit is located in the structure that records lifetime information.
Further, spill code in described step 5)
1process comprise the steps:
31) at the described conflict graph G of structure
1preserve a described conflict graph G
1backup conflict graph G
1-backup;
32) each simplify
1when certain lifetime l is overflowed in decision, first judge whether that available free hi-regs register can be used for overflowing, if had, after each assignment of l and before using, insert so move instruction, and record the information that lifetime l spills into hi-regs register; And when each hi-regs register related while overflowing the lifetime, according to described backup conflict graph G
1-backup judges whether register association allly overflows the lifetime and does not conflict with the current lifetime l that will overflow, if there is such register, it can be used for overflowing of l so, if there is no idle hi-regs for overflowing, and spill code so
1use load/store instruction the lifetime to spill into storer.
Beneficial effect of the present invention is: be applicable to have two or more different length instruction, and compared with the set of short instruction accessible registers, be wherein compared with the instruction set of the subset of the set of long instruction accessible registers, the present invention can improve the instruction density of generating code, and simple and practical, reliability is strong, and it is short instruction that the less cost of finally take makes the final machine instruction generating of all category-A instructions.
Accompanying drawing explanation
Fig. 1 is the basic flow sheet of graph coloring register allocation method;
Fig. 2 is specific embodiment of the invention process flow diagram;
Fig. 3 is mark lifetime type process flow diagram;
Fig. 4 is spill code
1process flow diagram;
Fig. 5 is the partial graph of the conflict graph of backup.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described further.
The present invention a kind ofly carries out improved register allocation method on graph coloring register apportion design basis.Graph coloring is traditional, is also the register allocation method of commonly using the most, and as shown in Figure 1, the brief description in each stage is as follows for its basic procedure:
Rename (Renumber): before this stage, intermediate code can be quoted " virtual register " that number is unlimited.This stage, on the basis of data-flow analysis, is found all lifetimes in function, and distributes unique numbering for it.Lifetime, since a definite value of a variable, finishes to the last use to this value.
Structure conflict graph (Build): this stage is set up " conflict graph G ", and the node in G is the lifetime, limit represents there is conflict by its two connected lifetimes, they are simultaneously active certain instruction place, therefore can not distribute same register for them.
Merge the lifetime (Coalesce): this stage is deleted unnecessary copy-statement by merging the lifetime.The merging lifetime has changed conflict graph, therefore need to re-execute " Build " process after merging.
Overflow cost analysis (Spill cost): this stage is for calculating the cost of overflowing of each lifetime.
Simplify conflict graph (Simplify): in this stage, conflict graph G is simplified, check repeatedly figure G, delete the number of degrees in G and be less than the node that available register is counted k, in the time of deletion, this node is pressed into stack s.
Insert flooding code (Spill code): when the degree of all nodes is all more than or equal to k in figure G, " Simplify " process cannot continue.Now, the lifetime of overflowing Least-cost need to be overflowed, delete its node, be pressed into stack s, and be labeled as and overflow.After overflowing a lifetime, need to restart execution graph colouring algorithm from " rename " stage.
Painted (Select): figure G finally can be reduced to an empty graph, now ejects the lifetime in stack s, for it distributes register, and inserts flooding code for being labeled as the lifetime of overflowing.
First register is classified, wherein the addressable register of most of short instructions is called lo-regs, and remaining register is called hi-regs.Then for each lifetime increases a zone bit, whether mark it once quoted by category-A instruction, the lifetime of only having category-B instruction to quote is called " category-B lifetime "; And be called to " category-A lifetime " lifetime that has category-A instruction to quote, and the instruction stream by scanning whole function arranges this mark for each lifetime.
Then carry out two graph coloring processes, for the category-A lifetime is distributed lo-regs, for the category-B lifetime is distributed hi-regs; If lo-regs, hi-regs be enough category-A lifetimes, the use of category-B lifetime respectively, or two graph coloring process registers are all not enough, all need to overflow the lifetime, and these two graph coloring processes are independently carried out so.If enough category-A lifetimes of lo-regs distribute and be available free, but the inadequate category-B lifetime distribution of hi-regs is distributed to the category-B lifetime by register idle in lo-regs so together with hi-regs register.Otherwise lo-regs is not enough if hi-regs is available free, while generating flooding code so in lo-regs assigning process, preferentially the lifetime is spilt into idle hi-regs, in the time can overflowing without hi-regs register, just spill into storer.
As shown in Figure 2, concrete steps are as follows for the specific implementation flow process of this method:
One, lifetime mark.All lifetimes in this phase lookup function; And by scanning all instructions of current function, the type of each lifetime is carried out to mark.
Two, Renumber
1, build
1, coalesce
1, spill cost
1, and simplify
1.Front 5 stages in this step execution graph colouring algorithm flow process, for all category-As lifetime is distributed lo-regs register.This step will obtain not carrying out the conflict graph G of any overflow operation after carrying out and finishing
1.
Three, computation-free lo-regs register number.The lo-regs register of this step computation-free is counted m, if G
1non-NULL, m is 0 so; Otherwise, if G
1for empty graph, we carry out select so
1process, and according to the lo-regs register number of the register allocative decision computation-free generating, and record idle register information.
Four, Renumber
2, build
2, coalesce
2, spill cost
2, simplify
2, spill code
2and select
2.This step is a complete traditional graph coloring register assigning process.We use this process for category-B lifetime distribution hi-regs register and m idle lo-regs register.And according to the hi-regs register quantity n of the allocative decision computation-free generating, and record idle register information.
Five, spill code
1and select
1.If G
1for sky, select so
1in step 3, carry out, whole algorithm finishes; Otherwise, repeat spill code
1, Renumber
1, build
1, coalesce
1, spill cost
1, simplify
1process, until G
1for sky, select then
1for the category-A lifetime generates register allocative decision.The special character of this step is, if n>0 is carrying out insertion spill code so
1time, we preferentially spill into the lifetime idle hi-regs register, only have when available without hi-regs register, just will the lifetime spill into storer.The code that is spilt into idle hi-regs register the lifetime that the advantage of doing is like this to use move instruction to generate, its execution speed generally will spill into the lifetime code of storer faster than what use load/store to carry out to generate.
In addition, shuffling instruction set provides special short instruction---move conventionally, and it is a short instruction, but can all registers of addressing.Now, the code that is spilt into idle hi-regs register the lifetime that uses move instruction to generate compare spill into storer will be more efficient (used short instruction to overflow, rather than common long instruction).
This method only need to be carried out a small amount of modification on traditional graph coloring register allocation method, can make full use of the feature of shuffling instruction set, the code that generating code density is higher, have simple and practical, the feature that reliability is strong.
Below in conjunction with instantiation, be described in more details:
First, in recording the structure of lifetime information, increase a zone bit flag_short, if this zone bit set illustrate that this lifetime is a category-A lifetime, otherwise it is a category-B lifetime.After " lifetime identification " process finishes, increase the process of " mark lifetime type ", as shown in Figure 3.This process is by scanning successively each instruction in current function, for each lifetime arranges flag_short sign.
Then, need to carry out two graph coloring processes.Select wherein
1for all category-As lifetime is distributed lo-regs register; Select
2for all category-Bs lifetime is distributed hi-regs register and possible idle lo-regs register.And select
2may be at select
1after completing, carry out, also may be at the conflict graph of the simplification for the first time G of select1
1after process, carry out, as shown in Figure 2.This depend on lo-regs whether enough category-A lifetimes distribute, if enough used, select so
1first be finished, remaining so idle lo-regs can offer select
2stage distributes; Otherwise, select
1carrying out simplify for the first time
1after process, carry out whole select
2flow process, if select like this
2the hi-regs that process is available free, they can be for select
1insertion spill code
1stage.In a word, we have used select
1, select
2two graph coloring processes, wherein select
1for the lifetime that all flag_short are true is distributed lo-regs register; Select
2for the lifetime that all flag_short are false is distributed hi-regs register and possible idle lo-regs register.In these two graph coloring processes, the present invention only need to increase the judgement of a sign of the flag_short to the lifetime in traditional graph coloring algorithm, makes select
1, select
2process respectively the lifetime that flag_short is true, false, and simply reorganize select
1, select
2execution flow process.
Finally, the present invention can also revise the overflow process insertion spill code of traditional graph coloring algorithm
1, its flow process as shown in Figure 4.First, carrying out structure conflict graph G
1during process, need to preserve the conflict graph G of a backup
1-backup; Then at each conflict graph G that simplifies
1when certain lifetime l is overflowed in decision, first judge whether that available free hi-regs can be used for overflowing, if had, after each assignment of l and before using, insert so move instruction, and record the information that lifetime l spills into hi-regs.It should be noted that as each hi-regs relatedly while overflowing the lifetime, and do not mean that do not have hi-regs to can be used for overflowing; At this moment, need to be according to G
1-backup has judged whether certain register, and its association all are overflowed the lifetime and do not conflicted with the current lifetime l that will overflow, if there is such register, it can be used for overflowing of l so.If there is no idle hi-regs for overflowing, so spill code
1carry out the process same with traditional graph coloring algorithm, use load/store instruction the lifetime to spill into storer.
Be below an example that spills into register, given first is at structure conflict graph G
1execution finishes the G of rear backup
1-backup, (for the purpose of simplifying the description, in schematic diagram, only include 4 lifetimes, can think the sub-fraction of conflict graph) as shown below:
Suppose to have two idle hi-regs register R1, R2 can be used for overflowing, and need to overflow the lifetime 3 now, and overflow operation before to the service condition of hi-regs as following table:
| Hi-regs register | The lifetime of having overflowed |
| R1 | 1 |
| R2 | 2 |
Table
hi-regs register spilling situation record
As shown in process flow diagram 4, first obtain the hi-regs register R1 that first can be used for overflowing, and known according to upper table, the lifetime 1 has spilt into R1, and currently will overflow the lifetime 3, according to the conflict graph G of backup
1-backup, there is conflict the known lifetime 1,3, therefore R1 can not be for overflowing the lifetime 3.Next, obtain second hi-regs register R2 that can be used for overflowing, according to G
1-backup is known, lifetime 2,3 is without conflict, illustrate in active time period lifetime 3, lifetime 2 has not re-used, therefore the lifetime 3 can be spilt into R2, this information is inserted to table 1, and in the place that need to use the lifetime 2, insert move instruction and be worth from R2 and copy corresponding lo-regs register to, after use finishes, insert move instruction and be worth from corresponding lo-regs register and copy R2 to.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, without departing from the inventive concept of the premise; can also make some improvements and modifications, these improvements and modifications also should be considered as in protection domain of the present invention.
Claims (1)
1. for a register allocation method for mixed length instructions collection, it is characterized in that, comprise the steps:
1) search all life cycles in function, by zone bit is set, whether set judges that establishing the lifetime is category-A lifetime or category-B lifetime;
2) Renumber of the painted register allocation method of execution graph
1, build
1, coalesce
1, spill cost
1, and simplify
1five processes, for all category-As lifetime is distributed lo-regs register, the conflict graph G that obtains not carrying out any overflow operation
1;
3) computation-free lo-regs register is counted m, if described conflict graph G
1non-NULL, to count m be 0 to idle lo-regs register, if described conflict graph G
1for empty graph, the select of the painted register allocation method of execution graph
1process, and count m according to the lo-regs register of the register allocative decision computation-free generating, and record idle register information;
4) Renumber of the painted register allocation method of execution graph
2, build
2, coalesce
2, spill cost
2, simplify
2, spill code
2and select
2process, for the category-B lifetime is distributed hi-regs register and m idle lo-regs register, and according to the hi-regs register quantity n of the allocative decision computation-free generating, and record idle register information;
5) the spill code of the painted register allocation method of execution graph
1and select
1process, if select
1process step 3) carry out finish in steps, if do not had, repeat spill code
1, Renumber
1, build
1, coalesce
1, spill cost
1, simplify
1process is until described conflict graph G
1for sky, then carry out select
1process is the category-A lifetime to generate register allocative decision;
Renumber
1, build
1, coalesce
1, spill cost
1, simplify
1, spill code
1, select
1, Renumber
2, build
2, coalesce
2, spill cost
2, simplify
2, spill code
2and select
2process is the step of graph coloring register allocation method;
Described graph coloring register allocation method comprises the steps:
11) Renumber: on the basis of data-flow analysis, find all lifetimes in function, and for it distributes unique numbering, since a definite value of a variable, finish one of them lifetime to the last use to this value;
12) build: set up conflict graph G, the node in described conflict graph G is the lifetime, limit represents there is conflict by its two connected lifetimes, can not distribute same register for them;
13) coalesce: judge whether to merge the lifetime, as need to be deleted unnecessary copy-statement by the merging lifetime, return after merging, re-execute step 12), if do not needed to merge, perform step 14);
14) spill cost: the cost of overflowing of calculating each lifetime;
15) simplify: described conflict graph G is simplified, check repeatedly figure G, delete the number of degrees in G and be less than the node that available register is counted k, in the time of deletion, this node is pressed into stack s;
16) spill code: when the degree of all nodes is all more than or equal to k in described conflict graph G, the lifetime of overflowing Least-cost need to be overflowed, delete its node, be pressed into stack s, and be labeled as and overflow, return to execution step 11 after overflowing a lifetime);
17) select: when described conflict graph G is sky, the lifetime in stack s being ejected, is that it distributes register, and insert flooding code for being labeled as the lifetime of overflowing;
Described lo-regs register is the addressable register of short instruction, remaining is described hi-regs register, the described zone bit whether standard of set is: the lifetime that has category-A instruction to quote is made as to set, the lifetime of only having category-B instruction to quote is made as to not set;
Described category-A instruction is that the final machine instruction generating of an instruction is that long instruction or short instruction depend on the register that it is assigned to;
No matter which register described category-B instruction is assigned to for its register manipulation number, it must generate a long instruction, or must generate a short instruction;
Described short instruction is a subset of long instruction in function.
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| CN102831005B (en) * | 2012-07-13 | 2015-10-28 | 天津国芯科技有限公司 | The Compilation Method of distributing for C*core processor register and compiler |
| CN104731555A (en) * | 2013-12-23 | 2015-06-24 | 中兴通讯股份有限公司 | Method and device for avoiding conflict among registers |
| CN105739947A (en) * | 2014-12-10 | 2016-07-06 | 中兴通讯股份有限公司 | Register conflict detection method and apparatus |
| CN105912304B (en) * | 2016-03-31 | 2018-04-20 | 中国人民解放军国防科学技术大学 | Vectorial vliw architecture graph coloring register is grouped distribution method |
| CN111435309A (en) * | 2019-01-11 | 2020-07-21 | 中标软件有限公司 | Register allocation optimization implementation method |
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|---|---|---|---|---|
| US4571678A (en) * | 1982-11-05 | 1986-02-18 | International Business Machines Corporation | Register allocation and spilling via graph coloring |
| CN1973263A (en) * | 2004-06-30 | 2007-05-30 | 英特尔公司 | Bank assignment for partitioned register banks |
| CN101710291A (en) * | 2009-11-27 | 2010-05-19 | 中国科学院声学研究所 | Register allocation method for optimizing stack space |
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2011
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4571678A (en) * | 1982-11-05 | 1986-02-18 | International Business Machines Corporation | Register allocation and spilling via graph coloring |
| CN1973263A (en) * | 2004-06-30 | 2007-05-30 | 英特尔公司 | Bank assignment for partitioned register banks |
| CN101710291A (en) * | 2009-11-27 | 2010-05-19 | 中国科学院声学研究所 | Register allocation method for optimizing stack space |
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