CN102355245A - Signal regulating circuit and signal regulating method - Google Patents
Signal regulating circuit and signal regulating method Download PDFInfo
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- CN102355245A CN102355245A CN2011101670308A CN201110167030A CN102355245A CN 102355245 A CN102355245 A CN 102355245A CN 2011101670308 A CN2011101670308 A CN 2011101670308A CN 201110167030 A CN201110167030 A CN 201110167030A CN 102355245 A CN102355245 A CN 102355245A
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Abstract
The invention relates to a signal regulating circuit which is used for automatically regulating the rising and falling time of an output signal and comprises a first data input end, a second data input end, a data driver, a first output end, a second output end, a time detector, an amplifier, a first comparator, a second comparator and a digital encoder, wherein the data driver is connected with the first data input end and the second data input end, the fist output end is connected with the data driver, the second output end is connected with the data driver, the time detector is connected with the first output end and the second output end, the amplifier is connected with the time detector, the first comparator is connected with the amplifier, the second comparator is connected with the amplifier, and the data encoder is connected with the first comparator and the second comparator. The invention also provides a signal regulating method. The structure and the regulating method provided by the invention are simple.
Description
Technical field
The present invention relates to a kind of regulating circuit and method, refer to a kind of simple in structure and circuit for signal conditioning and the method that can regulate output signal rise and fall time automatically especially.
Background technology
The rise and fall time of signal refers to signal and is carved into from zero the time and reaches steady-state value first or dropped to for zero constantly time from steady-state value.
In the prior art; The rise and fall time of input signal is uncertain often; Rise and fall time with input signal is controlled in the time range of an expectation all the time if desired; Usually need manual operation to regulate the rise and fall time of input signal; Operation is complicated and time cost is longer, therefore is necessary to provide a kind of circuit for signal conditioning and the method that can regulate output signal rise and fall time automatically.
Summary of the invention
In view of above content, be necessary to provide a kind of simple in structure and circuit for signal conditioning and the method that can regulate output signal rise and fall time automatically.
A kind of circuit for signal conditioning; Be used for regulating automatically the rise and fall time of output signal, said circuit for signal conditioning comprises one first data input pin; One second data input pin; One data driver that links to each other with said first data input pin and said second data input pin; One first output that links to each other with said data driver; One second output that links to each other with said data driver; One time detector that links to each other with said first output and said second output; One amplifier that links to each other with said time detector; One first comparator that links to each other with said amplifier; One second comparator that links to each other with said amplifier and a digital encoder that links to each other with said first comparator and said second comparator.
A kind of Signal Regulation method is used for regulating automatically the rise and fall time of exporting signal, and it may further comprise the steps:
The expected range value of typing output signal rise and fall time, and the higher limit of expectation as required is first voltage, and the lower limit of expectation is second voltage;
One first data input pin and one second data input pin are imported a pair of differential data signals to a data driver;
Said data driver is driven into the differential data signals of said first data input pin and said second data input pin input respectively on one first output and one second output, and as the input differential signal of a time detector;
Said time detector detects the rise and fall time of said first output and said second output output signal, and is converted into a voltage signal;
The voltage signal that one amplifier is exported said time detector amplifies the back and compares through one first comparator and said first voltage, compares through one second comparator and said second voltage;
One digital encoder is encoded the back corresponding conditioning signal of output to said data driver with the comparative result of said first comparator and the output of said second comparator; And
Voltage after said data driver amplifies said amplifier according to the conditioning signal that receives is adjusted to less than said first voltage and greater than said second voltage, and the rise and fall time of said first output and said second output output signal gets into expected range.
Relative prior art; Circuit for signal conditioning of the present invention and method can be regulated the rise and fall time of output signal automatically; When the expected range of rise and fall time after outside typing; The rise and fall time that meeting of the present invention will be exported signal automatically transfers in the expected range, and circuit structure and control method are simple.
Description of drawings
Fig. 1 is the circuit block diagram of circuit for signal conditioning of the present invention.
Fig. 2 is the circuit diagram of circuit for signal conditioning better embodiment of the present invention.
Fig. 3 is the flow chart of Signal Regulation method better embodiment of the present invention.
Fig. 4 is the flow chart of Signal Regulation method better embodiment desired scope of the present invention typing.
Embodiment
See also Fig. 1, circuit for signal conditioning of the present invention comprises one first data input pin; One second data input pin; One data driver that links to each other with this first data input pin and this second data input pin; One first output that links to each other with this data driver; One second output that links to each other with this data driver; One time detector that links to each other with this first output and this second output; One amplifier that links to each other with this time detector; One first comparator that links to each other with this amplifier; One second comparator that links to each other with this amplifier and a digital encoder that links to each other with this first comparator and this second comparator.
See also Fig. 2; Fig. 2 is the circuit diagram of circuit for signal conditioning better embodiment of the present invention, and it comprises an ON-OFF control circuit; One first differential signal input IN+; One second differential signal input IN-; One time detector T1; One amplifier OPM1; One first comparator C MP1; One second comparator C MP2; One digital encoder CODE; One data driver DRIVE; One first data input pin DATA+; One second data input pin DATA-; One first output end vo ut+; One second output end vo ut-; One first switch Φ 1; One second switch Φ 2; One the 3rd switch Φ 3; One the 4th switch Φ 4; One first capacitor C 1 and one second capacitor C 2.
This ON-OFF control circuit comprises one or door OR and a not gate INV; Should or the door OR two inputs link to each other with this first switch Φ 1 and this second switch Φ 2 respectively; Should or the door OR output link to each other with the input of this not gate INV, the output of this not gate INV links to each other with the 3rd switch Φ 3.This first differential signal input IN+ and this second differential signal input IN-are used to import the differential voltage signal of pair of standard; This time detector T1 is used for converting the rise and fall time of the differential voltage signal of the differential voltage signal of this first differential signal input IN+ and this second differential signal input IN-input or this first output end vo ut+ and this second output end vo ut-output into a voltage signal Vrf, and the proportional relation of magnitude of voltage of the value of rise and fall time and voltage signal Vrf; This amplifier OPM1 is used for voltage signal Vrf is enlarged into a voltage signal Vb, so that this first comparator C MP1 and this second comparator C MP2 are more prone to carry out voltage ratio; This first comparator C MP1 is used for the relatively size between this voltage signal Vb and one first voltage V1, and exports a comparative result Vout1; This second comparator C MP2 is used for the relatively size between this voltage signal Vb and one second voltage V2, and exports a comparative result Vout2; This digital encoder CODE is used for compared result Vout1, Vout2 encodes, to export three conditioning signal A0, A1, A2; This first data input pin DATA+ and this second data input pin DATA-are used to import a pair of differential data signals; This data driver DRIVE is used for a pair of differential data signals of the first data input pin DATA+ and second data input pin DATA-input is converted into the differential signal of a pair of simulation and is driven into this first output end vo ut+ and this second output end vo ut-respectively, and regulates the rise and fall time that this first output end vo ut+ and this second output end vo ut-upward export signal according to three conditioning signal A0, A1, A2 receiving.The 3rd switch Φ 3 is the switch of this data driver DRIVE, and this data driver DRIVE only works during for high level at the 3rd switch Φ 3.This first voltage V1 and this second voltage V2 are respectively the higher limit and the lower limit of expectation rise and fall time.
The physical circuit annexation of circuit for signal conditioning better embodiment of the present invention is following: this first differential signal input IN+ links to each other with the normal phase input end of this time detector T1 by the 4th switch Φ 4; This second differential signal input IN- links to each other with the inverting input of this time detector T1 by the 4th switch Φ 4; The output output voltage signal Vrf of this time detector T1 is to the input of this amplifier OPM1; The output output voltage signal Vb of this amplifier OPM1; The output of this amplifier OPM1 links to each other the other end ground connection of this first capacitor C 1 by this first switch Φ 1 with the normal phase input end of this first comparator C MP1 and an end of this first capacitor C 1.The output of this amplifier OPM1 links to each other with the inverting input of this first comparator C MP1 through the 3rd switch Φ 3; The output of this amplifier OPM1 links to each other with the inverting input of this second comparator C MP2 and an end of this second capacitor C 2 through this second switch Φ 2; The other end ground connection of this second capacitor C 2, the output of this amplifier OPM1 links to each other with the normal phase input end of this second comparator C MP2 through the 3rd switch Φ 3.The output of this first comparator C MP1 links to each other with two inputs of this digital encoder CODE respectively with the output of this second comparator C MP2; The output output comparative result Vout1 of this first comparator C MP1 is to the input in1 of this digital encoder CODE, and the output output comparative result Vout2 of this second comparator C MP2 is to the input in2 of this digital encoder CODE.The output out0 of this digital encoder CODE, out1, out2 link to each other with the control end of this data driver DRIVE, and export three conditioning signal A0, A1, the A2 control end to this data driver DRIVE respectively.This first data input pin DATA+ links to each other with the normal phase input end of this data driver DRIVE, and this second data input pin DATA-links to each other with the inverting input of this data driver DRIVE.The output of this data driver DRIVE links to each other with the normal phase input end of this time detector T1 through this first output end vo ut+, and links to each other with the inverting input of this time detector T1 through this second output end vo ut-.
The principle Analysis of circuit for signal conditioning of the present invention is following:
First process: the typing of expected range
The level of the 3rd switch Φ 3 must be always low level; To guarantee that data driver DRIVE closes all the time; The inverting input that guarantees voltage signal Vb and this first comparator C MP1 simultaneously breaks off all the time, and the normal phase input end of this voltage signal Vb and this second comparator C MP2 breaks off all the time.Begin to carry out the typing of expected range now, at first, open this first switch Φ 1, be about to this first switch Φ 1 and be changed to high level, carry out the upper limit typing of expected range, i.e. the maximum of typing rise and fall time.Since the 4th switch Φ 4 be this first switch Φ 1 and this second switch Φ's 2 or; So the time the 4th switch Φ 4 be high level; The differential voltage signal of this first differential signal input IN+ and this second differential signal input IN-input pair of standard is to the input of this time detector T1, and its rise and fall time is the higher limit of expectation typing.This moment, this time detector T1 can detect the rise and fall time of the differential voltage signal of the standard of input; And generate a magnitude of voltage Vrf1 directly proportional with it; This magnitude of voltage Vrf1 carries out a certain proportion of amplification back output one voltage Vb1 through this amplifier OPM1; This voltage Vb1 charges to this first capacitor C 1; V1 equals this voltage Vb1 up to this first voltage; So far, the typing of the expected range upper limit finishes; Be changed to low level with this first switch Φ 1 this moment; Then this second switch Φ 2 is changed to high level; Carry out the typing of expected range lower limit; Since the 4th switch Φ 4 be this first switch Φ 1 and this second switch Φ's 2 or; So the time the 4th switch Φ 4 be high level; This first differential signal input IN+ and this second differential signal input IN-input another to the differential voltage signal of standard input to this time detector T1, its rise and fall time is the lower limit of expectation typing.This moment, this time detector T1 can detect the rise and fall time of the differential voltage signal of the standard of input; And generate a magnitude of voltage Vrf2 directly proportional with it; This magnitude of voltage Vrf2 carries out a certain proportion of amplification back output one voltage Vb2 through this amplifier OPM1; This voltage Vb2 charges to this second capacitor C 2; V2 equals this voltage Vb2 up to this second voltage; So far, the typing of expected range lower limit finishes; Be changed to low level with this second switch Φ 2 this moment.So far, first process finishes.
Second process: the automatic adjusting of output signal rise and fall time
This first switch Φ 1 must be always low level with the level of this second switch Φ 2, guaranteeing the constant of this first voltage V1 and this second voltage V2 level, and shields this first differential signal input IN+ and this second differential signal input IN-.At first; Open the 3rd switch Φ 3; Be about to the 3rd switch Φ 3 and be changed to high level; This moment, this data driver DRIVE began the differential data signals of this first data input pin DATA+ and this second data input pin DATA- input is driven on this first output end vo ut+ and this second output end vo ut-; The input differential signal of this time detector T1 is the signal that this first output end vo ut+ and this second output end vo ut- go up output simultaneously; What promptly detected this moment is the rise and fall time that this first output end vo ut+ and this second output end vo ut- go up signal; And be converted into an output voltage V rf3; Be enlarged into a voltage Vb3 behind this amplifier of this voltage Vrf3 process OPM1; This voltage Vb3 while is as the input of this first comparator C MP1 and this second comparator C MP2; And compare with this first voltage V1 and this second voltage V2; And if only if this voltage Vb3 is during less than this first voltage V1 and greater than this second voltage V2; Comparative result Vout1, Vout2 are high level simultaneously at this moment; The rise and fall time of this first output end vo ut+ and this second output end vo ut- output signal has just got into expected range; Otherwise; This digital encoder CODE and this data driver DRIVE will constantly adjust according to comparative result Vout1, Vout2; Up to making comparative result Vout1, Vout2 be high level simultaneously, promptly up to the rise and fall time of this first output end vo ut+ and this second output end vo ut- output signal is transferred in the expected range.
See also Fig. 3, Signal Regulation method better embodiment of the present invention may further comprise the steps:
Step 1, the expected range value of signal rise and fall time is exported in typing as required, and promptly Qi Wang higher limit is the first voltage V1, and the lower limit of expectation is the second voltage V2.
Step 2, the first data input pin DATA+ and the second data input pin DATA-import a pair of differential data signals to data driver DRIVE.
Step 3, data driver DRIVE is driven into the differential data signals of the first data input pin DATA+ and second data input pin DATA-input on the first output end vo ut+ and the second output end vo ut-, and as the input differential signal of time detector T1.
Step 4, time detector T1 detects the rise and fall time of the first output end vo ut+ and second output end vo ut-output signal, and is converted into output voltage V rf.
Step 5, amplifier OPM1 amplifies the back with the output voltage V rf of time detector T1 and compares through the first comparator C MP1 and the first voltage V1, compares through the second comparator C MP2 and the second voltage V2.
Step 6, digital encoder CODE encodes the back corresponding conditioning signal of output to data driver DRIVE with comparative result Vout1, the Vout2 of the first comparator C MP1 and second comparator C MP2 output.
Step 7; Voltage after data driver DRIVE amplifies amplifier OPM1 according to the conditioning signal that receives is adjusted to less than the first voltage V1 and greater than the second voltage V2; At this moment, the rise and fall time of the first output end vo ut+ and second output end vo ut-output signal gets into expected range.
See also Fig. 4, may further comprise the steps in the typing of the step 1 desired scope of Signal Regulation method better embodiment of the present invention:
Step 1; Carry out the upper limit typing of expected range; It is the maximum of typing rise and fall time; The differential voltage signal of the first differential signal input IN+ and second differential signal input IN-input pair of standard is to the input of time detector T1, and its rise and fall time is the higher limit of expectation typing.
Step 2; Time detector T1 detects the rise and fall time of the differential voltage signal of the standard of input; Generate a magnitude of voltage Vrf1 proportional with it; This magnitude of voltage Vrf1 carries out a certain proportion of amplification back output one voltage Vb1 through amplifier OPM1; This voltage Vb1 charges to first capacitor C 1; Equal this voltage Vb1 up to the first voltage V1, so far, the typing of the expected range upper limit finishes.
Step 3; Carry out the typing of expected range lower limit; It is the minimum value of typing rise and fall time; The first differential signal input IN+ and second differential signal input IN-input another to the differential voltage signal of standard input to time detector T1, its rise and fall time is the lower limit of expectation typing.
Step 4; Time detector T1 detects the rise and fall time of the differential voltage signal of the standard of input; Generate a magnitude of voltage Vrf2 proportional with it; This magnitude of voltage Vrf2 carries out a certain proportion of amplification back output one voltage Vb2 through amplifier OPM1; This voltage Vb2 charges to second capacitor C 2; Equal this voltage Vb2 up to the second voltage V2, so far, the typing of expected range lower limit finishes.
Circuit for signal conditioning of the present invention and method can be regulated the rise and fall time of output signal automatically; When the expected range of rise and fall time after outside typing; The rise and fall time that meeting of the present invention will be exported signal automatically transfers in the expected range, and circuit structure and control method are simple.
Claims (10)
1. circuit for signal conditioning; Be used for regulating automatically the rise and fall time of output signal, it is characterized in that: said circuit for signal conditioning comprises one first data input pin; One second data input pin; One data driver that links to each other with said first data input pin and said second data input pin; One first output that links to each other with said data driver; One second output that links to each other with said data driver; One time detector that links to each other with said first output and said second output; One amplifier that links to each other with said time detector; One first comparator that links to each other with said amplifier; One second comparator that links to each other with said amplifier and a digital encoder that links to each other with said first comparator and said second comparator.
2. circuit for signal conditioning as claimed in claim 1; It is characterized in that: said first data input pin and said second data input pin are imported a pair of differential data signals to said data driver; Said data driver is converted to a pair of analog difference signal with the differential data signals that receives and exports said time detector to by said first output and said second output; Said time detector inputs to said amplifier with the proportional voltage signal of value that the rise and fall time of the differential signal that receives is converted to a magnitude of voltage and rise and fall time; After amplifying said voltage signal, said amplifier relatively exports comparative result to said digital encoder in the back by said first comparator and said second comparator with the higher limit and the lower limit of expectation rise and fall time respectively; Said digital encoder is encoded the back corresponding conditioning signal of output to said data driver with comparative result, and said data driver is adjusted to the rise and fall time of said first output and said second output output signal according to the conditioning signal that receives the scope of expectation rise and fall time.
3. circuit for signal conditioning as claimed in claim 2; It is characterized in that: said circuit for signal conditioning also comprises an ON-OFF control circuit; One first differential signal input; One second differential signal input; One first switch; One second switch; One the 3rd switch; One the 4th switch; One first electric capacity and one second electric capacity; Said first differential signal input and the said second differential signal input are used to import the differential voltage signal of pair of standard, and said ON-OFF control circuit is used to control said first switch; Said second switch; The unlatching of said the 3rd switch and said the 4th switch is with closed.
4. circuit for signal conditioning as claimed in claim 3; It is characterized in that: said ON-OFF control circuit comprise one or the door and a not gate; Two inputs said or door link to each other with said first switch and said second switch respectively; Output said or door links to each other with the input of said not gate; The output of said not gate links to each other with said the 3rd switch; Said the 3rd switch is the switch of said data driver, and said data driver is worked during for high level at said the 3rd switch.
5. circuit for signal conditioning as claimed in claim 3; It is characterized in that: the said first differential signal input links to each other with a normal phase input end of said time detector by said the 4th switch; The said second differential signal input links to each other with an inverting input of said time detector by said the 4th switch; One output of said time detector links to each other with an input of said amplifier; One output of said amplifier links to each other with a normal phase input end of said first comparator and an end of said first electric capacity by said first switch; The other end ground connection of said first electric capacity; The output of said amplifier also links to each other with an inverting input of said first comparator by said the 3rd switch; The output of said amplifier links to each other with an inverting input of said second comparator and an end of said second electric capacity by said second switch; The other end ground connection of said second electric capacity, the output of said amplifier also link to each other with a normal phase input end of said second comparator by said the 3rd switch.
6. circuit for signal conditioning as claimed in claim 5; It is characterized in that: an output of said first comparator links to each other with two inputs of said digital encoder respectively with an output of said second comparator, and the output of said first comparator links to each other with two inputs of said digital encoder respectively with the output of said second comparator.
7. circuit for signal conditioning as claimed in claim 6; It is characterized in that: the output of said digital encoder links to each other with the control end of said data driver; Said digital encoder is encoded the comparative result of said first comparator and the output of said second comparator, and output is used to regulate the control end of conditioning signal to the said data driver of exporting the signal rise and fall time.
8. circuit for signal conditioning as claimed in claim 7; It is characterized in that: said first data input pin links to each other with a normal phase input end of said data driver; Said second data input pin links to each other with an inverting input of said data driver; The output of said data driver links to each other with the normal phase input end of said time detector through said first output, and links to each other with the inverting input of said time detector through said second output.
9. a Signal Regulation method is used for regulating automatically the rise and fall time of exporting signal, and it may further comprise the steps:
The expected range value of typing output signal rise and fall time, and the higher limit of expectation as required is first voltage, and the lower limit of expectation is second voltage;
One first data input pin and one second data input pin are imported a pair of differential data signals to a data driver;
Said data driver is driven into the differential data signals of said first data input pin and said second data input pin input respectively on one first output and one second output, and as the input differential signal of a time detector;
Said time detector detects the rise and fall time of said first output and said second output output signal, and is converted into a voltage signal;
The voltage signal that one amplifier is exported said time detector amplifies the back and compares through one first comparator and said first voltage, compares through one second comparator and said second voltage;
One digital encoder is encoded the back corresponding conditioning signal of output to said data driver with the comparative result of said first comparator and the output of said second comparator; And
Voltage after said data driver amplifies said amplifier according to the conditioning signal that receives is adjusted to less than said first voltage and greater than said second voltage, and the rise and fall time of said first output and said second output output signal gets into expected range.
10. Signal Regulation method as claimed in claim 9 is characterized in that: the expected range value of typing output signal rise and fall time may further comprise the steps as required:
Carry out the upper limit typing of expected range, the input of differential voltage signal to the said time detector of one first differential signal input and one second differential signal input input pair of standard, its rise and fall time is the higher limit of expectation typing;
Said time detector detects the rise and fall time of the differential voltage signal of the standard of input; Generate a magnitude of voltage Vrf1 proportional with it; Said magnitude of voltage Vrf1 carries out a certain proportion of amplification back output one voltage Vb1 through said amplifier; Said voltage Vb1 charges to one first electric capacity; Equal said voltage Vb1 up to said first voltage; So far, the typing of the expected range upper limit finishes;
Carry out the typing of expected range lower limit, another input of said first differential signal input and the input of the said second differential signal input to differential voltage signal to the said time detector of standard, its rise and fall time is the lower limit of expectation typing;
Said time detector detects the rise and fall time of the differential voltage signal of the standard of input; Generate a magnitude of voltage Vrf2 proportional with it; Said magnitude of voltage Vrf2 carries out a certain proportion of amplification back output one voltage Vb2 through said amplifier; Said voltage Vb2 charges to one second electric capacity; Equal said voltage Vb2 up to said second voltage; So far, the typing of expected range lower limit finishes.
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| CN201110167030.8A CN102355245B (en) | 2011-06-21 | 2011-06-21 | Signal regulating circuit and signal regulating method |
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| CN201110167030.8A CN102355245B (en) | 2011-06-21 | 2011-06-21 | Signal regulating circuit and signal regulating method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102624394A (en) * | 2012-04-01 | 2012-08-01 | 四川和芯微电子股份有限公司 | Data driving circuit and system |
| CN106059536A (en) * | 2016-07-14 | 2016-10-26 | 深圳市鼎阳科技有限公司 | Square wave signal generator |
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| JPH03235385A (en) * | 1990-02-13 | 1991-10-21 | Sumitomo Electric Ind Ltd | Driver circuit of laser diode |
| US6362672B1 (en) * | 2001-02-08 | 2002-03-26 | Intel Corporation | Apparatus and method for automatic matching of signaling rise time to fall time |
| CN102005169A (en) * | 2009-08-28 | 2011-04-06 | 奇景光电股份有限公司 | Source driver |
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| US4216393A (en) * | 1978-09-25 | 1980-08-05 | Rca Corporation | Drive circuit for controlling current output rise and fall times |
| JPH03235385A (en) * | 1990-02-13 | 1991-10-21 | Sumitomo Electric Ind Ltd | Driver circuit of laser diode |
| US6362672B1 (en) * | 2001-02-08 | 2002-03-26 | Intel Corporation | Apparatus and method for automatic matching of signaling rise time to fall time |
| CN102005169A (en) * | 2009-08-28 | 2011-04-06 | 奇景光电股份有限公司 | Source driver |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102624394A (en) * | 2012-04-01 | 2012-08-01 | 四川和芯微电子股份有限公司 | Data driving circuit and system |
| CN102624394B (en) * | 2012-04-01 | 2014-11-19 | 四川和芯微电子股份有限公司 | Data driving circuit and system |
| CN106059536A (en) * | 2016-07-14 | 2016-10-26 | 深圳市鼎阳科技有限公司 | Square wave signal generator |
| CN106059536B (en) * | 2016-07-14 | 2024-03-01 | 深圳市鼎阳科技股份有限公司 | Square wave signal generator |
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| CN102355245B (en) | 2014-03-26 |
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