CN102355239B - Azimuth increment pulse signal adaptation device and processing method - Google Patents
Azimuth increment pulse signal adaptation device and processing method Download PDFInfo
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- CN102355239B CN102355239B CN 201110212799 CN201110212799A CN102355239B CN 102355239 B CN102355239 B CN 102355239B CN 201110212799 CN201110212799 CN 201110212799 CN 201110212799 A CN201110212799 A CN 201110212799A CN 102355239 B CN102355239 B CN 102355239B
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Abstract
The invention relates to the counting and processing of digital pulse signals, in particular to an adaptation device and a method for the input and processing of azimuth increment pulse digital signals of a mechanical scanning radar. The adaptation device and the method for the input and processing of the increment pulse digital signals aim to solve problems in the prior art. 4,096 and 8,192 azimuth increment pulses are processed into the 8,192 azimuth increment pulses, so the workload of a software processing way is reduced. A digital circuit is established to control comparison between the azimuth increment pulse input signal and a true north pulse input signal to detect the type of the azimuth increment pulse input signal, properly regulate the azimuth increment pulse input signal by aclock pulse input signal and process the 4,096 and 8,192 azimuth increment pulses into the 8,192 azimuth increment pulses for output. The device and the method are applied in the fields of a digital pulse technology and processing.
Description
Technical field
The present invention relates to counting and the process field of digital pulse signal, especially a kind of mechanical scanning radar bearing increment pulse signal input and self-reacting device and the method processed.
Background technology
Mechanical scanning radar (or claiming primary radar) scans target in the mode of antenna rotation sweep, calculates the residing orientation of scanning antenna (with respect to position, the positive north) by " bearing increment ".
" bearing increment " is that the antenna with mechanical scanning radar rotates a circle in (360 deg orientation), is quantified as N pulse, and each pulse is a bearing increment.Usually, the bearing increment of primary radar have 4096 and 8192 minute, namely begin to produce a bearing increment from position, the positive north, when returning the positive north to rotating a circle, total number of the bearing increment pulse that produces should be 4096 or 8192.
Before the present invention, secondary radar equipment is when supporting with primary radar, need know in advance that the antenna bearingt increment of the radar of attaching troops to a unit is any, then select corresponding process software to process, this just causes software release's increase, and also in the process of product delivery, there is the possibility of makeing mistakes, to using and managing all and make troubles.
Summary of the invention
Technical problem to be solved by this invention is: for the problem of above-mentioned existence, self-reacting device and the method for a kind of increment digit pulse input signal technology and processing are provided, two kinds of (4096 or 8192) bearing increment burst process are become 8192 bearing increment pulses, reduce software and process loaded down with trivial details workload.
The technical solution used in the present invention is as follows:
A kind of bearing increment pulse signal self-reacting device comprises bearing increment pulse input end ACP_IN, positive northern pulse input end ARP_IN, clock pulse input terminal CLK125 and bearing increment pulse output end ACP_OUT; Bearing increment pulse input end ACP_IN is used for input bearing increment pulse input signal; Positive northern pulse input end ARP_IN is used for inputting positive northern pulse input signal; Clock pulse input terminal CLK125 is used for input clock pulse signals; Bearing increment pulse output end ACP_OUT is used for the output signal after output is regulated, and described bearing increment pulse signal self-reacting device forms by digital circuit.
A kind of bearing increment pulse signal self-reacting device specifically comprises:
Pulse regulation device 2 is used for regulating bearing increment pulse input signal and output;
Described pulse detecting equipment 1 comprises the 3rd counter 4, AND gate circuit 5, the first trigger 6, described bearing increment pulse input signal is by the C end input of the 3rd counter 4, described positive northern pulse input signal is by the CLR end input of the 3rd counter 4, the 3rd counter 4 output signals are by the 9bit of the 3rd counter 4 output bus X_ACP, 12bit output, judge the type of bearing increment pulse input signal and export control signal through AND gate circuit 5, control signal is connected with output device after the Q end output by the first trigger 6 through the C end input of the first trigger 6.
Described pulse detecting equipment 1 also comprises pull down resistor PULLDOWN, is used for when the output of the first trigger 6 is not high level, and the S0 port of output device 7 must keep low level, and can not be in uncertain vacant state.
Described pulse regulation device 2 comprises the second trigger 13, the second counter 12, the 3rd trigger 11, the first counter 10, OR-circuit 9, described bearing increment pulse input signal is by the C end input of the second trigger 13, the Q end of the second counter 13 is connected with the CE end of the second counter, the CEO end of the second counter 12 is connected with the C end of the 3rd trigger 11, the Q end of the 3rd trigger 11 is connected with the CE end of the first counter 10 respectively, OR-circuit 9 one inputs connect, the Q3 end of described the first counter 10 is respectively with the CLR end of feedback signal by the second trigger 13, the CLR end of the second counter 12, the CLR end input of the 3rd trigger 11, the C end of described the first counter, the C end of the second counter is the input clock pulse input signal respectively, described OR-circuit 9 another input input bearing increment pulse input signals, described OR-circuit 9 output signals are by the D0 port input of output device, and the D of described the first trigger 13 holds, the D end of the second trigger 13, the D end of the 3rd trigger 11 connects respectively power Vcc.
Described output device 7 is selectors, and selector S0 end connects the Q end of the first trigger 6, and selector D0 end connects OR-circuit 9 outputs, selector D1 end input bearing increment pulse input signal, and selector ACP_OUT end is output.
A kind of bearing increment pulse signal self-reacting device processing method, by the counting of positive northern pulse input signal control to orientation delta pulse input signal, type in order to detection orientation delta pulse input signal, and suitably regulate the bearing increment pulse input signal by the clock pulse input signal, be a kind of required bearing increment pulse output signals so that output signal is unified.
A kind of bearing increment pulse signal self-reacting device processing method may further comprise the steps:
Step 1: input bearing increment pulse input signal, positive northern pulse input signal, clock pulse input signal;
Step 2, by detection orientation delta pulse input signal types, and the output control signal, when if control signal is high level, then finally export the bearing increment pulse input signal, if when control signal is low level, then final output is by the output signal of pulse regulation device adjusting.
Pulse regulation device 2 comprises the second trigger 13 in the described step 2, the second counter 12, the 3rd trigger 11, the first counter 10, OR-circuit 9, described bearing increment pulse input signal is by the C input input of the second trigger 13, the Q output of the second counter 13 is connected with the CE of the second counter end, the CEO output of the second counter 12 is connected with the C input of the 3rd trigger 11, the Q output of the 3rd trigger 11 is connected with the CE input of the first counter 10 respectively, OR-circuit 9 one inputs connect, the Q3 output of described the first counter 10 is respectively with the CLR end of feedback signal by the second trigger 13, the CLR end of the second counter 12, the CLR end input of the 3rd trigger 11, the C end of described the first counter, the C end of the second counter is the input clock pulse input signal respectively, described input OR-circuit 9 other ends input bearing increment pulse input signal, the output signal of described OR-circuit 9 is inputted by output device, the D end of described the first trigger 13, the D end of the second trigger 13, the D end of the 3rd trigger 11 connects respectively power Vcc.
Described bearing increment pulse input signal is 4096 or 8192, come the counting of control counter execution cycle inner orientation delta pulse number by positive northern pulse input signal, cooperate counter and trigger to the adjusting of delaying time of orientation delta pulse by the clock pulse input signal, then the delta pulse phase "or" original with another road, the unification of bearing increment pulse input signal is 8192 pulses outputs the most at last.
In sum, owing to having adopted technique scheme, the invention has the beneficial effects as follows: when no matter bearing increment with which kind of (for example 4096 or 8192) is inputted, all automatically be processed into 8192 delta pulse outputs with hardware mode, thereby attach troops to a unit when having the radar of different azimuth increment before having avoided, need with different process softwares identify be which kind of bearing increment and processing trouble.
Description of drawings
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is circuit theory diagrams of the present invention.
Embodiment
Disclosed all features in this specification, or the step in disclosed all methods or the process, except mutually exclusive feature and or step, all can make up by any way.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
As shown in Figure 1, this device circuit comprises bearing increment pulse input end, positive northern pulse input end, clock pulse input terminal totally three road inputs and a bearing increment pulse output end; Bearing increment pulse input end ACP_IN is used for input bearing increment pulse input signal; Positive northern pulse input end ARP_IN is with the positive northern pulse input end signal of input; Clock pulse input terminal CLK125 is used for input clock pulse signals, and the clock pulse input signal is by the inner clock signal that produces of FPGA; Bearing increment pulse output end ACP_OUT is used for the output signal after output is regulated.Wherein the bearing increment pulse input signal before being input to this device, passed through synchronously, debounce processing, positive northern pulse input end is introduced positive northern signal and (is guaranteed that the count cycle is from direct north, be zero clearing after maximum 8192 pulses of counter meter foot), namely within a scan period, begin to returning positive when north from direct north, be zero clearing after maximum 8192 pulses of counter meter foot, otherwise can ceaselessly count, will cause not making clear the true number of the umber of pulse of introducing this counting.
Mechanical scanning radar antenna bearingt delta pulse input signal is divided into four the tunnel after introducing from the C end of the 3rd counter 4, is connected respectively to the C end of the 3rd counter 4, the D1 end of selector 7, another input of OR-circuit 9 and the C end of the second trigger 13.The C end that is connected to the 3rd counter 4 is that to count the pulse number of telling input with this be 4096 or 8192.
When bearing increment pulse input end ACP_IN input signal types is 8192, the output bus X_ACP[15:0 of the 3rd counter 4] (comprise 16 bit data, the 0th to the 15th) 9bit, 12bit be logical one (being high level), through AND gate circuit 5 with after, process the control end S0 that outputs to output device 7 through the first trigger 6 again, when if control end S0 reception signal is high level, the signal that output device (alternative selector) will select output to be connected to the D1 end is namely directly exported ACP_IN; Otherwise, output bus X_ACP[15:0 when the 3rd counter 4] 9bit, 12bit be not logical one entirely, output to output device 7 control end S0 and must be low level through AND gate circuit 5,6 processing of the first trigger again, show that the input increment signal that bearing increment pulse input end ACP_IN sends into the D1 end of output device 7 is 4096, need to carry out pulse regulation by the pulse regulation device, at this moment the low level signal that receives by the SO control end will make output device select the signal output of D0 end, i.e. signal after the selection output pulse regulation.Its method is, after bearing increment pulse ACP_IN input signal delivered to the second trigger 13, generate a kind of stable pulse signal, then by the second counter 12 this signal is done delay disposal, generate a stable pulse signal by the 3rd trigger 11 again, again with it and undressed bearing increment pulse signal through OR-circuit 9 additions, namely obtaining one tunnel total number is the signal of 8192 delta pulses, selects output by the D0 road of selector 7.
The effect of the first counter 10 and the second trigger 13 is: with Q3 road (23=8 the counting) output of the first counter 10, as the second trigger 13, the second counter 12, the 3rd trigger 11, the CLR end clear signal of the first counter 10, the output of the 3rd trigger 11 is approximately being stopped after 6.4 microseconds, the pulsewidth of the bearing increment pulse that produces after namely guarantee postponing be 8 * 0.8=6.4 microsecond (can select the output larger than the value of Q3 representative else and get final product if wish increases pulse duration, as with the Q3 of the first counter 10 and the output of Q2 two-way with after export again be 12 * 0.8=9.6 microsecond).In other words, the 3rd trigger 11 is used for the delay pulse from the first counter 12 is processed into a stable start pulse signal, 12 pulse durations that are used for limiting this signal of the second counter.
The effect of the second counter 12 is: will introduce through the pulse that the second trigger 13 is processed and make delay process.The Q end output signal of the second trigger 13 is introduced from the CE pin of the second counter 12, and the CLK_125 clock signal is introduced from the C pin of the second counter 12, and each a clock signal counts once, and the CEO pin output from the second counter 12 is selected in its output; CEO is the carry pin, namely must be behind this 8 digit counter meter foot 256 times, and the CEO pin just can be exported a pulse signal.256 * 0.8=204.8 microsecond, the bearing increment pulse input signal is directly connected to an input of OR-circuit 9, after 204.8 microseconds then will be delayed at least in another road, could arrive another road input of two input OR-circuits 9, the effect of OR-circuit 9 is that then the umber of pulse addition of this two-way pulse is exported.
The effect of the 3rd trigger 11: the CEO end of the second counter is connected with the C end of the 3rd trigger 11, makes stable pulse signal of Q end output of the 3rd trigger 11.
The effect of the first counter 10: the pulsewidth that is used for the delta pulse of control generation.Its Q3 pin is inputted approximately at the signal of CE pin and is exported a high level after 6.4 microseconds, makes the equal zero clearing of connected other device as reset signal.
Output device is a selector, and its effect is that the S0 control end by output device is selected D0 end or the signal output of D1 end, if the S0 control end receives is low level signal, then selects the D0 end to hold with ACP_OUT and is connected; If what the S0 control end received is high level signal, then select the D1 end to be connected with the ACP_OUT end.Between the Q of output device S0 control end and the first trigger 6 end, increase the pull down resistor PULLDOWN of a ground connection, its effect is to guarantee that when the output of the first trigger 6 was not high level signal, the signal that the S0 control end receives must be low level, and can not be in uncertain vacant state.Another effect of the first trigger 6 is, after radar powers up through an antenna scanning cycle, no matter the output of AND gate circuit 5 is high level or low level, as long as total number of the bearing increment pulse input signal of the C of the 3rd counter 4 end input do not occur from 4096 to 8192 the sudden change of (or conversely), the output Q of the first trigger 6 will remain that high level signal or low level signal are constant.
The signal of positive northern signal input part ARP_IN input is to rotate a circle when getting back to the positive north when antenna, this signal produces, be used as finishing signal with it, the counting of termination counter, to guarantee that next cycle counts from zero again, otherwise, counter in an antenna rotation period, will incessantly count maximum 8192 but unrestrictedly stored counts go down.
Clock signal input terminal CLK125 provides a kind of clock signal of counting usefulness, the frequency of this clock signal is 1.25 megahertzes, much larger than antenna (the common per minute of mechanical scanning radar rotation 6 circles that whenever rotate a circle, namely whenever circle and take approximately 10 seconds) 8192 corresponding frequencies of delta pulse of generation, can guarantee under the effect of this clock signal, can not miss the admission to each delta pulse, and the pulsewidth of each pulse signal that generates is controlled at easily usually about desired 6 microseconds.
Through above-mentioned processing, what no matter input is 4096 bearing increment pulses or 8192 bearing increment pulses, and final output can only be outwards to export with 8192 bearing increment pulses.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.
Claims (7)
1. a bearing increment pulse signal self-reacting device comprises bearing increment pulse input end ACP_IN, positive northern pulse input end ARP_IN, clock pulse input terminal CLK125 and bearing increment pulse output end ACP_OUT; Bearing increment pulse input end ACP_IN is used for input bearing increment pulse input signal; Positive northern pulse input end ARP_IN is used for inputting positive northern pulse input signal; Clock pulse input terminal CLK125 is used for input clock pulse signals; Bearing increment pulse output end ACP_OUT is used for the output signal after output is regulated, and it is characterized in that described bearing increment pulse signal self-reacting device forms by digital circuit, and described bearing increment pulse signal self-reacting device specifically comprises:
Pulse detecting equipment for detection of bearing increment pulse input signal type, and produces control signal;
The pulse regulation device is used for regulating bearing increment pulse input signal and output;
Output device, be used for being connected with pulse detecting equipment with described pulse regulation device, and according to the control signal of pulse detecting equipment output, by bearing increment pulse output end output pulse regulation device output signal or bearing increment pulse input signal, described pulse detecting equipment comprises the 3rd counter, AND gate circuit, the first trigger, described bearing increment pulse input signal is by the input of the 3rd counter C end, described positive northern pulse input signal is by the input of the 3rd counter CLR end, the 3rd counter output signal is by the 3rd counter output bus X_ACP 9bit, 12bit output, judge the type of bearing increment pulse input signal and export control signal through AND gate circuit, control signal is through the input of the first trigger C end, by being connected with output device after the output of the first trigger Q end.
2. a kind of bearing increment pulse signal self-reacting device according to claim 1, it is characterized in that described pulse detecting equipment also comprises pull down resistor PULLDOWN, be used for when the first trigger output signal is not high level, output device S0 port must keep low level, and can not be in uncertain vacant state, described pull down resistor PULLDOWN one end is connected with pulse detecting equipment output Q, pull down resistor PULLDOWN other end ground connection.
3. a kind of bearing increment pulse signal self-reacting device according to claim 1, it is characterized in that described pulse regulation device comprises the second trigger, the second counter, the 3rd trigger, the first counter, OR-circuit, described bearing increment pulse input signal is by the input of the second trigger C end, the second trigger Q end is connected with the CE end of the second counter, the second counter CEO end is connected with the 3rd trigger C end, the 3rd trigger Q end is held with the first counter CE respectively, OR-circuit one input connects, described the first counter Q3 end is exported as clear signal and is held with the first counter CLR respectively, the second trigger CLR end, the second counter CLR end, the 3rd trigger CLR holds connection, the C end of described the first counter, the C end of the second counter is the input clock pulse input signal respectively, another input input bearing increment pulse input signal of described OR-circuit; Described OR-circuit output signal is connected with the D0 port of output device; Described the first trigger D end, the second trigger D end, the 3rd trigger D end, the 3rd counter CE end connect respectively power Vcc.
4. a kind of bearing increment pulse signal self-reacting device according to claim 1, it is characterized in that described output device is selector, selector S0 end connects the first trigger Q end, selector D0 end connects the OR-circuit output, selector D1 end input bearing increment pulse input signal, selector ACP_OUT end is output.
5. bearing increment pulse signal self-reacting device processing method, it is characterized in that by the counting of positive northern pulse input signal control to orientation delta pulse input signal, type in order to detection orientation delta pulse input signal, and the pulse position of suitably regulating the bearing increment pulse input signal by the clock pulse input signal, so that the output signal unification is a kind of required bearing increment pulse output signals, concrete steps:
Step 1: input bearing increment pulse input signal, positive northern pulse input signal, clock pulse input signal;
Step 2, by detection orientation delta pulse input signal types, and output control signal, when if control signal is high level, then finally export bearing increment pulse input signal ACP_IN, if control signal is low level, then final output is by the bearing increment pulse signal of pulse regulation device adjusting.
6. a kind of bearing increment pulse signal self-reacting device processing method according to claim 5, it is characterized in that the pulse regulation device comprises the second trigger in the described step 2, the second counter, the 3rd trigger, the first counter, OR-circuit, described bearing increment pulse input signal is by the input of the second trigger C input, the second trigger Q output is connected with the second counter CE end, the second counter CEO output is connected with the 3rd trigger C input, the 3rd trigger Q output is connected with the first counter CE input respectively, OR-circuit one input connects, described the first counter as clear signal, is held the Q3 output respectively with the first counter CLR, the second trigger CLR end, the second counter CLR end, the 3rd trigger CLR holds connection; Described the first counter C end, the second counter C end be the input clock pulse input signal respectively; Described OR-circuit other end input bearing increment pulse input signal, the OR-circuit output signal links to each other with output device D0, and the first trigger D end, the second trigger D end, the 3rd trigger D end connect respectively power Vcc.
7. a kind of bearing increment pulse signal self-reacting device processing method according to claim 5, it is characterized in that described bearing increment pulse input signal is 4096 or 8192, come the counting of control counter execution cycle inner orientation delta pulse number by positive northern pulse input signal, when pulse input signal is 4096, cooperate counter and trigger to the adjusting of delaying time of orientation delta pulse by the clock pulse input signal, then the delta pulse phase "or" original with another road, the unification of bearing increment pulse input signal is 8192 pulses outputs the most at last.
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| CN105093202B (en) * | 2015-08-25 | 2018-09-11 | 四川九洲电器集团有限责任公司 | Serial bearing data interpolation smoothing method and device |
| CN106597395B (en) * | 2016-12-19 | 2019-02-26 | 四川九洲电器集团有限责任公司 | A kind of real-time pulse orientation detecting method and radar equipment |
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