CN102354304B - Data transmission method, data transmission device and SOC (system on chip) - Google Patents
Data transmission method, data transmission device and SOC (system on chip) Download PDFInfo
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- CN102354304B CN102354304B CN 201110283906 CN201110283906A CN102354304B CN 102354304 B CN102354304 B CN 102354304B CN 201110283906 CN201110283906 CN 201110283906 CN 201110283906 A CN201110283906 A CN 201110283906A CN 102354304 B CN102354304 B CN 102354304B
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Abstract
The invention provides a data transmission method which is used for transmitting n-bit data to an n-bit memorizer by an m-bit processor. The data transmission method comprises the steps of: forming into y-x group of data by n-m bit data extracted from an assigned address of a plurality of groups of n-bit data in each unit, forming into y group of data in cooperation with extracted x group of m-bit data if the bit of the data is less than m bit, transmitting the data by the m-bit processor, reconverting y group of data into x group of n-bit data according to a corresponding relationship duringextracting, and inputting the x group of n-bit data into the n-bit memorizer. Correspondingly, the invention further provides a data transmission device. By adopting the technical scheme, the data among the devices with different bits can be transmitted, so that the accuracy degree corrected by Gamma can be improved, and the production cost can be effectively controlled.
Description
Technical field
The present invention relates to data transmission technology, in particular to a kind of data transmission method, a kind of data transmission device and a kind of SOC chip.
Background technology
In the design of television video process chip and application, last demonstration link after signal is processed, owing to being nonlinear relationship between the luminosity response of display device and the input signal (voltage), therefore, before the input signal driving display, input signal should be done pre-service.Gamma proofreaies and correct and can be considered to the indemnifying measure this nonlinear response taked for reproducing correct luminosity response, and its correction function is: L=E
1/ γ, adopt the method for look-up table (LUT) to realize the Gamma of input signal is proofreaied and correct.After powering on, CPU is written to default Gamma value in the Gamma look-up table (RAM256x10), and for the loss of the gray level that reduces the bright dark place in the image, the method that adopts 10 Gamma to proofread and correct, this can promote the accuracy of correction effectively than 8 common bit corrections.But because some cpu deal with data of 8 generally all is as the basis take the 8bit bit wide, comprise some processing of data and the transmission of data, can't be complementary with above-mentioned 10 bit correction data, so need a 8bit to realize mutual conversion between 8 bit data and 10 bit data to the converter of 10bit, then write during Gamma shows.
Therefore, need a kind of new data transmission technology, can realize the transmission of data between the device of a plurality of not isotopic numbers, thereby promote the accuracy that Gamma proofreaies and correct, and production control cost effectively.
Summary of the invention
In order one of to solve the problems of the technologies described above at least, the invention provides a kind of data transmission technology, can realize the transmission of data between the device of a plurality of not isotopic numbers, thereby promote the accuracy that Gamma proofreaies and correct, and production control cost effectively.
In view of this, the present invention proposes a kind of data transmission method, described data are the n bit data, and described n bit data transfers to the n bit memory by the m bit processor, wherein n＞m and n, m are positive integer, and described method comprises: step 102, the many groups n bit data that receives is stored; Step 104, according to n * x=m * y, and x and y be necessary for the condition of positive integer, and described many group n bit data are divided into a plurality of unit that each unit has x group n bit data; Step 106, the n-m bit data that the specific bit of every group of n bit data from described each unit is extracted is combined as y-x group data, the figure place of described y-x group data is not more than the m position, store the corresponding relation between described specific bit and the described n-m bit data data bit in described y-x group data, and with consisting of y group data through the x group m bit data that obtains after the described extraction in described y-x group data and described each unit, described y group data are exported in the described processor; Step 108 will be stored from the described y group data of described processor; Step 110, described corresponding relation according to storage, according to being reduced to described specific bit, make described y group data be converted to x group n bit data the bits per inch in the described y-x group data in the described y group data, then described x group n bit data is inputed to described n bit memory.In this technical scheme, because the limit bandwidth of processor when transmission, cause can't be directly with data transmission to the n bit memory, proofread and correct and carry out Gamma in the Gamma look-up table that this n bit data need to comprise in the n bit memory, and the figure place dress that need to carry out data changes.The processor here or CPU comprise single-chip microcomputer, DSP, ARM, FPGA etc.When changing, n is greater than m, and then x is less than y, and namely y-x is the number greater than 0.Owing to n and m are not further limited, when then x being organized in the data n-m bit data that obtains in every group of data and making up, if other are the m bit data, then last group data may be less than or equal to the m position, but as long as figure place is not more than the m position, this does not affect transmission course and result, because in combination, these data data bit of living in when having stored the specific bit of extracting these data and combination, convenient after transfer process in carry out restoring operation, obtain exactly the data identical with original n bit data.
According to another aspect of the invention, also proposed a kind of data transmission device, described data are the n bit data, and described n bit data transfers to the n bit memory by the m bit processor, wherein n＞m and n, m are positive integer, and described device comprises: the first buffer, many groups n bit data that storing received arrives; Modular converter, comprise grouped element, extraction unit, assembled unit, storage unit and the first output unit, wherein, described grouped element, according to n * x=m * y, wherein x and y are necessary for the condition of positive integer, the described many group n bit data that are stored in described the first buffer are divided into a plurality of unit that each unit has x group n bit data, described extraction unit, the specific bit of every group of n bit data from described each unit is extracted the n-m bit data, described assembled unit, the described n-m bit data that described extraction unit is extracted is combined as y-x group data, the figure place of described y-x group data is not more than the m position, and will consist of y group data through the x group m bit data that obtains after the described extraction in described y-x group data and described each unit, the figure place of described y group data is not more than the m position, described storage unit, store the corresponding relation between described specific bit and the described n-m bit data data bit in described y-x group data, and described the first output unit, described y group data are exported in the described processor; Described processor will be from described y group data transmission to the second buffer of described the first buffer; Described the second buffer, storage is from the y group data of described processor; Recovery module, comprise acquiring unit, split cells, processing unit and the second output unit, wherein said acquiring unit, obtain the described corresponding relation of the described storage unit that is stored in the described modular converter, described split cells, according to described corresponding relation, to split from the described y-x group data in the described y group data of described the second buffer, described processing unit, according to described corresponding relation, the bits per inch certificate that obtains after the described split cells fractionation is reduced to corresponding specific bit, make described y group data be converted to x group n bit data, and second output unit, described x group n bit data is inputed to storer; Described storer receives the described x group n bit data from described recovery module.In this technical scheme, because the limit bandwidth of processor when transmission, cause can't be directly with data transmission to the n bit memory, and this n bit data need to be carried out Gamma and proofreaied and correct in the Gamma look-up table that storer comprises, and the figure place dress that need to carry out data changes.The processor here or CPU comprise single-chip microcomputer, DSP, ARM, FPGA etc.When changing, n is greater than m, and then x is less than y, and namely y-x is the number greater than 0.Owing to n and m are not further limited, when then x being organized in the data n-m bit data that obtains in every group of data and making up, if other are the m bit data, then last group data may be less than or equal to the m position, but as long as figure place is not more than the m position, this does not affect transmission course and result, because in combination, these data data bit of living in when having stored the specific bit of extracting these data and combination, convenient after transfer process in carry out restoring operation, obtain exactly the data identical with original n bit data.
According to another aspect of the invention, also propose a kind of SOC chip, comprised the data transmission device described in above-mentioned technical scheme.In this technical scheme, this data transmission device can be integrated in the SOC chip, thereby when realizing identical data-transformation facility, reduces the volume of device, the room for promotion utilization factor.
Description of drawings
Fig. 1 shows the according to an embodiment of the invention process flow diagram of data transmission method;
Fig. 2 shows the according to an embodiment of the invention block diagram of data transmission device;
Fig. 3 shows the according to an embodiment of the invention schematic diagram of data transmission;
Fig. 4 shows the according to an embodiment of the invention block diagram of SOC chip;
Fig. 5 shows the according to an embodiment of the invention block diagram of display device; And
Fig. 6 shows the according to an embodiment of the invention schematic diagram of data transmission system.
Embodiment
In order more clearly to understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments the present invention is further described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, still, the present invention can also adopt other to be different from other modes described here and implement, and therefore, the present invention is not limited to the restriction of following public specific embodiment.
Fig. 1 shows the according to an embodiment of the invention process flow diagram of data transmission method.
As shown in Figure 1, data transmission method according to an embodiment of the invention, these data are the n bit data, and the n bit data transfers to the n bit memory by the m bit processor, wherein n＞m and n, m are positive integer, and method comprises: step 102, the many groups n bit data that receives is stored; Step 104, according to n * x=m * y, and x and y be necessary for the condition of positive integer, is divided into a plurality of unit that each unit has x group n bit data with organizing the n bit data more; Step 106, the n-m bit data that the specific bit of every group of n bit data from each unit is extracted is combined as y-x group data, the figure place of these y-x group data is not more than the m position, corresponding relation between storage specific bit and the n-m bit data data bit in y-x group data, and y-x is organized the x group m bit data formation y that process obtains after extracting in data and each unit organize data, y is organized data export in the processor; Step 108, the y of self processor group data are stored in the future; Step 110 according to the corresponding relation of storage, is organized bits per inch in the y-x group data in the data according to being reduced to specific bit with y, makes y group data be converted to x group n bit data, then x is organized the n bit data and inputs to storer.In this technical scheme, because the limit bandwidth of processor when transmission, cause can't be directly with data transmission to the n bit memory, proofread and correct and carry out Gamma in the Gamma look-up table that this n bit data need to comprise in the n bit memory, and the figure place dress that need to carry out data changes.The processor here or CPU comprise single-chip microcomputer, DSP, ARM, FPGA etc.When changing, n is greater than m, and then x is less than y, and namely y-x is the number greater than 0.Owing to n and m are not further limited, when then x being organized in the data n-m bit data that obtains in every group of data and making up, if other are the m bit data, then last group data may be less than or equal to the m position, but as long as figure place is not more than the m position, this does not affect transmission course and result, because in combination, these data data bit of living in when having stored the specific bit of extracting these data and combination, convenient after transfer process in carry out restoring operation, obtain exactly the data identical with original n bit data.
In technique scheme, by the restriction to n, m, x, when being the lowest common multiple of n and m such as the numerical value at n * x, guaranteed after x being organized the conversion of n bit data, what obtain is that y organizes the m bit data, and the situation of a certain group of data deficiencies m position can not appear, and make the conversion of data neat, be convenient to record is carried out in the data position.Certainly, whether carry out the neat conversion of form for not impact of result, as long as the data after the conversion can not exceed the m position restriction of processor.
In technique scheme, specific bit comprises that the minimum data position of n bit data plays the 1st to the n-m position.In this technical scheme, extraction be the n-m bit data that rise n bit data minimum data position, this is convenient to position record and behavior adjustment management.Certainly, selection for specific bit is not vital step, for the n bit data, can choose in advance specific bit by the user, also can when conversion, be chosen at random by system, can correctly transmit as long as correctly recorded the data residing data bit in n bit data and m bit data that is selected.
In technique scheme, when described n bit data was 10 bit data, described m bit data was 8 bit data, and described x group is 4 groups, and described y group is 5 groups.In this technical scheme, a kind of situation is transmitted for 10 bit data are converted to 8, and then this 8 bit data is reduced to 10 bit data, can choose 4 group of 10 bit data as a unit this moment, transmit after being converted to 5 group of 8 bit data, and then this 5 group of 8 bit data is being reduced to 4 group of 10 bit data, realize data transfer.
In technique scheme, comprise the Gamma look-up table in the n bit memory, and the x group n bit data that obtains is offered the Gamma look-up table.In this technical scheme, the n bit data is transferred to the n bit memory after via the m bit processor from the outside, the Gamma look-up table that is used for storer carries out Gamma and proofreaies and correct, data transfer mode by technique scheme, the problem that the figure place of carrying out the data that Gamma proofreaies and correct that can effectively solve input and the figure place of processor do not conform to, thereby can input the data of any digit, and the data of high bit number can improve the accuracy that Gamma proofreaies and correct, promote the user and experience.
Fig. 2 shows the according to an embodiment of the invention block diagram of data transmission device.
As shown in Figure 2, according to an embodiment of the invention in the data transmission device 200, data are the n bit data, and the n bit data transfers to n position Gamma look-up table by m bit processor 216, wherein n＞m and n, m are positive integer, device 200 comprises: the first buffer 202, many groups n bit data that storing received arrives; Modular converter 204, comprise grouped element 206, extraction unit 208, assembled unit 210, storage unit 212 and the first output unit 214, wherein, grouped element 206, according to n * x=m * y, wherein x and y are necessary for the condition of positive integer, the many groups n bit data that is stored in the first buffer 202 is divided into a plurality of unit that each unit has x group n bit data, extraction unit 208, the specific bit of every group of n bit data from each unit is extracted the n-m bit data, assembled unit 210, the n-m bit data that extraction unit 208 is extracted is combined as y-x group data, the figure place of described y-x group data is not more than the m position, and y-x is organized the x group m bit data formation y that process obtains after extracting in data and each unit organize data, storage unit 212 is stored the corresponding relation between specific bit and the n-m bit data data bit in y-x group data, and first output unit 214, y is organized data export in the processor 216; Processor 216 will be from y group data transmission to the second buffer 218 of the first buffer 202; The second buffer 218, storage come the y group data of self processor 216; Recovery module 220, comprise acquiring unit 222, split cells 224, processing unit 226 and the second output unit 228, wherein acquiring unit 222, obtain the corresponding relation of the storage unit 212 that is stored in the modular converter 204, split cells 224, according to corresponding relation, to split from the y-x group data in the y group data of the second buffer 218, processing unit 226, according to corresponding relation, the bits per inch certificate that obtains after split cells 224 fractionations is reduced to corresponding specific bit, make y group data be converted to x group n bit data, and second output unit 228, x is organized the n bit data input to storer; Storer 230 receives the x group n bit data from recovery module 220.In this technical scheme, because the limit bandwidth of processor 216 when transmission, cause can't be directly with data transmission to the n bit memory, and this n bit data need to be carried out Gamma and proofreaied and correct in the Gamma look-up table that storer comprises, and the figure place dress that need to carry out data changes.Here processor 216 or CPU comprise single-chip microcomputer, DSP, ARM, FPGA etc.When changing, n is greater than m, and then x is less than y, and namely y-x is the number greater than 0.Owing to n and m are not further limited, when then x being organized in the data n-m bit data that obtains in every group of data and making up, if other are the m bit data, then last group data may be less than or equal to the m position, but as long as figure place is not more than the m position, this does not affect transmission course and result, because in combination, these data data bit of living in when having stored the specific bit of extracting these data and combination, convenient after transfer process in carry out restoring operation, obtain exactly the data identical with original n bit data.
In technique scheme, by the restriction to n, m, x, when being the lowest common multiple of n and m such as the numerical value at n * x, guaranteed after x being organized the conversion of n bit data, what obtain is that y organizes the m bit data, and the situation of a certain group of data deficiencies m position can not appear, and make the conversion of data neat, be convenient to record is carried out in the data position.Certainly, whether carry out the neat conversion of form for not impact of result, as long as the data after the conversion can not exceed the m position restriction of processor.
In technique scheme, specific bit comprises that the minimum data position of n bit data plays the 1st to the n-m position.In this technical scheme, extraction be the n-m bit data that rise n bit data minimum data position, this is convenient to position record and behavior adjustment management.Certainly, selection for specific bit is not vital step, for the n bit data, can choose in advance specific bit by the user, also can when conversion, be chosen at random by system, can correctly transmit as long as correctly recorded the data residing data bit in n bit data and m bit data that is selected.
In technique scheme, when described n bit data was 10 bit data, described m bit data was 8 bit data, and described x group is 4 groups, and described y group is 5 groups.In this technical scheme, a kind of situation is transmitted for 10 bit data are converted to 8, and then this 8 bit data is reduced to 10 bit data, can choose 4 group of 10 bit data as a unit this moment, transmit after being converted to 5 group of 8 bit data, and then this 5 group of 8 bit data is being reduced to 4 group of 10 bit data, realize data transfer.
In technique scheme, comprise the Gamma look-up table in the n bit memory, and the x group n bit data that obtains is offered the Gamma look-up table.In this technical scheme, the n bit data is transferred to the n bit memory after via the m bit processor from the outside, the Gamma look-up table that is used for storer carries out Gamma and proofreaies and correct, data transfer mode by technique scheme, the problem that the figure place of carrying out the data that Gamma proofreaies and correct that can effectively solve input and the figure place of processor do not conform to, thereby can input the data of any digit, and the data of high bit number can improve the accuracy that Gamma proofreaies and correct, promote the user and experience.
Fig. 3 shows the according to an embodiment of the invention schematic diagram of data transmission.
As shown in Figure 3, in this data transmission procedure, 10 bit data 302 need to be transferred to and carry out the Gamma correction in the Gamma look-up table 310, the Gamma look-up table here is arranged in RAM, certainly, also can be stored in other storage medium, and this is apparent.But because the processor 306 that needs to utilize in the transmission course may not be that 10 bit strips are wide, but may be that 8 bit strips are wide, then owing to limit bandwidth, can not directly transmit, thereby need to carry out the conversion of data bits.Such as 10 bit data 302 are converted to 8 bit data by 10 to 8 bit pads 304, then by processor 306 this 8 bit data is transferred to 8 to 10 bit pads, again be converted to 10 bit data, again this 10 bit data transferred to Gamma look-up table 310 and carry out the Gamma correction.Here mainly be to receive data from the outside because Gamma look-up table 310 must pass through processor 306, and the figure place of processor 306 is not necessarily with Gamma look-up table 310 or external data is identical such as the figure place of 10 bit data 302, thereby can cause the difference of data bits, thereby need to carry out the data bits conversion.
When carrying out data-switching, at first be to carry out 10 when being converted to 8, may comprise a lot of groups of data for 10 bit data, be 10 bit data in every group, this moment can be with per 4 group of 10 bit data as a unit, thereby comprise 40 data in the unit, just in time after being converted to 8 bit data, consist of 5 groups of data.Certainly, this is more convenient during for data-switching and circuit design.Such as certainly selecting 3 group of 10 bit data as a unit, thereby when being converted to 8 bit data, can obtain 3 group of 8 bit data and 1 group of 6 bit data, but organize 6 bit data for this, because figure place is less than 8, still can realize transmission by this processor of 8 306, and for not impact of result.Certainly, carrying out 10 bit data when being converted to 8 bit data, need to extract and reconfigure certain 2 bit data in 10 bit data, consist of and be not more than 8 data.The position of the extraction here is such as being called " specific bit ", this specific bit can be chosen by the user in advance, also can when moving, automatically be selected immediately by system, because here after selecting and extracting the data of this data bit, and the residing data bit in 8 the data that is not more than that is regenerating for these data, need to carry out the storage of corresponding relation, thereby the data bit of no matter presetting or the random data bit of selecting, it is when again being converted to 10 bit data or other bit data, all can be reduced with reference to this corresponding relation, thereby be finished data transfer.
Fig. 4 shows the according to an embodiment of the invention block diagram of SOC chip.
As shown in Figure 4, SOC chip 400 according to the present invention comprises the data transmission device 402 described in above-mentioned technical scheme, and other circuit and parts 404.In this technical scheme, this data transmission device can be integrated in the SOC chip, thereby when realizing identical data-transformation facility, reduces the volume of device, the room for promotion utilization factor.
Fig. 5 shows the according to an embodiment of the invention block diagram of display device.
As shown in Figure 5, display device 500 according to the present invention comprises the data transmission device 502 described in above-mentioned technical scheme, and other circuit and parts 504.In this technical scheme, by using this data transmission device, the display of display device is proofreaied and correct, display effect is promoted better.If used the SOC chip that comprises this data transmission device, then can when realizing this data-transformation facility, reduce the volume of display device, promote the user and experience.
Fig. 6 shows the according to an embodiment of the invention schematic diagram of data transmission system.
As shown in Figure 6, the data of inputting from the outside at first are stored in the first buffer 602, then carry out the conversion of data bits by modular converter 604.The data of supposition input here are 10 bit data, and processor is that single-chip microcomputer 610 is 8 bit data.Many groups of 10 bit data that a CPU606 in the modular converter 604 will input are divided into groups, suppose and be divided into a plurality of unit here, comprise 4 group of 10 bit data in each unit, then a CPU606 carries out identical operation to the data of each unit, only describes with regard to the data of a unit here.
The one CPU606 extracts the data of the specific bit of every group of data in 4 group of 10 bit data in the unit, the specific bit here can be for such as 2 data bit, these 2 data bit specifically this group data in residing position can be prior setting, also can be when system's 600 operation, automatically to choose at random, for not impact of result, because in the data of having chosen specific bit, such as 2 in 10 bit data here, then 4 groups of data have 8 data altogether, and utilize these data to be combined into one group of 8 bit data, here when combination, the data that are selected residing position in former data is specific bit, and the corresponding relation that these data exist between the residing position in new this 8 bit data that forms need to be stored among the RAM608, therefore, no matter this specific bit is default or random, because the existence of corresponding relation can guarantee can not make a mistake when reduction.
Through behind the leaching process, 10 bit data have originally become 4 group of 8 bit data, add 1 group of 8 newly-generated bit data, consist of 5 group of 8 bit data, can transfer to by 8 single-chip microcomputer 610 in the second buffer 612 to carry out buffer memory.
Then, 5 group of 8 bit data that recovery module 614 is extracted in this second buffer 612, there is 1 group of data to generate when changing afterwards in this 5 group of 8 bit data, the 2nd CPU616 in the recovery module 614 is specific bit according to the data that are selected residing position in former data of before modular converter 604 generations, and the corresponding relation that in new this 8 bit data that forms, exists between the residing position of these data, thereby behind 1 group of newly-generated Data Division in 5 group of 8 bit data, reinsert in all the other 4 groups of data, again obtain 4 group of 10 bit data.Here need to prove, apparent, the 2nd CPU616 is when carrying out data-switching, need to extract the corresponding relation of storing among the RAM608 from modular converter 604, this corresponding relation can obtain when the 2nd CPU616 needs, also can in 5 group of 8 bit data of transmission, be sent among the 2nd CPU616.
At last, 4 group of 10 bit data that recovery module 614 will regenerate is sent to a RAM618, includes the Gamma look-up table that carries out Gamma timing needs among the RAM618, proofreaies and correct thereby utilize this 4 group of 10 bit data to carry out Gamma.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a data transmission method is characterized in that, described data are the n bit data, and described n bit data transfers to n bit memory, wherein n by the m bit processor〉m and n, m be positive integer,
Described method comprises:
Step 102 is stored the many groups n bit data that receives;
Step 104, according to n * x=m * y, wherein x and y are necessary for the condition of positive integer, and described many group n bit data are divided into a plurality of unit that each unit has x group n bit data;
Step 106, the n-m bit data that the specific bit of every group of n bit data from described each unit is extracted is combined as y-x group data, the figure place of wherein said y-x group data is not more than the m position, store the corresponding relation between described specific bit and the described n-m bit data data bit in described y-x group data, and with consisting of y group data through the x group m bit data that obtains after the described extraction in described y-x group data and described each unit, described y group data are exported in the described processor;
Step 108 will be stored from the described y group data of described processor;
Step 110, described corresponding relation according to storage, according to being reduced to described specific bit, make described y group data be converted to x group n bit data the bits per inch in the described y-x group data in the described y group data, then described x group n bit data is inputed to described n bit memory.
2. data transmission method according to claim 1 is characterized in that,
Described specific bit comprises that the minimum data position of described n bit data plays the 1st to the n-m position.
According to claim 1 and 2 in each described data transmission method, it is characterized in that,
When described n bit data was 10 bit data, described m bit data was 8 bit data, and described x group is 4 groups, and described y group is 5 groups.
4. data transmission method according to claim 1 and 2 is characterized in that,
Comprise the Gamma look-up table in the described n bit memory, and the described x group n bit data that will obtain offers described Gamma look-up table.
5. a data transmission device is characterized in that, described data are the n bit data, and described n bit data transfers to n bit memory, wherein n by the m bit processor〉m and n, m be positive integer,
Described device comprises:
The first buffer, many groups n bit data that storing received arrives;
Modular converter comprises grouped element, extraction unit, assembled unit, storage unit and the first output unit, wherein,
Described grouped element, according to n * x=m * y, wherein x and y are necessary for the condition of positive integer, and the described many group n bit data that are stored in described the first buffer are divided into a plurality of unit that each unit has x group n bit data,
Described extraction unit, the specific bit of every group of n bit data from described each unit is extracted the n-m bit data,
Described assembled unit, the described n-m bit data that described extraction unit is extracted is combined as y-x group data, the figure place of described y-x group data is not more than the m position, and will consist of y group data through the x group m bit data that obtains after the described extraction in described y-x group data and described each unit
Described storage unit is stored the corresponding relation between described specific bit and the described n-m bit data data bit in described y-x group data, and
Described the first output unit exports described y group data in the described processor to;
Described processor will be from described y group data transmission to the second buffer of described the first buffer;
Described the second buffer, storage is from the y group data of described processor;
Recovery module comprises acquiring unit, split cells, processing unit and the second output unit, wherein
Described acquiring unit obtains the described corresponding relation of the described storage unit that is stored in the described modular converter,
Described split cells according to described corresponding relation, will split from the described y-x group data in the described y group data of described the second buffer,
Described processing unit according to described corresponding relation, is reduced to corresponding specific bit with the bits per inch certificate that obtains after the described split cells fractionation, makes described y group data be converted to x group n bit data, and
The second output unit inputs to storer with described x group n bit data;
Described storer receives the described x group n bit data from described recovery module.
6. data transmission device according to claim 5 is characterized in that, comprising:
Described specific bit comprises that the minimum data position of described n bit data plays the 1st to the n-m position.
7. according to claim 5 or 6 described data transmission devices, it is characterized in that, comprising:
When described n bit data was 10 bit data, described m bit data was 8 bit data, and described x group is 4 groups, and described y group is 5 groups.
8. according to claim 5 or 6 described data transmission devices, it is characterized in that,
Comprise the Gamma look-up table in the described storer, and will offer described Gamma look-up table from the described x group n bit data of described recovery module.
9. a SOC chip is characterized in that, comprises such as each described data transmission device in the claim 5 to 8.
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Address after: 266555 Qingdao economic and Technological Development Zone, Shandong, Hong Kong Road, No. 218 Patentee after: Hisense Video Technology Co., Ltd Address before: 266555 Qingdao economic and Technological Development Zone, Shandong, Hong Kong Road, No. 218 Patentee before: HISENSE ELECTRIC Co.,Ltd. |