CN102347358A - Semiconductor device structure and manufacturing method thereof - Google Patents
Semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN102347358A CN102347358A CN2010102427253A CN201010242725A CN102347358A CN 102347358 A CN102347358 A CN 102347358A CN 2010102427253 A CN2010102427253 A CN 2010102427253A CN 201010242725 A CN201010242725 A CN 201010242725A CN 102347358 A CN102347358 A CN 102347358A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
The invention provides a semiconductor device structure and a manufacturing method thereof, wherein the semiconductor device structure comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate region formed on the channel region; the source/drain regions are formed on two sides of the channel region; a metal plug in contact with the gate region or the source/drain region; a dielectric layer formed around the metal plug and formed in one step from a bottom to a top of the metal plug. The embodiment of the invention is suitable for enhancing the channel stress of the device and reducing the parasitic capacitance of the device.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology field, the particularly a kind of semiconductor device structure and manufacturing approach thereof that can strengthen channel stress.
Background technology
Along with constantly dwindling of semiconductor device structure, channel region mobility of charge carrier rate receives very big influence.In order to improve channel region mobility of charge carrier rate, a kind of way commonly used is utilized stress engineering exactly, for example can be in the interlayer dielectric layer above source/drain structure or the device architecture stress application.Compression need be in channel region, applied for pMOSFET (p type metal oxide semiconductor field-effect transistor), tension stress need be in channel region, applied for nMOSFET (n type metal oxide semiconductor field-effect transistor).
In the prior art; The usual manner of stress application is as shown in Figure 1 in channel region: form that grid pile up 100, source/drain region 200 with and on the metal silicide (not shown) after, deposit stress nitride thing layer 300 and other dielectric layer 400 (for example oxide skin(coating)) successively.Wherein, for pMOSFET, stress nitride thing layer 300 has compression, and for nMOSFET, stress nitride thing layer 300 has tension stress, thereby can be respectively the raceway groove both sides of pMOSFET is applied compression or the raceway groove both sides of nMOSFET are applied tension stress.Can form the stress of nitride layer through the technological parameter of control deposition process.Etching oxide layer 400 and stress nitride thing layer 300 to metal silicide are then filled metal or other electric conducting material to form metal closures 500 to form contact hole in contact hole then.Prior art problems is, the process that forms metal closures can cause inner stress filtration of preformed stress nitride thing layer or loss fully, and, the reducing of height that piles up along with grid and spacing, this stress loss effect can be more and more obvious.
Summary of the invention
The object of the invention is intended to one of solve the problems of the technologies described above at least, particularly solves the internal stress problem that quilt is weakened owing to the formation of follow-up metal closures of the stress nitride thing layer that forms earlier.
For achieving the above object, one aspect of the present invention has proposed a kind of semiconductor device structure, comprising: Semiconductor substrate; Channel region is formed on the Semiconductor substrate; Gate regions is formed on the channel region; Source/drain region is formed at the channel region both sides; Metal closures contacts with gate regions or source/drain region; Dielectric layer forms around metal closures, and from the bottom of metal closures to the top, dielectric layer is one-time formed.
Preferably, the material of dielectric layer has stress, and for example for pMOSFET, dielectric layer has compression, and for nMOSFET, dielectric layer has tension stress.The material of dielectric layer can comprise the stress nitride thing.
Preferably, the material of dielectric layer can comprise the low k dielectric material, for example can be SiO
2, one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG and the BPSG.
Alternatively, source/drain region is embedded in Semiconductor substrate formation; Or source/drain region is hoist type source/drain region (raised S/D).For pMOSFET, source/drain region can be formed by SiGe, and for nMOSFET, source/drain region can be formed by Si:C.
Preferably, wherein the outside of gate regions directly contacts with dielectric layer, can reduce the grid parasitic capacitance.
In one embodiment of the invention, contact with metal closures on only active/drain region, and said metal closures and height such as gate regions grade.Therefore embodiments of the invention can form technology by compatible dual contact.
The present invention proposes a kind of formation method of above-mentioned semiconductor device structure on the other hand, may further comprise the steps: Semiconductor substrate is provided; On Semiconductor substrate, form the side wall in the gate regions and the gate regions outside; Both sides in gate regions form source/drain region; On Semiconductor substrate with the corresponding formation of gate regions or source/drain region metal closures; On Semiconductor substrate, form first dielectric layer so that the bottom of metal closures to the top by first dielectric layer around.
Preferably, gate regions is formed by sacrifice gates; Then after forming side wall, method further comprises: sacrifice gates is removed in side wall, to form opening; And in opening, form replacement gate.Wherein, in opening, form before the replacement gate, may further include: in opening, form gate dielectric layer.
Preferably, comprising with the corresponding formation of said gate regions and source/drain region metal closures on the Semiconductor substrate: on Semiconductor substrate, form second dielectric layer; In second dielectric layer,, and in contact hole, fill metal formation metal closures with the corresponding formation of gate regions or source/drain region contact hole; Second dielectric layer is removed.In one embodiment of the invention, only corresponding with source/drain region formation contact hole is filled metal and is formed metal closures in said contact hole, and the contact hole and the height such as said gate regions grade that form.Therefore embodiments of the invention can also form technology by compatible dual contact.
The method that forms first dielectric layer can comprise: the using plasma chemical gas-phase deposition enhanced forms first dielectric layer with stress.For pMOSFET, first dielectric layer has compression, and for nMOSFET, first dielectric layer has tension stress.
The material of first dielectric layer can comprise the low k dielectric material, for example can be SiO
2, one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG and the BPSG.
The method that wherein forms source/drain region can comprise: the etching semiconductor substrate forms groove in the outside of side wall; And extension forms source/drain region in groove.Wherein, for pMOSFET, source/drain region can be formed by SiGe, and for nMOSFET, source/drain region can be formed by Si:C.
Alternatively, can form hoist type source/drain region.
Preferably, when removing sacrifice layer, this method may further include: the side wall in the gate regions outside is removed, thereby the dielectric layer of winning is directly contacted with the grid outside, can reduce the grid parasitic capacitance.
Semiconductor device structure that proposes according to the embodiment of the invention and forming method thereof; Dielectric around metal closures is one-time formed after forming metal closures; So the internal stress of having avoided the stressor layers of first formation is weakened by the formation technology of follow-up metal closures or the problem of elimination; Thereby can improve the stress in the semiconductor device channel region greatly, improve the mobility of charge carrier rate.This method also is applicable to MOSFET (mos field effect transistor) device with lifting source/drain electrode structure, and can with first grid (gate first) and back grid (gate last) process compatible.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
Fig. 1 is the sketch map of semiconductor device structure in the prior art;
The semiconductor device structure sketch map of Fig. 2-3 for obtaining according to one embodiment of the invention;
Fig. 4-15 makes the intermediate steps sketch map of the method for semiconductor device structure for forming the embodiment of the invention.
The semiconductor device structure sketch map of Figure 16-17 for obtaining according to another embodiment of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; Below first characteristic of Miao Shuing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
The present invention proposes contact hole and metal closures are formed in sacrifice layer; Remove the method that sacrifice layer centers on the new stress dielectric layer of metal closures deposit afterwards again; Avoided in common process since earlier the internal stress of the stress dielectric layer that forms weakened by follow-up contact hole technology; Thereby can improve the stress of channel region both sides, improve the mobility of charge carrier rate.Below with the mode of specific embodiment above-mentioned thought of the present invention is introduced; Need to prove: following examples only are preferred implementations of the present invention; Be not that the present invention only can realize through following examples; Those skilled in the art can make modification or the replacement that is equal to following examples based on inventive concept, and modification that these are equal to or replacement all should be included within protection scope of the present invention.Particularly; To be example explanation embodiments of the invention below with CMOSFET (CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor); But should note; The device that includes only pMOSFET or include only nMOSFET also belongs to protection scope of the present invention; The device architecture of other that forms for the method through the embodiment of the invention or final devices structure fall into claim scope of the present invention, also belong to embodiments of the invention.
Fig. 2 is the CMOSFET structural representation of the embodiment of the invention, and this CMOSFET structure comprises: Semiconductor substrate 1000; On Semiconductor substrate 1000, with the nMOSFET district 102 and the pMOSFET district 104 of STI 1002 (shallow trench isolation leaves) separation; Channel region 1004 is formed on the Semiconductor substrate 1000; Gate regions 1006 is formed on the channel region 1004; Source/drain region 1008 is formed at channel region 1004 both sides; Metal closures 1010 contacts with gate regions 1006 or source/drain region 1008; Dielectric layer 1012 forms around metal closures 1010, and from the bottom of metal closures 1010 to the top, dielectric layer 1012 is one-time formed.
Particularly, gate regions 1006 can comprise, gate dielectric layer 1014 and gate conductor layer 1016.Gate conductor layer 1016 can be formed by polysilicon, and perhaps the lamination by conductor and polysilicon forms, and the present invention does not limit this.Can comprise metal silicide 1018 on source/drain region 1008 and the gate conductor layer 1016, thereby help reducing the contact resistance of device.
Preferably, the material of dielectric layer 1012 has stress.For example for pMOSFET, dielectric layer has compression; For nMOSFET, dielectric layer has tension stress.The material of dielectric layer is preferably the stress nitride thing.Therefore embodiments of the invention can be applicable to dual stressed films technology (dual stress linerprocess), can improve the mobility of charge carrier on the channel region, effectively improve the performance of device.
Preferably, the material of dielectric layer 1012 can also be the low k dielectric material, for example comprises: SiO
2, one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG and the BPSG.The low k dielectric material helps reducing the grid parasitic capacitance.
The thickness of dielectric layer 1012 is preferably 70-300nm.
Alternatively, source/drain region 1008 is embedded in Semiconductor substrate 1000 formation; Perhaps source/drain region 1008 also can be hoist type source/drain region (raised S/D).For pMOSFET, source/drain region 1008 can be formed by SiGe; For nMOSFET, source/drain region 1008 can be formed by Si:C.
As shown in Figure 2, for one embodiment of the present of invention, the outside of gate regions 1006 is formed with side wall 1020.
As shown in Figure 3, in another embodiment of the present invention, wherein the outside of gate regions 1006 directly contacts with dielectric layer 1012.In the embodiments of the invention side wall 1020 is removed, thereby gate regions 1006 can directly contact with dielectric layer 1012, embodiments of the invention can reduce the grid parasitic capacitance.
Below will combine Fig. 4-15 to describe manufacturing approach in detail according to the above-mentioned semiconductor device structure of the embodiment of the invention.
At first, as shown in Figure 4, Semiconductor substrate 1000 is provided.Wherein, substrate can comprise any suitable semiconductor substrate materials, specifically can be but is not limited to silicon, germanium, SiGe, SOI (silicon-on-insulator), carborundum, GaAs or any III/V compound semiconductor etc.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 1000 can comprise various doping configurations.In addition, substrate 1000 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen the property.
Then, utilize STI 1002 that Semiconductor substrate 1000 is divided into nMOSFET district 102 and pMOSFET district 104.Here it should be noted that for independent pMOSFET of formation or nMOSFET then not necessarily need form two device architectures simultaneously, independent pMOSFET or nMOSFET also belong to protection scope of the present invention.Fig. 4 only is one embodiment of the present of invention.
As shown in Figure 5, then on Semiconductor substrate 1000, form gate regions 1004 and source/drain region 1006.The method that forms gate regions 1004 can be on the entire semiconductor device structure, to form gate dielectric layer 1014 earlier, then on gate dielectric layer 1014, forms gate conductor layer 1016.Particularly, gate dielectric layer 1014 can be common gate dielectric layer, for example SiO
2, or the high-k gate dielectric layer, for example, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, any one or more the combination among the LaAlO.Gate conductor layer 1016 can be that conductive layer and polysilicon form, and also can only be formed by polysilicon, and the material of conductive layer can be metal or alloys such as Ti, Co, Ni, Al, W, or any other gate material.The composition of gate regions 1004 can be formed with reference to any existing or in the future possible grid, and the present invention does not limit this.
Then, on gate conductor layer 1016, apply photoresist, photoresist is carried out patterning form the grid pattern, be that mask carries out etching to gate conductor layer 1016 and gate dielectric layer 1014 with the photoresist behind the patterning, thereby form gate regions 1006 as shown in Figure 6.Embodiments of the invention are not limited thereto, with reference to Figure 12-13, also can an etching gate conductor layer 1016 in this step, and in the etching of side wall, just gate dielectric layer 1014 is carried out etching.
Then, the Semiconductor substrate 1000 of grid both sides is carried out source/leakage extend injection, alternatively, can also carry out the inclination angle ion and inject formation halo (Halo) injection region.These steps are optional step, and are not shown among Fig. 6.Then, all around gate district 1006 forms grid curb wall 1020.Particularly, on the entire semiconductor device structure, forming one deck dielectric layer earlier, for example can be Si
3N
4, follow selective etch Si
3N
4Thereby, form side wall 1020 in gate regions 1006 both sides.After side wall 1020 forms, in the outside of side wall 1020 Semiconductor substrate 1000 is carried out heavy doping ion and inject, thus formation source/drain region 1008.
After source/drain region 1008 forms, then below gate regions 1006, form channel region 1004.
After formation source/drain region 1008, preferably, above gate conductor layer 1016 and source/drain region 1008, form metal silicide and contact 1018.Particularly, can on the entire semiconductor device structure, form layer of metal,,, make these metals and Semiconductor substrate (for example Si) form metal silicide 1018, afterwards unreacted metal removed then through high annealing like W, Co, Ni etc.Metal silicide 1018 helps reducing contact resistance.
The method that embodiments of the invention form source/drain region is not limited thereto, and can after forming gate regions 1006, in time form grid curb wall 1020.As shown in Figure 7, after forming side wall 1020, be the boundary with the side wall, downward etching semiconductor substrate 1000, thus form groove 1022.Then, as shown in Figure 8, be brilliant source with the bottom and the sidewall of groove 1022, epitaxial growth source/drain region.For pMOSFET, epitaxial growth SiGe, thus compression is provided can for the channel region 1004 of gate regions 1006 belows; For nMOSFET, epitaxial growth Si:C, thus tension stress is provided can for the channel region 1004 of gate regions 1006 belows.In general, Ge content is 20-70% among the SiGe, and C content is 0.5-2% among the Si:C.Embodiments of the invention do not limit the generation type in source/drain region.
Behind formation source/drain region, on whole Semiconductor substrate structure, form one deck sacrifice layer 1024 (also can be described as second dielectric layer), thickness is about 70-300nm, as shown in Figure 9.The material of sacrifice layer 1024 can be the low k dielectric material, for example, and SiO
2, any or other materials among the SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG, BPSG.In an embodiment of the present invention, the material of sacrifice layer 1024 is not done particular determination, anyly can realize that material of the present invention may be used to the present invention, can preferably be easy to deposit and be easy to the material of etch material yet as sacrifice layer 1024.
Etching sacrificial layer 1024 then, thereby form contact hole 1026 therein, and in contact hole 1026, form metal closures 1010.Metal closures 1010 can be formed by materials such as W, Al, Cu, Al, TiAl or other material.
Then, as shown in figure 10, sacrifice layer 1024 is removed, for example can be adopted reactive ion etching (RIE).
As shown in figure 11, after removing sacrifice layer 1024, on whole semiconductor structure, form a ply stress dielectric layer or low k dielectric layer again as interlayer dielectric layer 1012 (also can be called first dielectric layer).The method that forms the stress dielectric layer is preferably plasma enhanced CVD (Plasma-enhanced CVD) or other deposit mode.The material of interlayer dielectric layer 1012 can comprise SiO
2, any or other material among the SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG, BPSG, in the present invention, preferably adopt Si
3N
4And to the top, promptly the bottom of metal closures 1010 is to the top around these metal closures 1010 and the bottom of running through metal closures for the stress dielectric layer, and stress dielectric material on every side is one-time formed.The character of stress can be controlled through the technological parameter in the forming process and realize.For pMOSFET, interlayer dielectric layer 1012 has compression, thereby compression is provided can for the channel region 1004 of gate regions 1006 belows; For nMOSFET, interlayer dielectric layer 1012 has tension stress, thereby tension stress is provided can for the channel region 1004 of gate regions 1006 belows.Such dual stressed films technology can improve mobility of charge carrier rate in the channel region greatly, improves device performance.
As shown in figure 11, so just accomplished a semiconductor device structure that obtains according to the embodiment of the invention.
In addition, for other embodiment of the present invention, when removing sacrifice layer 1024, can further side wall 1020 also be removed, so just form another semiconductor device structure that obtains according to the embodiment of the invention, concrete structure as shown in Figure 3.Because the removal of side wall has reduced the grid parasitic capacitance.
Below introduce through back grid (alternative gate) technology and realize method of the present invention.
At first the process according to Fig. 4-5 forms semiconductor device structure.Wherein gate conductor layer 1016 can select polysilicon to form, and uses as sacrificial gate.On gate conductor layer 1016, apply photoresist then, photoresist is carried out patterning form the grid pattern, be that mask carries out etching to gate conductor layer 1016 and gate dielectric layer 1014 with the photoresist behind the patterning, thereby form the gate regions of patterning.Embodiments of the invention are not limited thereto, also can etching gate conductor layers 1016 in this step, form structure shown in Figure 12.
Then, the Semiconductor substrate of grid conductor 1016 both sides is carried out source/leakage extend injection, can also carry out halo (Halo) alternatively and inject (not shown).As shown in figure 13, further form side wall 1020, carry out heavy doping and form source/drain region 1008.In forming the process of side wall 1020, when etching forms side wall with gate dielectric layer 1014 also etching.
The technology that above step and Fig. 6-8 describe can be replaced, and the present invention does not limit this.
As shown in figure 14, remove gate conductor layer 1016 (sacrificial gate), thereby form opening 1028 at the inwall of side wall 1020.
In opening 1028, form gate conductor layer 1016 ' then again, for example can form by metals such as Ti, Co, Ni, Al, W or alloy or other material.If gate dielectric layer 1014 is not to be formed by high k material, then forming gate conductor layer 1016 ' before, can further in opening 1028, form one deck high-k gate dielectric layer 1014 ' earlier, for example, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, any one or more the combination among the LaAlO.
So just formed structure as shown in figure 15.The process that forms sacrificial dielectric layer, metal closures and stress dielectric layer afterwards can be said with reference to above other embodiment, repeats no more here.
Embodiments of the invention can also compatible dual contact technology.As shown in figure 16, adopt above-mentioned method, form metal closures in the sacrifice layer kind earlier, remove sacrifice layer then, form stressor layers or low k layer again, thereby on source/drain region, form and the following metal closures 1010 of gate regions 1006 with high source/drain region.Then, as shown in figure 17, further deposit one interlayer dielectric layer 1028 again, and formed the last metal closures 1030 corresponding with following metal closures 1010.
The elder generation on Semiconductor substrate that proposes through the present invention forms sacrifice layer; In sacrifice layer, form metal closures; Remove sacrifice layer then and form the method for stress dielectric layer; The problem of having avoided the internal stress of the stressor layers of first formation to be weakened by the formation technology of follow-up metal closures; Thereby can strengthen the stress at channel region two ends, improve the mobility of charge carrier rate.Embodiments of the invention can adopt the low k dielectric material as interlayer dielectric layer, perhaps remove side wall, thereby can reduce the grid parasitic capacitance of device.In addition, this method is also applicable to the cmos device with lifting source/drain electrode structure, and can compatible back grid technique.In addition, this method can also be used in the dual stress film technology, improves the performance of device greatly, thereby makes application of the present invention more extensive.
Although illustrated and described embodiments of the invention; For the ordinary skill in the art, will be appreciated that range of application of the present invention is not limited to the technology of the specific embodiment of describing in the specification, mechanism, manufacturing, material composition, means, method and step.From disclosure of the present invention; To easily understand as those of ordinary skill in the art; For the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present; Wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, accompanying claims of the present invention is intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (21)
1. semiconductor device structure comprises:
Semiconductor substrate;
Channel region is formed on the said Semiconductor substrate;
Gate regions is formed on the said channel region;
Source/drain region is formed at said channel region both sides;
Metal closures contacts with said gate regions or source/drain region;
Dielectric layer forms around said metal closures, and from the bottom of said metal closures to the top, said dielectric layer is one-time formed.
2. semiconductor device structure according to claim 1, wherein, the material of said dielectric layer has stress, and for pMOSFET, said dielectric layer has compression, and for nMOSFET, said dielectric layer has tension stress.
3. semiconductor device structure according to claim 2, the material of wherein said dielectric layer comprises the low k dielectric material.
4. semiconductor device structure according to claim 2, wherein, the material of said dielectric layer comprises the stress nitride thing.
5. semiconductor device structure according to claim 1, wherein, said source/drain region is embedded in said Semiconductor substrate and forms; Or said source/drain region is hoist type source/drain region.
6. semiconductor device structure according to claim 5, wherein, for pMOSFET, said source/drain region is formed by SiGe, and for nMOSFET, said source/drain region is formed by Si:C.
7. semiconductor device structure according to claim 1, wherein, the thickness of said dielectric layer is 70-300nm.
8. semiconductor device structure according to claim 1 wherein, contacts with metal closures on only active/drain region, and said metal closures and height such as gate regions grade.
9. according to each described semiconductor device structure in the claim 1 to 8, the outside of wherein said gate regions directly contacts with said dielectric layer.
10. the manufacturing approach of a semiconductor device structure comprises:
Semiconductor substrate is provided;
On said Semiconductor substrate, form the side wall in the gate regions and the gate regions outside;
Both sides in said gate regions form source/drain region;
On said Semiconductor substrate with the corresponding formation of said gate regions or source/drain region metal closures;
On said Semiconductor substrate, form first dielectric layer so that the bottom of said metal closures to the top by said first dielectric layer around.
11. method according to claim 10, wherein, said gate regions is formed by sacrifice gates;
Then after forming side wall, said method further comprises:
Said sacrifice gates is removed in said side wall, to form opening; And in said opening, form replacement gate.
12. method according to claim 11 wherein, forms before the replacement gate in said opening, said method further comprises:
In said opening, form gate dielectric layer.
13. method according to claim 10 wherein, comprises with the corresponding formation of said gate regions and source/drain region metal closures on said Semiconductor substrate:
On said Semiconductor substrate, form second dielectric layer;
In said second dielectric layer,, and in said contact hole, fill metal formation metal closures with the corresponding formation of said gate regions or source/drain region contact hole;
Said second dielectric layer is removed.
14. method according to claim 13, wherein, only corresponding with source/drain region formation contact hole is filled metal and is formed metal closures in said contact hole, and the contact hole and the height such as said gate regions grade that form.
15. method according to claim 13, wherein said formation first dielectric layer comprises:
The using plasma chemical gas-phase deposition enhanced forms first dielectric layer with stress.
16. method according to claim 10, wherein, for pMOSFET, said first dielectric layer has compression, and for nMOSFET, said first dielectric layer has tension stress.
17. method according to claim 10, the material of wherein said first dielectric layer comprises the low k dielectric material.
18. method according to claim 10, the method that wherein forms source/drain region comprises:
The said Semiconductor substrate of etching forms groove in the outside of said side wall; And
Extension forms source/drain region in said groove.
19. method according to claim 10, wherein, for pMOSFET, said source/drain region is formed by SiGe, and for nMOSFET, said source/drain region is formed by Si:C.
20. method according to claim 10, wherein source/the drain region of Xing Chenging is a hoist type.
21. according to each described method in the claim 10 to 20, when removing said sacrifice layer, said method further comprises:
The side wall in the said gate regions outside is removed.
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| CN109037051A (en) * | 2018-07-24 | 2018-12-18 | 武汉新芯集成电路制造有限公司 | The preparation method and semiconductor structure of semiconductor structure |
| CN118073281A (en) * | 2024-04-19 | 2024-05-24 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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